Abstract: An operational amplifier in a bias voltage generator of a MOS current summing digital to analog converter corrects deviations in output current due to variations in drain to source voltages in current slaves caused by differing output resistances and supply voltages. Matching of MOS current sources uses an operational amplifier feedback circuit to create a controlled turn-on reference voltage used for biasing selected differential current paths so as to eliminate drain to source voltage variations in precisely ratioed current slave MOS transistors. One transistor of each differential current pair is enabled by a corresponding switch coupled to the turn-on reference voltage produced by the operational amplifier. In the preferred embodiment, the switches are CMOS transmission gates enabled by the binary digital input and its complement. Low voltage (3 volts) operation is achieved by having minimum number of stacked transistors between power supply voltages.

Abstract: A current memory cell comprises a first bipolar transistor providing a current source and coupled to the emitters of a second and a third bipolar transistor, the latter forming the storage elements of the memory cell. The memory cell is calibrated, to avoid mismatch between the second and third transistors, by adjustment of the current source via a parallel arrangement of a resistor and a field effect transistor in the emitter circuit of the first transistor.

Abstract: A digital to analogue converter having a plurality of output stages 46. Each output stage 46 includes a tri-state buffer 54 that outputs an on-signal, an off-signal or a pulse width modulated signal PWM that is selected by a multiplexer 52 that operates under control of a chord decoder 50 that is responsive to exponent bits within the input digital signal value. If a pulse width modulated signal is selected, then its duty cycle is controlled by a pulse width modulated decoder 48 that is responsive to mantissa bits within the input digital signal value. A further output provides a pulse width modulated signal of a predetermined duty cycle that may be used as a reference signal to compensate for variations in the operation of the rest of the digital to analogue circuit.

Abstract: A Digital-to-Analog (D/A) converter with programmable transfer function includes a Main Converter and at least one Sub-Converter. Errors in the Main Converter are compensated for by programming the one or more Sub-Converters with compensation values determined during a Calibration Sequence. The Calibration Sequence measures the deviations of the transfer function of the Main Converter from the ideal at predetermined bit transitions of the digital input signal and generates representative separate digital signals for the one or more Sub-Converters. By combining these separate signals with the digital input signal, the net errors of the D/A Converter transfer function are reduced.

Abstract: A D/A converter of a current output type desirably compensates for changes in the switching characteristic that arise in each constant current circuit. The D/A converter generates an analog output current that is in response to the level of input digital data and outputs it from an output side by switching each of output currents of a plurality of constant current circuits either to the output side or to a non-output side, in response to the input digital data. The D/A converter performs feedback control, for values of the output currents for the constant current circuits, based on an analog output current at the non-output side during a period when the output currents of all of the constant current circuits are connected to the non-output sides.

Abstract: An N bit (where N is an integer) converter having separately formed voltage dividing resistance regions includes a semiconductor substrate of a first conductivity type. (N+1) well regions of a second conductivity type are each formed separately on the semiconductor substrate and an input resistance region of the first conductivity type having a high concentration of impurities is formed in a first well region of the (N+1) well regions. (N-1) ladder resistance regions of the first conductivity type having a high concentration of impurities respectively are formed in (N-1) well regions, each resistance of the (N-1) ladder resistance regions being approximately two times greater than a resistance of the input resistance region. An output resistance region of the first conductivity type having a high concentration of impurities is formed in an (N+1)th well region of the (N+1) well regions, a resistance of the output resistance region being approximately equal to the resistance of the input region.

Abstract: An analog memory unit that can be implemented, at least in part, on an application specific integrated circuit (ASIC), utilizes at least the ASIC arithmetic logic unit (ALU) to enhance performance and to generate and store an accurate measure of power line thermal status. The memory unit includes an analog-to-digital (A/D) converter for converting an input analog signal from a parallel R-C circuit to a digital signal and a scaler for scaling the digital signal from the A/D converter to within a range acceptable for further processing. The memory unit also includes an arithmetic logic unit (ALU) which receives input signals from the scaler and from a digital thermal memory. The input signal supplied to the ALU from the digital thermal memory is a four bit (digital) value proportional to the measured actual thermal status of the subject power line. The output of the ALU is connected to the input of latches which latch, or store, the digital signal produced by the ALU.

Abstract: A DAC converts a sequence of digital codewords into an approximately piecewise linear analog waveform that follows rising and falling edges between plateau levels. The DAC processes, in parallel, each bit of the codewords to produce component waveforms that are weighted according to their bits significance and summed together to produce the piecewise linear analog waveform. Waveform shaping circuits control the rise and fall times of each component waveform so that the analog waveform's rising and falling edges settle to within a desired error bound of a linear output ramp whose slope is a function of the difference between successive codewords and the rise or fall times. The rise and fall times are preferably approximately the same. Limiting switches control the plateau levels of the component waveforms so that the analog waveform's plateaus settle to within the desired error bound of the ideal values represented by the codewords.

Abstract: A device for testing for disconnection of bus lines of a semiconductor device includes switches having current ratios formed in a geometric series connected to ends of a group of n of the bus lines. At least one testing electrode is connected to the switches and at least one power electrode is connected to the group of n of the bus lines. A disconnection of one or more of the bus lines can be determined according to a current flowing through the testing electrode.

Abstract: A digital-to-analog converter including a plurality of binarily-weighted stages each incorporating a differential switch-pair circuit which includes two matched bipolar switch transistors the bases of which are driven by a corresponding pair of complementarry signal sources. Two additional switches are included in this circuit, with each such switch being connected between a respective signal source and its corresponding transistor control electrode. These two switches are both opened before the clock-controlled activation of the complementary signal sources. A short time after such activation, sufficient to assure that the complementary signal voltages have stabilized at their new values, the two additional switches are reclosed simultaneously by a single control signal so as to effect synchronized switchover of the two switch transistors at that instant.

Abstract: An analog-to-digital converter circuit is disclosed that is capable of converting both positive and negative analog input signals, and that is capable of operating as either an analog-to-digital converter or a digital-to-analog converter. The converter includes a modifying filter, a series of substantially identical converter stages, and a restoring filter. An original reference signal is provided, coupled to a resistor array to provide a stage reference signal to each converter stage that is equivalent to the value of the bit of an N-bit binary word corresponding to that stage. An incoming analog signal is modified to ensure that it is positive before applying it in parallel to the converter stages. Each converter stage compares the modified analog signal to the sum of its own reference signal and the value of all stage reference signals for prior converter stages where the digital output of the stage was a binary "1.

Abstract: A D/A converter having a bias circuit that supplies a well-compensated gate voltage to a weighted current source part of the D/A converter, so that any changes in component characteristics due to the manufacturing of the components making up the D/A converter or due to temperature variations in the D/A converter are compensated for to output a correct analog voltage. The bias circuit comprises an amplifier and a p-type FET, where the drain of the p-type FET is fed back to a non-inverting input of the amplifier, and a reference voltage is applied to an inverting input of the amplifier. The bias circuit operates in a negative feedback condition, such that the non-inverting input is kept as close to the reference voltage as possible. A first resistor is connected to the drain of the p-type FET, to determine the current at the drain of the p-type FET. The weighted current source is made up of FETs having similar operating characteristics as the p-type FET of the bias circuit.

Abstract: A digital to analog converter which includes a delta-sigma modulator for transforming the lower n bits of an input digital signal of N bits by delta-sigma modulation; first and second signal output devices for outputting first and second signals which are used for selecting current cells of a current cell array according to the higher bits and the higher bits+one LSB of the input digital signal, and a selector for selecting either of the first and second signals in accordance with the change of the output of the delta-sigma modulator. A filter is provided for smoothing the total of the currents output from the current cells which are in the output state corresponding to the first or second signal selected by the signal selector.

Abstract: A multi-stage digital to analog converter with increased speed and enhanced accuracy. Multiple resistor ladders are interconnected through switches with the first resistor ladder converting the most significant bits and successive ladders converting lesser significant bits. The resistance values of the resistors of each ladder are greater than those of the preceding ladders in order to minimize inaccuracies due to loading. A monolithic fabrication technique includes a common resistor biasing scheme to switch the voltage across parasitic capacitances associated with the resistors in each ladder in common mode, thereby increasing the converter speed.

Abstract: Disclosed is a system and method for providing full monotonicity among desired sequential output values by converting a stream of sequential input signals each of which are representative of their corresponding desired output values. The disclosed invention comprises a system and method for individually translating each received signal to a unary value, the unary value being representative of a desired output value, and a system and method for selectively enabling a plurality of energy sources as a function of this unary value such that the total of any enabled energy source at any one time is proportional to this unary value. The conversion circuit uses a shifting array for controlling the energy sources.

Abstract: A digital-to-analog converter having a ladder resistor portion for generating a plurality of quantization signals of predetermined values based on reference signals of predetermined values and a quantization switch portion for selectively outputting one of the quantization signals in accordance with a digital input value. The ladder resistor portion is coupled to at least one resistor for generating a signal of a value which corresponds to a desired signal level of a signal to be added. A switch provided for supplying the signal of the value corresponding to the desired signal level to an output of the switch portion in response to a timing signal synchronized with the signal to be added.

Abstract: An n-bit analog processing circuit constructed with network swappers has n stages and an input port for inputting an analog signal to be processed. Each of the n stages includes first and second reference input ports, at least one swappable network having first and second terminals, and a switching element that is responsive to a digital input signal for varying a connectivity of the first and second terminals with respect to the first and second reference input ports. Each of the n networks has a primary electrical characteristic that is binarily weighted with respect to others of the networks. The primary electrical characteristic may be resistance, capacitance, capacitive reactance, inductance, inductive reactance, voltage potential, gain, transconductance, superconductance, time delay, permeability, electrical or optical conductor length, and/or winding turns.

Abstract: The number of current sources and switches necessary for a plurality of unit D/A converters using equal reference currents, are drastically reduced to reduce the parasitic capacitance coupled to current output lines, by converting a plurality of digital signals of a predetermined bit, which are divided from an input digital signal, into an analog current unit D/A converters and by converting the analog current in a manner to correspond to the weights of the corresponding input digital signals, thereby to synthesize the currents. The fixed reference digital signal is inputted to the D/A converter for cancelling offsets. The offsets of a plurality of analog output signals in positive and opposite phases obtained by branching the output of the D/A converter are individually detected. After this, the DC offset values of the individual analog outputs are used as offset adjusted negative feedback signals for a desired value.

Abstract: A digital-to-analog conversion device that has one or more conversion cells, each cell coupled to a master voltage source and to a specific binary input element. The conversion cells include binary-weighted or binary-sized output transistors such that each output transistor, when called upon, delivers a unique analog output current corresponding to a particular binary signal. The master potential provided by a stable source is supplied to the control nodes of the output transistors so that the potential at those control nodes remains constant. Switching on and off of the output transistors is achieved by regulating the sources of those transistors rather than their gates. By regulating the operation of the output transistors at their sources, the present invention provides a digital-to-analog converter and a conversion method with little switching noise and minimal switching delay.

Abstract: The number of resistors and switches required for a voltage-scaling digital-to-analog converter (DAC) is greatly reduced by segmenting the voltage decrementing resistor string into two separate outer strings and an inner string. The outer strings decrement a full-scale voltage in accordance with the most significant bits (MSBs) of the input digital signal, while the inner string decrements the least significant bits (LSBs); alternately, the outer strings can decrement the LSBs and the inner string the MSBs. Opposite ends of the inner string are connected to corresponding points on the two outer strings through passive switched taps on the outer strings that allow the DAC to function as a potentiometer or rheostat, and "slide" up and down along the two outer strings as the input digital signal varies. An analog output is tapped from a selected point on the inner string whose voltage elevation is controlled by the switching of the outer strings.

Abstract: A digital/analog converter with a weighted capacitive converter network is provided with weighted stray capacitors for reducing non-linearities in switching. Additional stray capacitors are connected in parallel to the otherwise present stray capacitors for that purpose. In the higher-value network capacitances, the additional stray capacitors are positive, in the lower-value network capacitances, the stray capacitors are effective, i.e. their effect is negative. The converter is constructed differentially in its entirety. The combination allows the optimization with regard to the chip surface.

Abstract: A digital-to-analog converter including a plurality of binarily-weighted stages each incorporating a differential switch-pair circuit which includes two matched bipolar switch transistors the bases of which are driven by a corresponding pair of complementary signal sources. Two additional switches are included in this circuit, with each such switch being connected between a respective signal source and its corresponding transistor control electrode. These two switches are both opened before the clock-controlled activation of the complementary signal sources. A short time after such activation, sufficient to assure that the complementary signal voltages have stabilized at their new values, the two additional switches are reclosed simultaneously by a single control signal so as to effect synchronized switchover of the two switch transistors at that instant.

Abstract: A digital-to-analog converter has a bias block that provides first and second voltage outputs, and a bit cell having a switch for selectively connecting either a first or a second summing node to a current flow path depending upon the state of a binary input signal. An output bipolar transistor and a current source are connected in series between a supply voltage and a reference potential. A first MOS transistor is connected in the current flow path with its gate connected to the bipolar transistor. A base current compensating second MOS transistor is connected between the supply voltage and a base of the output bipolar transistor with its gate connected to the first voltage output of the amplifier. A resistor is connected between the base of the output bipolar transistor and the second voltage output of the amplifier. When a plurality of bit stages are provided, the resistor of each of the plurality of bit cells is sized according to a position of its associated cell in the bit order.

Abstract: A switched capacitor circuit includes a first capacitor (102) connected between first and second nodes (101, 103), a second capacitor (C.sub.1) connected between the first node and an intermediate node (M), and a third capacitor (C.sub.2) connected between the intermediate node (M) and ground. A group of m parallel circuits are connected between the intermediate node and the second node. Each of the m parallel circuits has a fourth capacitor (C.sub.V) and a switch (D.sub.V) for coupling it to ground or to the second node (103) depending on a corresponding one of m bits of an N-bit gain control signal. (N-m) parallel circuits are connected between the first and second nodes, each including a fifth capacitor and a switch for charging it depending on one of (N-m) bits of the N-bit gain control signal. A first sampling switch (S.sub.1) couples an input voltage to the first node (101) in response to the first phase of a two-phase clock signal and coupling the first node to ground in response to the second phase.

Abstract: A system on an integrated circuit chip for providing a digital-to-analog conversion includes a plurality of output members each providing a particular current when energized. These members may be disposed on the chip in a pair of spaced columns. First control lines in the space between the columns of output members provide a thermometer code. Second control lines in this space provide a binary code. The first and second control lines are preferably parallel to the columns. When a first one of the first control lines is energized, different ones or combinations of the second control lines provide progressive values in the output members between "0" and "15", assuming four (4) of the second control lines. Similarly, when a second one of the first control lines is additionally energized, different ones or combinations of the second control lines provide progressive values between "16" and "31" in associated output members. At the same time, the output members providing a value of "15" continue to be energized.

Abstract: A digital-to-analog converter of a current addition type using weighted resistors, includes an input resistor network (4) for providing a resistance dependent on a digital input signal having a predetermined number of bits, and an adder (3) having a first input terminal coupled to the input resistor network and a second input terminal connectable to receive a reference potential, for adding a signal obtained at the first input terminal and the reference potential. The adder also has an output terminal via which a result of an adding operation is output, and the result of the adding operation shows an analog signal corresponding to the digital input signal.

Abstract: A digital-to-analog converter (10) uses series-connected resistors (55-59) to implement conversion of most significant bits of a digital input signal to an equivalent analog output signal. Current sources (22-26) are used to implement conversion of least significant bits of the digital input signal to the analog output signal. After making a binary-to-thermometer code conversion of the least significant bits, first logic circuitry (70) provides control signals (SI) for controlling the switching of each of the current sources to either a first (42) or a second (44) node. After making a binary to `one of` code conversion of the most significant bits, second logic circuitry (86) provides control signals (SR) for respectively switching the first and second nodes to any two resistor nodes of the resistors. The resistors are connected between a reference voltage terminal and a third node where the analog output signal is developed.

Abstract: A non-impact printhead, for example one that includes a plurality of LEDs, is driven by a current that is programmed to have a linear temperature profile with a desired slope. The change in current with temperature facilitates maintaining of LED uniformity. Linearity between various stages of driver circuitry is maintained by a digital-to-analog converter that includes transistors arranged in a common centroid configuration. Driver current to each LED is provided by a master slave circuit that is dedicated to each LED. Thus, cross-talk between LED channels is minimized.

Abstract: A modified sign-magnitude DAC includes first internal DAC circuitry including a first number of bit switch circuits responsive to an input word including a sign bit and a digital data word. Each bit switch circuit is coupled to a corresponding current source transistor. Second internal DAC circuitry includes the same number of bit switch circuits responsive to the input word. Each bit switch circuit of the second internal DAC circuitry is coupled to a corresponding current source transistor. The same number of binarily weighted bit current determining resistor circuits corresponding to bits of the digital data word are connected to a reference voltage conductor. The emitter of the current source transistor of each bit switch circuit of the first internal DAC circuitry is coupled by a first gain balancing resistor to the corresponding bit current determining resistor.

Abstract: A segment control type D to A converter includes a decoder and a plurality of current source cells. The decoder decodes a digital input signal to generate a control signal. The plurality of current source cells are selected by the control signal output from the decoder. A current output from the selected current source cell is output from an output terminal. Each of the current source cells includes first and second transistors. One terminal of the current path of the first transistor is connected to a constant current source, and the first transistor is ON/OFF controlled such that the gate of the transistor receives the control signal output from the decoder. One terminal of the current path of the second transistor is connected to the other terminal of the current path of the first transistor, and the other terminal of the second transistor is connected to the output terminal.

Abstract: A low-noise switched-capacitor DAC converts an integer number from an N-bit digital format into an analog voltage level by transferring charge between two appropriately ratioed capacitors using a plurality of switches. The switches select only an appropriate one of a plurality of capacitors to connect to an operational amplifier in accordance with any digital input. The sampled kT/C noise and switch charge injection from an N-bit DAC is thus beneficially reduced.

Abstract: A current generating device for generating two different currents having different magnitudes in response to corresponding one-bit data of digital data of a plurality of bits includes: NMOS transistors, (1,2,3), a control signal generating circuit and a supply circuit. The control signal generating circuit generates a voltage (V2) at which NMOS transistors (2,3) can be turned on and a voltage (V3) which is in the range between a ground potential and threshold values of the NMOS transistors and at which NMOS transistors (2,3) can be turned off. The supply circuit complementarily applies voltages (V1,V2) to NMOS transistors (2,3). NMOS transistor (1) generates a current with a predetermined magnitude. NMOS transistors (2,3) respond to voltages (V2, V3) to switch and allow/prevent passage of the predetermined-magnitude current generated by NMOS transistor (1).

Abstract: A multiplying digital-to-analog converter for multiplying a bipolar input current by a digital word A having N bits a.sub.i including a current adder for adding a constant current to the bipolar input current to produce a unipolar current, a first current mirror responsive to the unipolar current for providing N binary weighted versions of the unipolar current, a second current mirror for providing binary weighted versions of the constant current, N current selection circuits respectively controlled the N bits a.sub.

Abstract: An interpolation DAC includes first and second registers connected to receive the X least significant and Y most significant bits of a digital input word, and are clocked to latch the X least significant bits and Y most significant bits at a first clock rate. An adder has a first group of X inputs, a second group of X inputs, X outputs, and a carry output. A third register has X inputs, and X outputs coupled to the second group of X inputs of the adder. The third register is clocked to latch the outputs of the adder at a second clock rate which is the oversampling ratio times faster than the first clock rate. A Y bit plus 1 bit DAC in which the 1 bit is a duplicate of the least significant of the Y bit section has its most significant Y bits coupled to receive the outputs of the second register. The duplicate LSB is connected to receive the carry output from the adder. A low pass filter responsive to the Y bit plus 1 bit DAC produces an analog output representative of a value of the digital input word.

Abstract: An apparatus for converting the sum of m digital signals to an analog signal utilizing resistors and switches only. The operating time of the apparatus is the time required to pass the signal through a single switch. This invention can also be utilized in an A/D converter for converting the difference between an analog signal and several digital signals to a digital signal without using extra time to compute the subtraction.

Abstract: A plurality of segment groups constituting a D/A converter, and decoders for decoding digital signals and selecting segments constituting the segment groups are arranged on a semiconductor chip. The segments constituting the plurality of segment groups are mingled and two-dimensionally arranged. The positions of the centers of gravity of the respective segment groups are substantially matched with the center of the arranged segments.

Abstract: A digital-analog converter circuit comprising a current output type digital-analog converter and a current/voltage converter connected to an output terminal of the current output type digital/analog converter, the current/voltage converter including bias application means to always apply a bias voltage having a predetermined set value to the output terminal of the digital/analog converter.

Abstract: A DAC embodied in a CMOS integrated circuit converts a multi-bit digital signal to an analog-current signal. A higher-order portion of the digital signal, e.g., the most significant 5 bits of a byte, are decoded separately from the lower-order portion, e.g., the 3 least significant bits. The DAC includes circuitry for producing a first bias voltage, a first set of current sources each biased by the first bias voltage to produce a switchable current having a unit magnitude, and switching circuitry controlled by the decoded lower-order portion to cause a selected number of the unit-magnitude currents to contribute to the analog-current signal.

Abstract: A digital-to-analog converter of the resistor string type comprises a string of resistors for dividing a reference voltage into a series of divided voltages, and a switch matrix circuit for selectively generating the divided voltages as an analog signal when activated in response to a digital signal. The string of resistors are divided and folded into four square arrays, one pair of the four square arrays being arranged diagonally to the other pair of the four square arrays respectively. The switch matrix circuit includes four switching circuits for generating respective ore divided voltages from the four square arrays when activated respectively, and four decoder circuits for activating the four switching circuits in response to the digital signal respectively and for generating the respective one divided voltages from the four switching circuits in relation to a portion of the digital signal respectively.

Abstract: An electrical circuit (30) corrects for the presence of noise current and current drift in the currents developed by each current source transistor Q.sub.0, Q.sub.1, Q.sub.2, Q.sub.3, . . . Q.sub.n in a current source array. The electrical circuit corrects for the presence of noise current and current drift by simultaneously inducing in each current source correction currents whose values sum to cancel the current drift and noise. A noise suppression circuit includes an amplifier having an open loop gain, A.sub.v, which is configured to adjust the magnitudes of the multiple currents in response to the introduction of a noise current, i.sub..delta., in any one of the currents. The adjustment substantially cancels i.sub..delta. and thereby substantially reduces the presence of i.sub..delta. in the output current. The presence of i.sub..delta. in the output signal is substantially equal to i.sub..delta. /(1+A.sub.v).

Abstract: Signal conversion apparatus transforms an input signal having a value falling in one of a plurality of ranges into an output signal whose value varies for each different range. All of the output signal values corresponding to the plurality of ranges form an ordered set. The output signal values in this set are related to one another such that the value of any output signal is equal to the immediately preceding output signal value multiplied by a predetermined factor which is a constant for at least a plurality of consecutive output signal values. Use of such a relationship between output signal values advantageously reduces quantization errors in certain telecommunications applications and can be embodied within analog-to-digital, digital-to-analog and digital-to-digital signal conversion apparatus.

Abstract: A DAC includes a simple width-scaled weighted array (104) of N number of current sources and a weighted cascode current divider (108) comprised of m number of current sources. The simple width-scaled weighted array conducts N first scaled currents (I.sub.0 -I.sub.3), the array including N first transistors (116a-116d) connected to different ones of N second transistors (112a-112d), one of the N second transistors (112d) having a gate width w. The weighted cascode current divider includes M current sources, the current divider including M third transistors (120a-120d) that conduct M second scaled currents (I.sub.4 -I.sub.7) which are summed at a node (134). The node is connected to a master current transistor (138) that conducts a current I.sub.S and has a gate width w.

Abstract: A self-calibrating A/D and D/A converter operating according to the principle of charge redistribution includes a weighted capacitive primary converter network for most significant bits, a subsidiary converter network for bits of lesser significance, and a calibration and correction network. Each of the networks have capacitors. A comparator has an input connected to a node point. The capacitors of the primary converter network are each connected to the node point. A coupling capacitor is connected between the capacitors of the subsidiary converter network and the node point. Another coupling capacitor is connected between the capacitors of the calibration and correction network and the node point.

Abstract: A self-calibrating A/D and D/A converter operating according to the principle of successive approximation includes a weighted converter network, a calibration and correction network, network elements and switches associated with the network elements. A control configuration controls the converter network and the calibration and correction network through the switches for performing a conversion and correction phase as well as a calibration phase. A comparator feeds the converter network and the calibration and correction network back to the control configuration. The control configuration includes a single successive approximation register for controlling the converter network and the calibration and correction network in a multiplex mode.

Abstract: A calibration method for redundant A/D and D/A converters with a weighted network and error correction includes performing a self-calibration in which each of n weighted elements is determined as a function of respectively lower weighted elements by means of a measurement with n steps, except for a lowest weighted element. Subsequently each weighted element is calculated and stored in memory in terms of the sum of all of the weighted elements as a function of the results of the measurement with the aid of a calculating register.

Abstract: A digital/analog converter designed for very high frequencies is described. It has a first stage, which is a standard stage, in which several parallel-mounted controllable loads deliver currents in geometrical progression in a current/voltage converting transistor. Each controllable load has an input transistor, to the gate of which a bit is addressed as well as a diode and a saturable resistor. The second stage is a shifter formed by a transistor mounted as a follower source, in series with at least one diode and one pull-back transistor, the source of which is at a negative potential. The voltage at the drain of the converting transistor is applied to the gate of the shifter transistor, and the output voltage at the drain of the pull-back transistor is looped to the gate of the converting transistor.

Abstract: In digital-to-analog converters with "rotating" current sources for converting an n-bit binary signal to an analog output signal, a single cyclic shift register is replaced by m cyclic shift register portions each having p=(2.sup.n -1)/m inputs, and the n-digit binary signal to be converted is changed into the thermometer code by means of a code converter. The middle output of the code converter and equal numbers of code converter outputs on both sides thereof are connected to one of the shift register portions. According to the same rule, the code converter outputs located further from the middle are connected to the other shift register portions. Thus, a clock signal serving as a shift signal for the shift register portions only needs to have a frequency which is p times that of the sampling signal with which an, e.g., analog, audio signal is digitized.

Abstract: A multiplying digital to analog converter using ladder networks and binary weighted load compensation to allow integration and video frequency operation. In one form, the circuit is configured from field effect transistors which incorporate by virtue of their structural and operational characteristics both the switching and resistive functions of R-2R ladder networks. The circuit is used to convert digital format words representing intensity and color (red, green and blue) into analog red, green and blue display drive signals. According to that configuration, the output of the digital to analog intensity word converter serves as the reference for the three digital to analog color word converters. Loading effects attributable to differences in the bit content of the color words are offset by a binary weighted switched load which is responsive to a digital compensation word. The switched load is also connected to the output of the intensity word converter.

Abstract: A digital-to-analog converter (DAC) ladder segment is disclosed in which diode networks are introduced into the ladder step circuits. Each diode network includes a control diode which controls the flow of current through the network in accordance with a signal from an associated actuating circuit, which in turn is controlled by an input digital signal. In one embodiment, the control diodes are connected in series with resistors, with the diodes and resistors scaled so that their respective bit circuits conduct desired current levels. In another embodiment, the control diodes have equal scalings and are connected in series with respective resistors and second diodes which are called so that their step circuits conduct the desired currents. In a third embodiment, current sources are provided which supply currents to the second diodes in amounts that permit the second diode and the resistors for the various step circuits to have substantially equal scalings.

Abstract: A digital-to-analog converter for converting a digital signal having a word length n into an analog signal. The converter includes at least two switched capacitor integrators (1, 2) arranged in series and a control unit (18) for applying control signals to the integrators which perform an integration step under the influence of the control signal. Each integrator is provided with a capacitor network (11, 12) having at least two capacitors (27.1, 27.2, . . . ; 28.1, 28.2, . . . ) coupled between the input (13; 4) of the integrator and the inverting input (-) of an associated amplifier stage (5; 6). A capacitor (9; 10) is coupled between the inverting input (-) and the output (7; 8) of this amplifier stage. The control unit is adapted to apply, in this order, a first control signal to the first integrator (1), a second control signal to the second integrator (2), a third control signal to the first integrator and a fourth control signal to the second integrator.