Abstract: Techniques are disclosed for improving the dynamic performance of digital-to-analog converters (DAC), by compensating for the unique delay characteristics of each bit in the DAC summing junction to equalize the delays. In one example case, a DAC device is provided that includes a plurality of current sources and a plurality of switches, each switch operatively coupled between a corresponding one of the current sources and a summing junction that is operatively coupled to an analog output. The device further includes a plurality of switch control lines configured to receive a digital input, each switch control line for controlling a corresponding one of the switches. The device further includes a plurality of compensation delay elements, each associated with a corresponding one of the switch control lines and providing a different delay value.

Abstract: A digital analog converter has an input terminal receiving a digital input signal, a lower-side capacitor group coupled to a lower-side common terminal in parallel, an upper-side capacitor group coupled, in parallel, to an upper-side common terminal at which an analog output signal is generated, a coupling capacitor provided between the lower-side common terminal and the upper-side common terminal, a switch group coupled to the upper-side capacitor group and the lower-side capacitor group and controlled as a conduction state and a non-conduction state in accordance with the digital input signal, and an adjusting capacitor coupled to the lower-side common terminal and having a variable capacitance value.

Abstract: A current output type digital-analog conversion circuit which outputs a current signal includes a decoder for decoding higher-order bits of input digital data, a plurality of binary current generators, and a current adder. Each of the binary current generators includes a device for outputting a binary current which increases linearly as binary values according to lower-order bits of the input digital data, and a device for outputting a predetermined all-ON current. Either the device for outputting the binary current or the element for outputting the all-ON current of the binary current generator is selected according to a decode signal output by the decoder. The current adder adds up and outputs the binary currents and the all-ON currents output by the plurality of binary current generators.

Abstract: A parallel digital-analog converter for the conversion of a plurality of differential digital input signals into a differential analog output signal, including a group of 1-bit digital-analog converters (200) which respectively include an intermediate storage cell (202) and a current cell (201) and which are adapted to feed a respective output current to a first (204) or a second output contact (206) in dependence on a logic state of the intermediate storage cell, wherein a first of two outputs of an intermediate storage cell (202) is connected by way of an input resistor (220) to a first signal terminal (208.1) of a first transistor (208) and a second of the two outputs of the intermediate storage cell (202) is connected by way of an input resistor (218) to a first signal terminal (210.

Abstract: In accordance with at least some embodiments, an electronic device comprises a digital-to-analog converter (DAC) having a DAC element array. Reference-rotated data weighted averaging (RRDWA) is applied to the DAC element array.

Abstract: A high power digital to analog converter (DAC) includes (a) an array of n bipolar transistors arranged in a binary sequence, (b) a depletion mode FET and (c) an array of n switches. The collector terminals of each bipolar transistor in the array are tied together. Furthermore, the depletion mode FET includes a source terminal which is directly connected to the collector terminals of each bipolar transistor. The FET also includes a gate terminal connected to a ground potential, and a drain terminal. Each bipolar transistor is sized to be a factor larger than its preceding transistor in the array of n bipolar transistors, for example, twice as large. The array of n switches is controlled by a digital word of n bits. Each of the n switches selectively activates a respective bipolar transistor in the array of n bipolar transistors. As the n switches are selectively activated, the array of n bipolar transistors provides n binary weighted collector currents in the source terminal of the FET.

Abstract: A variable resistor is connected to each terminal of (2^n)?1 resistors R connected in series. The variable resistors have resistances RH and RL determined according to a digital signal containing m lower bits LoB<m?1:0>.

Abstract: A system and method for performing phase-locked loop is disclosed. The system includes phase frequency detector circuitry, charge pump circuitry having first current mirror circuitry and second current mirror circuitry, loop filter circuitry, and voltage controlled oscillator circuitry. The phase frequency detector circuitry generates an up signal and a down signal based on the phase difference of an input signal and a feedback signal. The charge pump circuitry includes the first current mirror circuitry and the second mirror circuitry and generates a charge pump output signal based on the up and down signals. The loop filter circuitry generates a filtered control signal based on the charge pump output signal. The voltage controlled oscillator circuitry generates the feedback signal with a repeating waveform based on the filtered control signal.

Abstract: A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.

Abstract: A digital to analog converter (DAC) includes a pair of operational amplifiers each having a first input coupled to a respective high or low reference voltage. The DAC includes a plurality of switch-controlled cells, each of which includes a resistor and two force/sense switch pairs. Within each cell, all four switches are coupled to the resistor. A first force switch is coupled to an output of a first op amp and an associated sense switch is coupled to an inverting input of the first op amp. A second force switch is coupled to an output of a second op amp and an associated sense switch is coupled to an inverting input of the second op amp. Thus, the force switches provide selectively conductive paths to permit either op amp to drive a given cell.

Abstract: A digital-to-analog converter including includes a decoder which receives m (where m>=4 holds) reference voltages having voltage values that differ from one another, and selects and outputs n (where n>=3 holds) identical or different voltages from among the m reference voltages based upon a digital signal; and an amplifying circuit that outputs a voltage, which is obtained by taking the weighted mean of the selected n voltages at a ratio of 2n?1:2n?2: . . . :20, from an output terminal.

Abstract: A digital-to-analog converter circuit layout includes a ratiometric digital-to-analog converter. The ratiometric digital-to-analog converter includes a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module. The a digital data input, a converter voltage output, a voltage controlled oscillator, and a pulse width modulation module is configured in a controllable manner for converting digital data received at the input to a converter output voltage at the output using a reference voltage, an adjustable current as a reference current, and an adjustable impedance value. The circuit layout is characterized in that the voltage controlled oscillator includes circuit components which multiply the reference voltage by a quotient between the adjustable impedance value and the adjustable current, and which apply the multiplication results to the pulse width modulation module.

Abstract: In a current switch circuit A used for a current steering D/A converter, a current switch basic circuit 1 includes first and second transistors Tr121 and Tr122 included in a differential switch 12. A threshold voltage control circuit 5 has an output terminal Vbout controlling the substrate voltage to be outputted to the substrate terminal of each of the two transistors Tr121 and Tr122 included in the differential switch 12 for controlling the threshold voltage of the two transistors of the differential switch. Accordingly, the present invention improves the decrease in the dynamic range of the current switch basic circuit 1 dependent on the threshold of each of the two transistors in the differential switch 12 and realizes a wider output voltage range without causing deterioration in properties even in a case that the power voltage is reduced in the current switch basic circuit 1.

Abstract: Embodiments relate to a current cell circuit in a digital-analog converter. According to embodiments, a current cell circuit in a digital-analog converter may include a current source connected to a power voltage terminal to generate current having a predetermined magnitude, a first current switch transferring current provided from the current source to a first output terminal, a first current generator detecting output voltage from the first output terminal and generating the amount of reduced current from the detected voltage, and a first current supplier supplying the amount of current generated from the first current generator to the first current switch. According to embodiments, current variations at a constant output voltage may be minimized. This may make it possible to obtain more stable frequency characteristics.

Abstract: A video driver includes a current-to-voltage converter circuit that converts an analog input current to a corresponding analog voltage. Active termination circuitry is configured to synthesize an output impedance at an output thereof that substantially matches a load impedance to which the output is coupled, the active termination circuitry buffering the analog voltage to the output.

Abstract: Methods and systems to provide dynamic element matching (DEM) in multi-phase sample systems include multiple uncorrelated, dual data weighted averaging, dynamic element matching (DDWA DEM). DDWA DEM may be implemented in a multiple-phase sample system in which sample paths and feedback paths share capacitances. Compensation feedback is apportioned amongst corresponding banks of capacitive sample circuits to utilize the capacitive sample circuits within each bank substantially equally over multiple sample cycles. The apportioning is substantially un-correlated between banks, which may reduce in-band quantization noise folding. DDWA DEM may be implemented within a digital-to-analog converter (DAC), in a delta-sigma modulator.

Abstract: A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature.

Abstract: A display panel driver including a binary-weighted current-type D/A converter and a source follower with current mirror is provided. The binary-weighted current-type D/A converter receives n input signals and sends a D/A output voltage signal based on 2n?1 times a reference current. The source follower with current mirror receives the D/A output voltage signal and sends 2n?1 times the reference current to the output of the source follower with current mirror, so as to output a output voltage and drive the display panel.

Abstract: A method and a system are disclosed for transmitting an N-bit digital signal at a source. The N-bit digital signal representing a binary value is used to modulate an electrical current by using N discrete voltages representing each bit. The N discrete voltages are coupled to N corresponding switches to control the switches. The switches conduct a corresponding electrical current if the value of the corresponding discrete voltage is the binary value of 1. The currents from each of the closed switches are summed to form a current-encoded data signal in a single physical conductor representing the original N-bit digital signal. The current-encoded data signal is transmitted through the single physical conductor to a current decoder for decoding the current-encoded data signal and extracting the original N-bit digital signal at a destination.

Abstract: A resistor network digital-to-analog converter (DAC) subdivides each sampling clock cycle of the DAC into a number of phases. For at least one bit input of the DAC associated with a desired input resistor weight, the input bit value is sampled at each phase. Each of those sampled values is then applied to a respective resistor branch, the parallel set of resistor branches forming the parallel equivalent of the desired input resistor weight for that bit input. Such application may be, for example, via a slew-rate controlled driver, to smooth transient edges in the generated analog output signal. The resulting analog signal experiences reduced reconstruction errors at a higher frequency while consuming less power than a comparable oversampling DAC. Shifting reconstruction errors to higher frequencies relaxes downstream filtering requirements, which simplifies analog signal filtering and allows, for example, the use of current-mode low pass filters.

Abstract: A current-steering type digital-to-analog converter (DAC) is disclosed. The DAC includes a first sub-DAC, a second sub-DAC and a controlling device. Both the first sub-DAC and the second sub-DAC are configured to receive input signals. The controlling device selectively and periodically sends output signals of either the first sub-DAC or the second sub-DAC to a resistive load while sending output signals of the remaining one of the two sub-DACs to a dummy resistive load. An output of the DAC is provided at the resistive load.

Abstract: A circuit includes T sets of digital to analog converters (DACs), each including N current sources and M delay elements. An output signal includes a sum of outputs of the N current sources. An input of a first one of the M delay elements and a control input of a first one of the N current sources receive a respective one of a plurality of decoded signals. T sets of first converters each have a feedback node, an output, and an input that communicates with the output signal of a respective one of the T sets of DACs. T second converters have inputs that communicate with respective ones of the feedback nodes of each of the T sets of first converters. A summer generates a difference signal that is based on the outputs of the T sets of first converters and outputs of the T second converters.

Abstract: A display panel driver including a binary-weighted current-type D/A converter and a source follower with current mirror is provided. The binary-weighted current-type D/A converter receives n input signals and sends a D/A output voltage signal based on 2n?1 times a reference current. The source follower with current mirror receives the D/A output voltage signal and sends 2n?1 times the reference current to the output of the source follower with current mirror, so as to output a output voltage and drive the display panel.

Abstract: A weight level generator is provided. Weight level generator W has plural weight generators 5-1-5-j. At least one of said plural weight generators is used at at least two different time rates. Also, a digital-to-analog converter (DAC) using said weight generators is equipped with a digital signal source, a weight controller, and a weight generator.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: A current compensation circuit and an optimized current compensation circuit are disclosed for a Parallel Resistors Architecture (PRA) digital-to-analog converter (DAC). The circuits are used to balance code dependent current consumption of the PRA-DAC.

Abstract: A digital-to-analog converting circuit includes: 2N or more number of digital-to-analog converting elements converting an input digital code of N+1 (N is an integer equal to or more than two) values to an analog code to output; a selecting section selecting N-number of digital-to-analog converting elements; and a control section controlling a second selecting so that each of at least N-number of digital-to-analog converting elements used for the digital-to-analog converting does not continuously output the same analog code at a second digital-to-analog converting timing following a first selecting of the N-number of digital-to-analog converting elements by the selecting section at a first digital-to-analog converting timing.

Abstract: Provided are a dynamic element-matching method, a multi-bit Digital-to-Analog Converter (DAC), and a delta-sigma modulator with the multi-bit DAC and delta-sigma DAC with the multi-bit DAC. The dynamic element-matching method relates to preventing periodic signal components (in-band tones) from being generated from a delta-sigma modulator of a delta-sigma Analog-to-Digital Converter (ADC) and a multi-bit DAC used in a delta-sigma DAC. Unit elements are selected in a new sequence according to a simple algorithm every time that each of unit elements is selected once, and thus the unit elements are not periodically used. Consequently, it is possible to prevent in-band tones caused by a conventional Data Weighted Averaging (DWA) algorithm.

Abstract: A multi-input operational amplifier circuit operable with a high degree of accuracy and in a small area, a D/A converter using the multi-input operational amplifier circuit, and a drive circuit or driver for a display device, using the D/A converter. In embodiments of the multi-input operational amplifier circuit, a constant current source of a third differential amplifier circuit that causes a doubled constant current i×2 to flow with respect to constant current sources of first and second differential amplifier circuits by application of two types of bias voltages thereto is configured using PMOS of the same number and size. Therefore, operations equivalent to those of a conventional circuit may be realized by the three constant current source PMOSs, and a smaller chip size may be required.

Abstract: The invention provides an improved dynamic element matching (DEM) device. The DEM device performs dynamic element matching processing at a second timing rate different from the first timing rate for the digital input. As an embodiment, the DEM device is composed of encoder 10 and feedback circuit 12. Said encoder 10 has two inputs and one output. Of the two inputs, one receives the digital input as the object for the DEM processing, and the other input receives the output of feedback circuit 12. Then, the digital output of the encoded result is generated. Said feedback circuit 12 has sampling rate converter 120 and loop filter 122 in order to perform DEM processing at a timing rate different from the timing rate for the digital input as the DEM processing object.

Abstract: A system and method are disclosed for providing an ultra low power scalable digital-to-analog converter architecture. Refresh buffer circuits are provided to buffer a voltage reference resistor string. The refresh buffer circuits may be coupled to the resistor string at selected binary fold points. The refresh buffer circuits can reduce the output impedance of the resistor string. Also, each digital-to-analog converter channel can be provided with a multi-dimensional multiplexer that minimizes settling time. The number of refresh buffer circuits and the number of dimensions of the multiplexer can be selected to maximize circuit performance for a given load capacitance and bit rate of the digital-to-analog converter.

Abstract: A D/A converter with reduced power consumption is offered by reducing an amount of electric charges that is charged and discharged as D/A conversion is performed. A terminal of each of four capacitors C1, C2, C3 and C4 is connected to a common node. The capacitors C1, C2, C3 and C4 have capacitances C, C, 2C and 4C, respectively. A selection circuit SEL is provided with selection transistors ST1, ST2, ST3, ST4, ST5 and ST6, and selects and outputs either a first reference electric potential V1 or a second electric potential V2 according to a value of each bit of the digital signals D0, D1 and D2. Each of transfer transistors TT1, TT2 and TT3 transfers each of outputs of the selection circuit SEL to another terminal of corresponding each of the capacitors C2, C3 and C4, respectively, in response to a start pulse STP.

Abstract: A digital current source used to mirror a reference current is provided. The digitally controlled analog current source multiplies a current from a master mirror transistor producing an output current that is a digitally controlled multiple of the reference current. The circuit comprises a plurality of one bit current mirror cells. Each one bit current mirror cell comprises a mirror transistor receiving an analog gate voltage from a master mirror transistor and providing a drain voltage, an operational amplifier configured to maintain the drain voltage for the mirror transistor equivalent to the analog gate voltage, and a switch configured to receive one control bit, the switch enabling current mirroring when the mirror voltage is substantially equivalent to the master mirror voltage. The digital current source further includes a common line summing element employed to receive and compile currents from each of the one bit current mirror cells.

Abstract: A multiple-input follower amplifier is coupled through a configuration of switching devices to an upper reference voltage at a number of its inputs and to a lower reference voltage at the remaining number of its inputs to form a voltage interpolator. The output of the voltage interpolator is a voltage between the upper and lower reference voltages proportional to the number of inputs coupled to each reference voltage. The voltage interpolator may be constructed so that the interpolated voltage may be selected through a reduced number of signal lines, such as by a row/column selection scheme. A voltage reference circuit providing the upper and lower reference voltages may also implement a row/column selection mechanism, thereby allowing a decoding scheme common to both a voltage reference circuit and a voltage interpolator in a digital-to-analog converter.

Abstract: In a method to improve error reduction in a digital-to-analog converter (DAC), comprising a mapping matrix block and a plurality of selectable source units which supply signals that in combination provide for analog output signals, mapping input signals, obtained from digital input signals to be converted into the analog output signals, are supplied to the mapping matrix block. In the mapping matrix block mapping output signals are generated in response to said mapping input signals and to mapping control signals derived from errors occurring in the plurality of selectable source units. At least one of the mapping input signals is applied for the substantially simultaneous generation of the mapping output signals for a number of source units.

Abstract: Differential, current-steering DACs with reduced small signal differential non-linearity. A set of binary-weighted steerable constant current generators is used in which each constant current generator comprises a ternary constant current generator configured to generate a three-state differential current in response to a ternary signal on a control input. Each ternary current generator is associated with a bit of the binary code. The DAC further comprises a code converter coupled between a digital input, to receive a signed digital value for conversion, and control inputs of the steerable current generators, to convert the binary input code to a ternary code to control the steerable current generators to provide a differential analogue output. In embodiments the smallest current source is ½I0 where I0 is a change in differential output current caused by an lsb change in the binary input code.

Abstract: An output circuit, a digital/analog conversion circuit and a display apparatus can reduce the number of required input voltages and the number of transistors to save the necessary area. The output circuit and the digital/analog conversion circuit comprise a selection circuit for receiving as input a plurality of (m) reference voltages having mutually different respective voltage values, selecting two of the voltages according to a selection signal and outputting them and an amplifier circuit for receiving as input the voltages output from the selection circuit at two input terminals T1, T2 and outputting the voltage obtained by interpolating the voltage difference of the two input terminal voltages V(T1), V(T2) to a predetermined ratio. It may alternatively be so arranged that the selection circuit sequentially outputs the selected two voltages and the amplifier circuit sequentially receives as two input the two voltages and outputs the output voltage obtained by interpolation.

Abstract: A D/A converter with reduced power consumption is offered by reducing an amount of electric charges that is charged and discharged as D/A conversion is performed. A terminal of each of four capacitors C1, C2, C3 and C4 is connected to a common node. The capacitors C1, C2, C3 and C4 have capacitances C, C, 2C and 4C, respectively. A selection circuit SEL is provided with selection transistors ST1, ST2, ST3, ST4, ST5 and ST6, and selects and outputs either a first reference electric potential V1 or a second electric potential V2 according to a value of each bit of the digital signals D0, D1 and D2. Each of transfer transistors TT1, TT2 and TT3 transfers each of outputs of the selection circuit SEL to another terminal of corresponding each of the capacitors C2, C3 and C4, respectively, in response to a start pulse STP.

Abstract: A digital-to-analog converter includes a first section (MSB) that converts the more significant bits of a digital code into a first voltage (Vin) of a multiplicity of discrete voltages that are integral multiples of a predetermined first voltage step (?V1). A second section (LSB) of the converter converts the less significant bits of the digital code into a current. The current is transformed into a second voltage of a multiplicity of discrete voltages that are integral multiples of a second voltage step (?V2) equal to ½ L of the product of the first voltage step (?V1) multiplied by a predetermined coefficient, where L is the number of the less significant bits of the digital code to be converted. A summer generates an output voltage (Vout) that is the sum of the second voltage and the product of the first voltage multiplied by the predetermined coefficient. With a view to obtaining a low consumption, the summer has a resistive feedback circuit including a voltage divider (R3, R4).

Abstract: The invention relates to a device for digital-to-radio frequency conversion, the device comprising: conversion cell matrices for digital-to-radio frequency conversion; means for providing a digital data signal; means for dividing the digital data signal into data signal groups; means for generating clock signals, the clock signals having different phases, the number of clock signals being the same as the number of data signal groups; means for synchronizing the data signal groups by using the clock signals; means for conveying the synchronized data signal groups to the conversion cell matrices, the number of conversion cell matrices being the same as the number of data signal groups; and means for synchronizing each conversion cell matrix by using the clock signal with which the synchronized data signal group conveyed thereto was synchronized for generating interpolation values.

Abstract: Disclosed is a digital-to-analog converting circuit including: a reference voltage generating circuit for outputting a plurality of reference voltages having voltage values that differ from one another; a data input control circuit for exercising control based upon a control signal so as to output either one of even-numbered bits or odd-numbered bits and then the other of the even-numbered bits or odd-numbered bits from a multiple-bit digital data signal input thereto; a decoder for successively selecting first and second voltages, inclusive of voltages that are identical, from among the plurality of reference voltages, which are output from the reference voltage generating circuit, in accordance with an output signal from the data input control circuit, and outputting the selected first and second voltages successively to the single terminal; and a differential amplifier, receiving the first and second voltages output from the decoder successively from the single terminal, for outputting from an output termi

Abstract: A spread spectrum system having a self-oscillating delay-line digital pulse width modulator and a method for mitigating electromagnetic interference. The spread spectrum system has a pseudo-random pattern generator connected to a digital-to-analog converter, which in turn is connected to a linear regulator. The linear regulator receives a reference voltage from the digital-to-analog converter and creates a frequency varying voltage that serves as an input voltage for delay elements of a delay-line based digital pulse width modulator. In response to frequency varying input signal, the delay-line based digital pulse width modulator generates a frequency varying voltage that is input to a switching network to vary its switching frequency.

Abstract: A gamma voltage generation circuit coupled to a digital-to-analog converter and provides the digital-to-analog converter with reference voltages by voltage division through resistor circuits. A variable voltage source can be modulated and charge-sharing switches can be included to save power. The reference voltage generation circuit can adopt output buffers that further improve the driving capability of the reference voltage generation circuit.

Abstract: An Ethernet controller includes a decoder, and T sets of transmit circuits. Each set of transmit circuits receives one of T decoded signals from the decoder, and includes a digital-to-analog converter (DAC) that provides a transmit output signal, and a replica circuit that provides a replica output signal. Each DAC includes N current sources arranged in parallel and differentially, and M delay elements. Each current source includes a control input. A sum of outputs of the N current sources forms each transmit output signal. An input of the first delay element and the control input of the first current source receive a decoded signal. An input of an mth delay element is in communication with an output of an m?1th delay element. The output of each delay element controls a corresponding control input of a current source. A sum of the transmit output signals forms an accumulated output signal.

Abstract: The present invention provides a digital-analog converter having: a DEM logic device (10) for generating at least two digital output data items (13, 14) from the digital input data (11) on the basis of a predetermined algorithm to determine an initial cell and a final cell in the array arrangement (22), between which there are situated cells (24) with energy sources (30) to be activated; a decoder device (16) for decoding the at least two digital output data items (13, 14) from the DEM device (10) into actuation signals (17, 17?, 18, 18?, 19, 19? 20, 20?, 21, 21?) in order to activate the cells (24) which are to be activated; and an array arrangement (22) of cells (23) for outputting at least one quantized analog signal (25, 25?) on the basis of the actuation signals (17, 17?, 18, 18?, 19, 19? 20, 20?, 21, 21?). The present invention likewise provides a method for digital-analog conversion.

Abstract: A transresistance amplifier circuit includes an input terminal receiving an input current, an output terminal providing an output voltage indicative of the input current, a first bias current source providing a first bias current to the input terminal, a first transistor, a second transistor, and a biasing circuit. The first transistor is coupled between the output terminal and the input terminal and controlled by a first bias voltage. The second transistor is coupled between a first supply voltage and the output terminal and controlled by a second bias voltage. The biasing circuit generates the first bias voltage for the first transistor for imposing a first voltage at the input terminal. The first voltage is equivalent to a selected voltage of an application circuit and the biasing circuit generates the first bias voltage in a manner so as to allow the first voltage to track variations in the selected voltage.

Abstract: A data converting method is realized by a data-converting circuit including: a data combining circuit for outputting 1st through (2n?1)th intermediate data bits by combining data bits corresponding to “1”s in n-bit binary data corresponding to a decimal number; a thermometer code generating circuit for generating 1st through (2n?1)th bits of thermometer code data each activated as “1” when a corresponding intermediate data bit among the 1st through (2n?1)th intermediate data bits are activated, wherein each of the 1st through (2n?1)th bits of thermometer code data is additionally activated as “1” by the 1st through (2n?1)th intermediate data bits activated by binary data having a greater value than binary data activating the corresponding intermediate data bit; and a reset circuit for periodically resetting the 1st through (2n?1)th bits of thermometer code data to “0” in response to an external clock signal. A digital-to-analog converter incorporates the data-converting circuit.

Abstract: A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller (“DAC”), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially. The invention can be implemented as a Z/kZ ladder network, where k is a real number.

Abstract: In a display device, clock supplying transistors turn on and off in response to a digital image signal retained in capacitance elements fed from drain signal lines through pixel element selection transistors. The image signal is applied to capacitance electrodes through the clock supplying transistors. Voltages change at the pixel element electrodes according to the value of the digital image signal. Therefore, a DA conversion is possible at the pixel element portion, leading to simplification of the peripheral circuit configuration around pixel element portions and the reduction of the framing area of the panel.

Abstract: A communication circuit, Ethernet controller card, and method comprises K digital-to-analog converters each receiving a corresponding digital control signal and each providing a corresponding analog control signal, wherein K is at least two; K voltage-to-current converters each providing a corresponding bi-level transmit signal component in accordance with a respective one of the corresponding analog control signals; and wherein the corresponding bi-level transmit signal components of each of the K voltage-to-current converters are combined to produce a J-level transmit signal, wherein J=K+1.