Abstract: In described examples, a digital-to-analog converter (DAC) includes an output, a ground, a reference voltage terminal, an input code terminal, multiple switches, multiple resistors, and a controller. The switches couple to the reference voltage terminal when activated and to the ground when deactivated. The resistors are variously coupled between corresponding ones of the switches and the output, so that activating the switches causes the DAC to output an output voltage. The controller is coupled to the input code terminal and coupled to control the switches. The controller generates an output code based on an input code in response to at least one differential nonlinearity error greater than one least significant bit voltage. The input code corresponds to a first ideal output voltage, the output code corresponds to a second, different ideal output voltage. The controller generates an output voltage by controlling the switches using the output code.

Abstract: Differential circuitry including first and second current paths each including a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry controlling a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively, wherein: the first load nodes of the first and second current paths include a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path include a successive further pair of load nodes.

Abstract: A method of performing a predetermined operation for a circuit that includes a resistor group, one end of the resistor group being configured for connection to a power supply unit, the other end of the resistor group being configured for connection to a sampling capacitor, and a parasitic capacitance existing at each node between resistors of the resistor group. The method includes in a forward process, determining a time when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage as a switching time; at the switching time, connecting the sampling capacitor to a ground or predetermined voltage and floating the power supply unit; in a backward process, after the switching time, determining a time when a power supply unit voltage applied to the power supply unit reaches a second reference voltage as an end time; and performing the predetermined operation based on the end time.

Abstract: A digital-to-analog converter (DAC) for generating an output voltage according to an input code includes a first-type and a second-type sub-DAC's connected in series. The first-type sub-DAC includes a first resistor string and plural first switches, and receives a reference current to determine a first voltage drop. The first switches are controlled by a first portion of the input code to determine a voltage division of the first voltage drop. The second-type sub-DAC includes a second resistor string and plural second switches. The second switches are controlled by a second portion of the input code to determine a portion of the second resistor string to receive the reference current, wherein the portion of the second resistor string and the reference current determines a second voltage drop. The output voltage includes a sum of the second voltage drop and the voltage division of the first voltage drop.

Abstract: A method for self-calibration of reference voltage drop in a Digital to Analog Converter (DAC) includes measuring each one of a plurality of thermometric weightages associated with a respective one of a plurality of thermometric bits, wherein the DAC includes a plurality of sub-binary bits and the plurality of thermometric bits. For each sequentially increasing combination of thermometric bit settings including at least two thermometric bits coupled to a high reference voltage and each sub-binary bit coupled to a low reference voltage, performing the steps of: determining a respective combined weightage correction; adding the combined weightage correction to the highest order bit of the combination of thermometric bit settings; and incrementing a number of bits of the combination of thermometric bit settings in response to the number of bits of the sequential combination being less than a total number of the plurality of thermometric bits.

Abstract: An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.

Abstract: A system includes a transmitter to transmit a set of bits associated with signaling having one or more levels. The system includes a receiver coupled to the transmitter, the receiver to receive the set of bits and generate a first plurality of digital values, each digital value generated at a first timing value and a plurality of reference voltages, the reference voltage incremented based at least in part on generating a digital value of the first plurality of digital values. The receiver is to generate a second plurality of digital values at a second timing value and the plurality of reference voltages, the first timing value incremented to the second timing value based at least in part on generating the first plurality of digital values. The system includes a controller to determine an amplitude associated with each the first and second plurality of digital values.

Abstract: An electronic device may include a digital to analog converter receiving digital signals and outputting analog signals based on the received digital signals. The electronic device may also include a power source to supply current to the digital to analog converter. The digital to analog converter may include a first resistor ladder section to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series. The digital to analog converter may also include a second resistor ladder section to electrically couple the output node to a reference voltage via a second number of resistors in series. The sum of the first number of resistors in series and the second number of resistors in series may be the same for each of the different analog signals.

Abstract: A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

Abstract: A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.

Abstract: A display device and a driving circuit enable to detect the crack for each display panel block by independently controlling each data driving circuit in case of multi data driving circuit and to provide a display device and a driving circuit enable to detect not only fine cracks but also disconnection by sequentially comparing a voltage of the display panel block with a reference voltage using a plurality of reference resistors.

Abstract: A digital-to-analog converter includes: a first partial circuit with a first bank of resistors and a first group of switches; a second partial circuit; a first resistor; a third partial circuit with a third bank of resistors and a third group of switches; and a fourth partial circuit with a fourth bank of resistors and a fourth group of switches Supposing that the first resistor has a resistance value R, the fourth bank of resistors has a combined resistance value of 2(n-m)R, the first bank of resistors has a combined resistance value of (2m?1)R, the third bank of resistors has a combined resistance value of (2m?1)R, and the second partial circuit has a combined resistance value of R/(2(n-m)?1).

Abstract: A self-check system and a method thereof are disclosed. In the self-check system, a memory stores a safety check program, a main application program and a predetermined checksum data. The safety check program include a circuit check program, a watchdog circuit reset program and a checksum check program. When a chip system is powered on, a processing unit executes the main application program, and then executes an interrupt call to generate an interrupt, so as to execute the safety check program and the circuit check program to check a to-be-checked circuit. The processing unit also executes the watchdog circuit reset program to reset a counting value of a watchdog circuit. The processing unit also executes the checksum check program to calculate a checksum data of the first safety check program, and reset the chip system when the calculated checksum data is not equal to the predetermined checksum data.

Abstract: An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.

Abstract: A display driver includes an operational amplifier, a D/A conversion circuit, a resistance circuit, and a resistance element. The D/A conversion circuit includes first and second variable resistance circuits including one end to which first and second voltages are input and another end connected to an inverting input node. The resistance circuit is provided between the inverting input node and an output node. The resistor is provided between the output node and the inverting input node. A resistance value of the first variable resistance circuit is set based on upper bit data of display data. A resistance value of the second variable resistance circuit is set based on lower bit data of the display data.

Abstract: A circuit board which includes a circuit that measures an input voltage and an output voltage in a voltage converter that converts the input voltage which is a difference between first and second voltages into the output voltage which is a difference between third and second voltages, may include: first to fourth resistor circuits respectively including first to fourth resistor element groups; a first differential amplifier circuit configured such that the first voltage is inputted via the first resistor element group and the second voltage is inputted via the second resistor element group; and a second differential amplifier circuit configured such that the third voltage is inputted via the third resistor element group and the second voltage is inputted via the fourth resistor element group. The second and fourth resistor element groups may be arranged to be adjacent to each other between the first and third resistor element groups.

Abstract: Circuits for an analog-to-digital converter and methods of operating an analog-to-digital converter. A resistor digital-to-analog converter (RDAC) has a first reference node coupled to a first current source, a second reference node coupled to a second current source, an input port configured to receive a first voltage, and an output port coupled to a buffer. The RDAC is configured to generate a second voltage including a first voltage shift from the first voltage and to supply the second voltage from the output port of the RDAC to the buffer.

Abstract: An auxiliary power circuit includes an impedance circuit, a switch, and a controller. The switch is coupled in series with the impedance circuit. The switch is configured to selectively couple the impedance circuit to a power source. The controller is coupled to the switch. The controller is configured to close the switch when an output voltage of the power source exceeds a voltage threshold.

Abstract: The present disclosure describes aspects of segmented resistor architecture for digital-to-analog converters (DACs). In some aspects, a DAC circuit is implemented with a first resistor network coupled to a set of binary code-controlled current sources and a second resistor network that includes a resistor coupled between the first resistor network and an output of the DAC circuit. A set of thermometer code-controlled current sources are coupled to a node of the second resistor network and provide varying amounts of current. This current is scaled based on a resistance of the second resistor network's resistor, which is higher than a resistance of the first resistor network and effective to increase a combined output impedance of the first and second resistor networks. The increase of output impedance reduces noise of the resistor networks that transfers to the output of the DAC circuit, thereby improving signal-to-noise performance of the DAC circuit.

Abstract: The present disclosure provides a display panel, a method and a device for measuring screen flickering, and a display device. The display panel includes a substrate, data lines and gate lines arranged on the substrate and crossing each other, and subpixel units defined by the data lines and the gate lines. Each subpixel unit includes a TFT, a pixel electrode, a first common electrode and a second common electrode. The second common electrode is connected to an input end capable of providing an alternating voltage at a first frequency. An orthogonal projection of the second common electrode onto the substrate at least partially overlaps an orthogonal projection of the pixel electrode onto the substrate.

Abstract: A system for providing on-chip voltage supply includes a plurality of local voltage regulators each including a first input, a second input, and an output; a transconductance amplifier connected with the local voltage regulators and configured to drive the local voltage regulators, including a first input, a second input and an output; a reference voltage source; and a plurality of transistors. The output of the transconductance amplifier is connected to the first input of each local voltage regulators. The first input of each local voltage regulator is connected to ground through a first capacitor. The output of each local voltage regulator is connected to gate of each transistor correspondingly. Source or drain of each transistor is connected to a load, to the second input of the local voltage regulator, to each other through a plurality of first resistors representing metal routing resistance, and to ground through a RC network.

Abstract: A digital to analog converter with output impedance compensation has an encoding unit, a current cell array, a summing unit and a compensation unit. The compensation unit is connected to output terminals of the DAC and provides a nonlinear impedance to compensate an original output impedance of the DAC. With the compensated output impedance, the SFDR performance and the linearity of the DAC are improved to obtain a superior input-to-output transfer curve.

Abstract: An apparatus of an exponential current digital-to-analog converter (IDAC) using a binary-weighted MSB to efficiently drive current controlled light emitting diode (LED) devices. The apparatus comprises of an exponential current digital-to-analog converter (IDAC) current source, a voltage buffer to create an active cascode at the output stage, and an error amplifier that by means of a DC-DC converter voltage loop imposes an appropriate voltage at the output of the IDAC, depending on the current load set to drive the LEDs. The definition of the apparatus involves defining an exponential LSB and exponential MSB current mirrors according to a defined methodology.

Abstract: An R-2R ladder resistor circuit including: plural first resistance elements, one end of each being connected to an input terminal; plural second resistance elements, one end of each being connected to a reference potential; plural third resistance elements, one end of each being connected to an output terminal; and plural switching connection sections that are each in correspondence relationships with the first resistance elements, the second resistance elements, and the third resistance elements, and that connect the input terminal and the output terminal according to a bit signal, wherein, according to the bit signal, each switching connection section switchably connects another end of the third resistance element to another end of the first resistance element or to another end of the second resistance element, among the first resistance element, the second resistance element, and the third resistance element corresponding thereto.

Abstract: A digital-to-analog conversion (DAC) circuit has a resistor ladder circuit controlled by high order bits and a resistor string circuit controlled by low order bits. The resistor ladder circuit includes a stem resistor and a branch resistor. The stem resistor has a stem resistance, and the branch resistor has a branch resistance that is substantially equal to two times of the stem resistance. The resistor string circuit includes a string current source, a string resistor, and a bridge resistor. The string current source is configured to generate a string current that is based on a ratio of a reference voltage divided by a predetermined resistance. The string resistor has a string resistance that corresponds to the predetermined resistance, and it is configured to selectively receive the string current based on a selection signal decoded from the low order bits.

Abstract: A sampling circuitry for a plurality of electrodes the circuitry comprising a plurality of charge amplifiers and a plurality of modulators, wherein each charge amplifier and each modulator, comprised in the plurality of charge amplifiers and the plurality of modulators, respectively, corresponds to an electrode of the plurality of electrodes, wherein each modulator is capable of generating a residue signal and a rough code corresponding to each sampled electrode of the plurality of electrodes, a multiplexer capable of receiving a plurality of residue signals generated by the plurality of modulators, a residue analog to digital converter capable of receiving a multiplexed residue signal from the multiplexer and outputting a digitized multiplexed residue signal, and a digital summation circuitry capable of receiving the digitized multiplexed residue signal and a plurality of rough codes, comprising each rough code corresponding to each sample electrode, and outputting a plurality of output codes.

Abstract: An oscillating signal generator includes: a controllable oscillator arranged to output an oscillating signal according to a control signal and a band adjusting signal; a control circuit arranged to generate a continuous signal having a specific slew-rate when the control signal reaches a boundary of a control signal interval; and a current mirror arranged to generate the band adjusting signal according to at least the continuous signal.

Abstract: A voltage monitoring device monitors voltage of each of battery cells connected in series to one another to configure an assembled battery. The device includes a capacitor circuit, a filter circuit, an input side connection switching unit, a potential difference detection unit, and an output side connection switching unit. The capacitor circuit includes a plurality of capacitors connected in series to one another. The filter circuit includes a plurality of resistors connected to an electrode terminal of each of the battery cells. The plurality of resistors are divided into a first resistor group and a second resistor group. The first resistor group is connected to a connection point between adjacent capacitors of the plurality of capacitors. The second resistor group is connected to an independent end of the plurality of capacitors. A resistance value of the first resistor group is smaller than a resistance value of the second resistor group.

Abstract: An LCD device and a driving method thereof are disclosed. The LCD device includes a data driver, a detection unit, and a power mode control option generation unit. The data driver controls a consumption power of an output buffer which outputs an image data signal to a liquid crystal display panel. The detection unit detects a low power driving mode interval for driving the data driver at a first consumption power. The power mode control option generation unit transfers a second power mode control option to the data driver during an interval other than the low power driving mode interval, and transfers a first power mode control option to the data driver during the low power driving mode interval.

Abstract: In an example, a multistring DAC is described and includes at least two DAC stages. Each DAC stage includes a string of impedance elements and a switching network. In one configuration, the multi-string DAC is configured to use the voltage change at terminals of a first string separately to the voltage drop across a first switching network that couples the first and second strings to provide an analog output in response to a digital input to the DAC.

Abstract: In an integrating A/D converter, first and second reference voltage inputs (18, 20) alternatingly connect through a reference voltage switch (16, 16?) via a first reference resistor (Rref) to an inverting input (122) of an integrator (12). A comparator (22) connected downstream of the integrator (12) compares a test voltage applied to its test voltage input (221) with a comparator reference voltage applied to its reference voltage input (222). This input (221) is connected to- the output (126) of the integrator (12). A control device (40) actuates the first reference voltage switch (16, 16?) in a pulsed manner and measures the time intervals between the individual switching processes. An inverter (24) inverting a measuring voltage (UM) and a first heating resistor (RMH) coupled thermally with a measuring resistor (RM), are connected in series between the measuring voltage input (14) and the output of the first reference voltage switch (16, 16?).

Abstract: A key press detecting circuit and method detect the status of multiple keys through a single pin. In an embodiment, a constant current is provided to apply to a key module through a single pin, to generate a voltage at the single pin that is related to the equivalent resistance of the key module observed from the single pin, and the voltage of the single pin is compared with a set of reference values to identify the status of the plurality of keys. In another embodiment, a variable current is provided to apply to a key module through a single pin in such a way that the variable current is adjusted to maintain a constant voltage at the single pin, and the variable current is compared with a set of reference values to identify the status of the plurality of keys.

Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: A resistor string digital-to-analog converter includes an input terminal receiving a digital input signal in digital code, an output terminal revealing an analog output signal in analog voltage, a first plurality of voltage-acquisition nodes including a first pair of nodes which is adjacent to each other, a first plurality of resistors being connected in series via the first plurality of voltage-acquisition nodes, a second pair of nodes revealing a pair of analog voltages, a high-order voltage-acquisition circuit providing conduction between a respective one of the first pair of nodes and a respective one of the second pair of nodes in accordance with the digital input signal, a low-order converter generating the analog output signal, which is obtained by interpolating one and the other of the pair of analog voltages in accordance with the digital input signal.

Abstract: A current controller includes impedance elements coupled to form at least one impedance ladder circuit which exhibits a fixed impedance at an input and current divider steps each differing in a current magnitude by a multiple of three with respect to the current magnitude in an adjacent less significant step. Single pole triple throw (SPTT) switchably couple an associated step in the impedance ladder circuit to one of three outputs. Three discrete current sources or sinks are each coupled to a corresponding one of the outputs of each of the SPTT switches. The digital driver is coupled to each control input of each SPTT switch to additively deliver selected ones of the stepped currents from each step of the impedance ladder circuit to a corresponding selected one of the current sources or sinks.

Abstract: A digital-to-analog (D/A) converter includes first resistors coupled in series, second resistors respectively coupled to the first resistors and each having a resistance twice as large as the resistance of the first resistor, and first switch circuits respectively coupled to the second resistors. Third resistors each have a resistance twice as large as the resistance of the first resistor. Second switch circuits each are coupled to the third resistors and a GND wire. A control circuit controls the first and second switch circuit in accordance with the digital input signals to set a state of a connection node to either one of a first voltage, a second voltage, and a high impedance.

Abstract: Embodiments of the present invention may provide a string DAC with charge boosting. The string DAC may include multiple strings, such as an MSB DAC and an LSB DAC, for converting a digital word into a corresponding analog voltage. The string DAC may also include a charge boost system to couple a charge into or out of the DAC during a code transition, such as a MSB code transition. The string DAC may operate in a break-before-make connection technique where all relevant connections are substantially open-circuited before new connections are made. Therefore, the charge boost may shorten the settling time of impedance elements in the string DAC between code transitions and may substantially reduce (or eliminate) glitches.

Abstract: Embodiments of the present invention may provide a multi-string DAC with leakage current cancellation. A leakage cancellation circuit may be coupled to output node(s) of the—multi-string DAC. The leakage cancellation circuit may replicate leakage current present at the coupled output node(s) and generate a corresponding complementary signal, a leakage cancellation signal. The leakage cancellation signal may be injected into the coupled output node(s) to cancel (or reduce) the net impact of the leakage current.

Abstract: Polarity compensating dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a secondary voltage divider of a dual-string DAC includes a switch logic unit. The switch logic unit is configured to compensate for polarity changes in the dual-string DAC to maintain monotonicity. Monotonicity means an output voltage of a DAC either increases or stays constant for monotonically increasing functions or either decreases or stays constant for monotonically decreasing functions given an incremental change in a DAC input code. The switch logic unit is configured to compensate for polarity changes in the input voltage from the primary voltage divider to the secondary resistor string. The switch logic unit is configured to select a secondary switch among the plurality of secondary switches in a secondary voltage divider, to divide an input voltage based on a polarity indicator and a DAC input code, to maintain monotonicity.

Abstract: A digital programmable load measurement device provides a controllable and variable load unit in a system. The variable load unit is connected to a voltage follower and a current follower to measure and figure out dynamic load voltage and load current of a device under test. Selected loads can be switched in a short period to measure the voltage and current values thereof, sampled for saving, and an I-V curve of the system can be depicted.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: Systems and techniques for performing binary divarication digital-to-analog conversion are described. A described converter includes voltage range adjusters arranged in series to convert a digital sequence to an analog representation, each of the adjusters being responsive to a respective bit of the digital sequence, and a combiner. The first adjuster produces first high and low output voltages based on first high and low input voltages and a most significant bit value of the digital sequence. The last adjuster produces last high and low output voltages based on last high and low input voltages and a least significant bit value of the digital sequence. The last high and low input voltages are responsive to the first high and low output voltages as modified by any of zero or more intermediate voltage range adjusters. The combiner produces an analog output signal based on the last high and low output voltages.

Abstract: A resistor string digital-to-analog converter includes a high-order resistor string, first high-order switches, a high-order decoder, a low-order decoder, and a conversion unit. The high-order resistor string includes a plurality of voltage acquisition points that are coupled through unit resistors. The high-order decoder generates a first high-order control signal in accordance with a high-order bit value, and operates in accordance with the first high-order control signal to bring into conduction a first high-order switch coupled to a pair of voltage acquisition points adjacent to each other through one or more voltage acquisition points. The low-order decoder generates a low-order control signal for controlling the conversion unit. The conversion unit divides a pair of high-order analog voltages output from a pair of voltage acquisition points.

Abstract: A resistor network implemented in an integrated circuit includes a first plurality of interconnect traces coupled in series at a first plurality of nodes; a first plurality of switches coupled between the first plurality of nodes and an output node; a second plurality of interconnect traces coupled in series at a second plurality of nodes; and a second plurality of switches coupled between the second plurality of nodes and the output node, wherein a voltage at the output node is generated in response to a resistance of the resistor network based upon a configuration of the first plurality of switches and the second plurality of switches.

Abstract: A sound volume control circuit includes: a first operational amplifier; a variable resistor circuit connected between an output and an inverting input of the first operational amplifier and having a plurality of resistance values; an R-2R ladder circuit connected between a voltage source of an input voltage; and a control circuit controlling the variable resistor circuit and the R-2R ladder circuit; wherein when changing a resistance value of the variable resistor circuit from a first resistance value to a second resistance value, so as to change the output voltage in a step size where a difference between the output voltage corresponding to the first resistance value and the output voltage corresponding to the second resistance value is further segmented, the control circuit changes the magnitude of the electric current flowing to the variable resistor circuit by use of the R-2R ladder circuit.

Abstract: Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.

Abstract: An N-bit digital-to-analog converter (DAC) includes N input stages each of which generates the same amount of current and includes a pair of similarly sized transistor switches responsive to differential bits. The 2M?1 input stages associated with the M most significant bits of the DAC are connected in parallel and deliver their currents differentially to the DAC's current summing nodes. Each of the remaining (N-M) stages includes a resistive network that supplies a current defined by a binary weight of the stage's bit position within the DAC. The (N-M) stages deliver their currents to the current summing nodes differentially. The DAC further includes an impedance attenuator adapted to maintain the impedance of the current summing nodes and the voltage difference between the current summing nodes within a range defined by a gain of a differential amplifier disposed in the impedance attenuator.

Abstract: A digital-to-analog (D/A) converter includes D/A conversion circuits and an amplifier circuit coupled between the D/A conversion circuits. Each D/A conversion circuit includes an R-2R ladder type resistor network, first transistors coupled between the resistor network and a first wiring at a first voltage level, and second transistors coupled between the resistor network and a second wiring at a second voltage level. The sizes of the first transistors are set at a ratio of powers of 2. The sizes of second transistors are set at a ratio of powers of 2. The second transistors are respectively turned on and off complementarily to the first transistors according to the digital input signal.

Abstract: A resistor-2 resistor (R-2R) digital-to-analog converter with partial resistor network reconfiguration. A circuit includes a plurality of resistor stacks. The circuit also includes a plurality of separation resistors which separate each of the plurality of resistor stacks. The circuit further includes a first selection circuit connected to a first resistor stack of the plurality of resistor stacks and a plurality of selection circuits connected between the plurality of separation resistors. The circuit also includes a termination resistor stack connected to a drain of the first resistor stack.

Abstract: A digital-to-analog (D/A) converter includes first resistors coupled in series, second resistors respectively coupled to the first resistors and each having a resistance twice as large as the resistance of the first resistor, and first switch circuits respectively coupled to the second resistors. Third resistors each have a resistance twice as large as the resistance of the first resistor. Second switch circuits each are coupled to the third resistors and a GND wire. A control circuit controls the first and second switch circuit in accordance with the digital input signals to set a state of a connection node to either one of a first voltage, a second voltage, and a high impedance.