Abstract: A digital-to-analog (D/A) converter includes first resistors coupled in series, second resistors respectively coupled to the first resistors and each having a resistance twice as large as the resistance of the first resistor, and first switch circuits respectively coupled to the second resistors. Third resistors each have a resistance twice as large as the resistance of the first resistor. Second switch circuits each are coupled to the third resistors and a GND wire. A control circuit controls the first and second switch circuit in accordance with the digital input signals to set a state of a connection node to either one of a first voltage, a second voltage, and a high impedance.

Abstract: A dynamically selectable resistor network is provided in a star configuration for producing a weighted sum of input values, without attenuation from near zero contributions. Each branch of the star connected network comprises sets of impedance components, preferably resistors, that are actively selectable to produce permutated combinations of effective weighting values. The resistors code digital control bits and the outputs of sets of resistors in respective branches that correspond to the least significant control bits provide their outputs to the summing output node independently of the sets of resistors corresponding to control bits of other significance.

Abstract: Embodiments of the present invention may provide a string DAC with charge boosting. The string DAC may include multiple strings, such as an MSB DAC and an LSB DAC, for converting a digital word into a corresponding analog voltage. The string DAC may also include a charge boost system to couple a charge into or out of the DAC during a code transition, such as a MSB code transition. The string DAC may operate in a break-before-make connection technique where all relevant connections are substantially open-circuited before new connections are made. Therefore, the charge boost may shorten the settling time of impedance elements in the string DAC between code transitions and may substantially reduce (or eliminate) glitches.

Abstract: A differential resistor-based digital-to-analog converter (RDAC) can include a positive digital-to-analog converter (PDAC) stage and a negative digital-to-analog converter (NDAC) stage. A first network of resistors of the PDAC stage can be electrically coupled to a second network of resistors of the NDAC stage utilizing an intermediary network of resistors. Further, a differential receiver can include a first input and a second input. The first input can be electrically coupled to a first resistor of the intermediary network of resistors, and the second input can be electrically coupled to a second resistor of the intermediary network of resistors. Furthermore, a portion of the first network of resistors can be electrically coupled to a positive output of the RDAC, and another portion of the second network of resistors can be electrically coupled to a negative output of the RDAC.

Abstract: One of the critical design parameters occurs when a digital signal is converted into an analog signal. As the supply voltage drops to less than 2 times of threshold voltage to reduce leakage and save power, generating a relative large swing with a resistor-ladder DAC becomes more difficult. For a 5 bit DAC, 32 sub-arrays are used to select the appropriate voltage from the series coupled resistor network. Each sub-array uses p-channel transistors where the sub-array extracting the lowest voltage 700 mV only has a 100 mV of gate to source voltage. To compensate for the reduced gate to source voltage, the sub-arrays are partitioned into four groups. In each group, the p-channel width is increased from 2 um to 5 um, as the tap voltage drops from 1.2 V to 0.7 V. This allows the p-channel transistor with a small gate to source voltage to have a larger width thereby improving performance.

Abstract: An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As.

Abstract: An N bit sub-binary radix digital-to analog converter (DAC) includes a radix conversion module that converts an m bit digital input signal to an N bit sub-radix DAC code. A ladder module having NL bits has a plurality of first circuit elements corresponding to first respective bits of the N bit sub-radix DAC code. A segment module having NS bits has at least one second circuit element corresponding to second respective bits of the N bit sub-radix DAC code. N>m, and N is the sum of NL and NS.

Abstract: A differential digital-to-analog converter (DAC) is disclosed. In one embodiment, a DAC includes a number of resistor networks coupled in series to form a ring, and a digital decoder configured to receive a digital code. Based on the most significant bits of the digital code, the digital decoder is configured to close selected ones of first and second groups of switches to couple first and second reference voltage nodes to corresponding tap points on the ring. Within the number of networks are first and second output circuits, each of which is arranged as a one-hot multiplexer. Based on the least significant bits of the digital code, the decoder is configured to couple respective tap points in the ring to first and second output voltage nodes in order to provide a differential output voltage based on the digital code.

Abstract: A resistor-2 resistor (R-2R) digital-to-analog converter with resistor network reversal and methods of use are disclosed. A circuit includes a plurality of resistor stacks and a plurality of separation resistors which separate the resistor stacks. The circuit further includes a plurality of selection devices connected to a respective one of the plurality of resistor stacks. The circuit also includes a first termination resistor stack connected to a drain of a first resistor stack of the plurality of resistor stacks and a second termination resistor stack connected to a drain of a last resistor stack of the plurality of resistor stacks. The circuit further includes a first switch connected to the drain of the first resistor stack of the plurality of resistor stacks and an output. The circuit also includes a second switch connected to the drain of the last resistor stack of the plurality of resistor stacks and the output.

Abstract: N upper-side resistors and N lower-side resistors are severally associated with respective bits of a digital input code. Each resistance value is weighted in an essentially binary manner according to the corresponding bit. N upper-side switches are each arranged in parallel with a corresponding upper-side resistor, and each is configured such that its on/off state is controlled according to the corresponding bit. N lower-side switches are each arranged in parallel with a corresponding lower-side resistor, and each is configured such that its on/off state is controlled according to logical inversion of the corresponding bit.

Abstract: A DAC has at least one bit current-steering circuit. In the DAC, the current-steering circuit has a current source circuit, a switch, a feedback circuit, and an amplifier circuit. The current source circuit is disposed for outputting a bias current to the switch and coupled to the amplifier circuit. The switch has a first input/output terminal coupled to output an analog signal, a control terminal coupled to the feedback circuit, and a second input/output terminal for receiving the bias current, so that the first switch determines whether the first and the second input/output terminals are conducted according to a status of the control terminal.

Abstract: A continuous-time delta-sigma Analog to Digital Converter (ADC) includes: a loop filter, for receiving and noise-shaping an analog input signal, and outputting a first loop voltage; a first summing resistor, for transforming a first feedback current to be a first feedback voltage, and summing the first loop voltage and the first feedback voltage so as to generate a first summing voltage, wherein the first summing voltage is equal to a sum of the first loop voltage and the first feedback voltage; a quantizer, for outputting a digital output signal according to the first summing voltage; and a current Digital to Analog Converter (DAC), for generating the first feedback current according to the digital output signal.

Abstract: A device includes a comparator, and a selection circuit coupled to the inputs of the comparator. The selection circuit receives reference voltages and a variable voltage. In a normal operation mode, the selection circuit provides the variable voltage and a selected reference voltage to the comparator and the comparator provides an indication based on the variable voltage. In a test mode, the selection circuit provides a first selected reference voltage and a second selected reference voltage to the comparator for determining a switching offset voltage of the comparator.

Abstract: A resistor-2 resistor (R-2R) digital-to-analog converter with resistor network reversal and methods of use are disclosed. A circuit includes a plurality of resistor stacks and a plurality of separation resistors which separate the resistor stacks. The circuit further includes a plurality of selection devices connected to a respective one of the plurality of resistor stacks. The circuit also includes a first termination resistor stack connected to a drain of a first resistor stack of the plurality of resistor stacks and a second termination resistor stack connected to a drain of a last resistor stack of the plurality of resistor stacks. The circuit further includes a first switch connected to the drain of the first resistor stack of the plurality of resistor stacks and an output. The circuit also includes a second switch connected to the drain of the last resistor stack of the plurality of resistor stacks and the output.

Abstract: A resistor-2 resistor (R-2R) digital-to-analog converter with partial resistor network reconfiguration. A circuit includes a plurality of resistor stacks. The circuit also includes a plurality of separation resistors which separate each of the plurality of resistor stacks. The circuit further includes a first selection circuit connected to a first resistor stack of the plurality of resistor stacks and a plurality of selection circuits connected between the plurality of separation resistors. The circuit also includes a termination resistor stack connected to a drain of the first resistor stack.

Abstract: A digital-to analog-converter (DAC) has a MSB resistor ladder with a plurality of series connected resistors, wherein the MSB resistor ladder is coupled between a first and second reference potential, a LSB resistor ladder with a plurality of series connected resistors, and a plurality of switching units for connecting one of the series connected resistors of the MSB resistor ladder with the LSB resistor ladder, wherein each switching unit has a first switch for connecting a first terminal of an associated MSB resistor with a first terminal of the LSB resistor ladder and a second switch for connecting a second terminal of the associated MSB resistor with a second terminal of the LSB resistor ladder and wherein each switch is configured form a resistor of similar value of the resistors of the LSB resistor ladder when switched on.

Abstract: A system includes an NL bit digital to analog converter (DAC) ladder module having NL ladder resistors connected in parallel, NL series resistors connected in series between the NL ladder resistors, and a plurality of switches. NL is an integer greater than one. Adjacent pairs of the plurality of switches are connected in series with respective ones of the ladder resistors. On resistances of each of the plurality of switches are approximately equal. A switch control module provides a plurality of switch control signals to respective ones of the plurality of switches.

Abstract: A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion. At least one tap voltage generator generates a plurality of voltages, preferably using a resistor string. A decoder decodes at least one sub-word that forms the lesser significant portion to generate a corresponding at least one control signal. A switching unit accesses voltages generated by the at least one tap voltage generator in response to the at least one control signal. A scaled current generator generates a respective weighted current from each accessed voltage. An output stage combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.

Abstract: A multi-valued driver circuit selectively outputs, to a transmission line, one from among multiple voltages according to a selection signal. A memory circuit stores setting data which define the respective levels of the multiple voltages. According to the selection signal, a selector circuit selects one from among the multiple setting data stored in the memory circuit. A Thevenin termination circuit outputs a voltage that corresponds to the upper M bits of the data thus selected by the selector circuit. An R-2R ladder circuit outputs a voltage that corresponds to the lower Nl bits of the data thus selected by the selector circuit.

Abstract: An inverter-driven resistor-ladder digital-to-analog (DAC) converter includes a resistor-ladder network that comprises a resistor for each bit signal of a multi-bit input signal. Each resistor of the resistor-ladder network comprises an input end and an output end. The input end of each resistor is coupled to a corresponding bit signal of the multi-bit input signal, and the output end of each resistor is coupled to an output node of the resistor-ladder network. An output voltage is generated at the output node that is based on the multi-bit input signal. In one exemplary embodiment, the multi-bit input signal is a sigma-delta (??) modulated multi-bit input signal. In another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are related by a binary weighting. In still another exemplary embodiment, resistance values of the resistors of the resistor-ladder network are substantially equal.

Abstract: Complete testing of an analog-to-digital converter (ADC) can be carried out using digital signals and at high speeds. Circuit elements are added to an ADC so that a first phase of testing may be carried out using a limited number of analog test voltages. The ADC may then be reconfigured using added circuit elements to disable conventional analog-to-digital conversion. A digital signal may then be applied to the ADC to rapidly test all switching elements used in analog-to-digital conversion. According to some implementations, testing times for ADCs may be reduced from hours to milliseconds.

Abstract: A circuit has a digital to analog (DA) resistance ladder having an analog output; a capacitor coupled to the analog output; a first resistance coupled from the capacitor to ground; and a switch coupled to the capacitor in parallel to the resistor, wherein the switch, when closed, has a second resistance, and the first resistance is greater than the second resistance.

Abstract: A digital-to-analog (D/A) converter includes D/A conversion circuits and an amplifier circuit coupled between the D/A conversion circuits. Each D/A conversion circuit includes an R-2R ladder type resistor network, first transistors coupled between the resistor network and a first wiring at a first voltage level, and second transistors coupled between the resistor network and a second wiring at a second voltage level. The sizes of the first transistors are set at a ratio of powers of 2. The sizes of second transistors are set at a ratio of powers of 2. The second transistors are respectively turned on and off complementarily to the first transistors according to the digital input signal.

Abstract: An apparatus is provided that comprises resistors, a first set of switches, and a second set of switches. The resistors are arranged in an array having columns and rows, where the number of resistors is an integer multiple of the number of columns or rows. The resistors are coupled together in a skip-K pattern. Each switch from the first and second sets of switches is coupled to the resistor string, and the first and second sets of switches are each arranged in a sequence and are offset from one another by an offset value. The first and second sets of switches are arranged along the periphery of the array such that each switch from the first set of switches is located in proximity to and is associated with the same row or the same column as its corresponding switch in the sequence from the second set of switches.

Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N?m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.

Abstract: Examples of resistive digital-to-analog converter (RDAC) circuits are provided herein. RDAC circuits may provide an analog output signal derived from an n-bit digital input signal. In one example, an RDAC circuit may include a plurality of resistive circuit branches. Each resistive circuit branch may be arranged in a pull up/pull down network configuration. For example, an RDAC circuit may include a plurality of resistive circuit branches positioned in parallel. In an example, each of the plurality of resistive circuit branches may include a first inverter circuit, a second inverter circuit, and a resistive component. The RDAC circuit may include an output node for providing the analog output signal. Additionally, methods are provided for converting an analog output signal derived from an n-bit digital input signal.

Abstract: A circuit has a digital to analog (DA) resistance ladder having an analog output; a capacitor coupled to the analog output; a first resistance coupled from the capacitor to ground; and a switch coupled to the capacitor in parallel to the resistor, wherein the switch, when closed, has a second resistance, and the first resistance is greater than the second resistance.

Abstract: A circuit includes a digital-to-analog converter with non-uniform resolution for converting a digital signal into an analog signal. The digital-to-analog converter includes high-resolution circuitry, reduced-resolution circuitry coupled to the high-resolution circuitry and a switch coupled to the high-resolution circuitry and to the reduced-resolution circuitry. The switch couples one of the high-resolution circuitry and the reduced-resolution circuitry to an output node. The circuit also includes a decoder coupled to the switch. The decoder receives the digital signal to control the switch.

Abstract: An analog-to-digital converter including a voltage generation unit and a plurality of sub ADCs, each including a selection unit for selecting a voltage generated by the voltage generation unit based on a number and forwarding the selected voltage to a comparator arrangement. The selection unit includes first and second switch layers. The first switch layer includes a plurality of switch groups, each including a plurality of switch devices, each connected to a unique output terminal of the voltage generation unit with a first terminal and to a common node of the switch group with a second terminal. The second switch layer includes a switch device between the common node of each switch group and the first output terminal of the selection unit and a switch device between the common node and the second output terminal of the selection unit. A control unit generates control signals for the switch devices.

Abstract: A low power consumption DA converter includes a segment type DA converter and an R-2R resistance ladder DA converter. The segment type DA converter is coupled to a power source voltage VDD and outputs a current signal changing in a stepwise manner according to inputted upper bits D[7 to 5]. The R-2R resistance ladder DA converter is coupled to the segment type DA converter in series between the power source voltage VDD and a ground voltage GND, and outputs an output voltage Vout changing in a stepwise manner. The R-2R resistance ladder DA converter changes the output voltage Vout by raising or lowering a reference voltage Vref according to the lower bits D[4 to 0] and the current signal from the segment type DA converter.

Abstract: An integrated circuit includes a first connection line; a second connection line; a plurality of tuning resistors with each having a sequence number and being coupled between the first connection line and the second connection line; and a plurality of switches, with each being coupled in series with one of the plurality of tuning resistors. The sequence numbers of the plurality of tuning resistors are continuous. The resistance values of the plurality of tuning resistors are a function of the respective sequence numbers.

Abstract: A resistor string digital-to-analog converter includes an input terminal receiving a digital input signal in digital code, an output terminal revealing an analog output signal in analog voltage, a first plurality of voltage-acquisition nodes including a first pair of nodes which is adjacent to each other, a first plurality of resistors being connected in series via the first plurality of voltage-acquisition nodes, a second pair of nodes revealing a pair of analog voltages, a high-order voltage-acquisition circuit providing conduction between a respective one of the first pair of nodes and a respective one of the second pair of nodes in accordance with the digital input signal, a low-order converter generating the analog output signal, which is obtained by interpolating one and the other of the pair of analog voltages in accordance with the digital input signal.

Abstract: A gamma voltage generator includes an RGB common gamma voltage generation section configured to generate RGB common gamma voltages using corresponding gamma reference voltages among a plurality of gamma reference voltages; and at least two of an RG gamma voltage generation section configured to generate RG gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, an R gamma voltage generation section configured to generate R gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, a G gamma voltage generation section configured to generate G gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, and a B gamma voltage generation section configured to generate B gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages.

Abstract: A system includes an N bit sub-binary radix digital-to-analog converter (DAC) that converts an m bit digital input signal to an analog output signal, where m and N are integers greater than or equal to 1 and N>m. A radix conversion module determines a code ratio, the code ratio being a ratio of a total number of available monotonic codes to 2m, and performs radix conversion on the m bit digital input signal based on the code ratio.

Abstract: A digital potentiometer includes a circuit containing multiple string arrays, each having a plurality of switching devices connected to an array of resistors. Each input terminal receives a separate digital input code enabling the resistance of one of the arms to be varied without changing the other.

Abstract: A system for implementing a cyclic digital to analog converter (c-DAC) is capable of supporting a large size liquid crystal display. The system includes an upper DAC stage configured to output a first voltage between a lower voltage supply (HVDD) and an upper voltage supply (AVDD). The system also includes a lower DAC stage configured to output a second voltage between the lower voltage supply (HVDD) and a ground. The upper DAC stage includes a single PMOS switch and the lower DAC stage includes a single NMOS switch.

Abstract: A method and apparatus are provided for calibrating a ladder circuit. The apparatus includes: a logic unit for receiving a first logical signal, a second logical signal, and N control bits and for outputting N alternative control bits and an additional control bit, where N is an integer greater than 1; a core circuit for receiving the N alternative control bits, the additional control bit, and a tuning word, and for outputting an output signal, wherein the core circuit comprises N?1 series elements, N shunt elements with a connectivity controlled by the N alternative control bits, respectively, and a termination element with a connectivity controlled by the additional control bit; and a calibration circuit for receiving the first logical signal, the second logical signal, and the output signal and for outputting the tuning word.

Abstract: A digital-to-analog conversion circuit includes a gradation voltage generation circuit, a most-significant-bits decoder circuit, a least-significant-bits decoder circuit and a calculation circuit. The gradation voltage generation circuit generates multiple main voltages corresponding to most significant bits of the inputted data, and multiple sub voltages corresponding to least significant bits of the inputted data. The most-significant-bits decoder circuit selects one of the main voltages in accordance with the most significant bits, and the least-significant-bits decoder circuit selects one of the sub voltages in accordance with the least significant bits. The calculator circuit performs calculation processing by use of a first main voltage selected by the most-significant-bits decoder circuit, a first sub voltage selected by the least-significant-bits decoder circuit, and a reference voltage.

Abstract: A system includes an N bit sub-binary radix digital-to-analog converter (DAC) that converts an m bit digital input signal to an analog output signal, where m and N are integers greater than or equal to 1 and N>m. A radix conversion module determines a code ratio, the code ratio being a ratio of a total number of available monotonic codes to 2m, and performs radix conversion on the m bit digital input signal based on the code ratio.

Abstract: A grayscale voltage generating circuit includes a first constant-voltage source for generating a high potential; a second constant-voltage source for generating a low potential; ? resistor connected between outputs of the first and second constant-voltage sources; a difference voltage detecting circuit for detecting a difference voltage across the ? resistor; and a voltage-to-current converting circuit for converting the difference voltage to a current by a resistor and outputting the current as a source current and a sink current. The source current output and sink current output of the voltage-to-current converting circuit are connected to the high and low potential sides, respectively, of the ? resistor.

Abstract: A circuit includes a digital-to-analog converter with non-uniform resolution for converting a digital signal into an analog signal. The digital-to-analog converter includes high-resolution circuitry, reduced-resolution circuitry coupled to the high-resolution circuitry and a switch coupled to the high-resolution circuitry and to the reduced-resolution circuitry. The switch couples one of the high-resolution circuitry and the reduced-resolution circuitry to an output node. The circuit also includes a decoder coupled to the switch. The decoder receives the digital signal to control the switch.

Abstract: A digital-to-analog converter (DAC) includes: a plurality of first controllers and a plurality of resistor devices. The plurality of first controllers are configured to be selectively switched on according to a received digital signal to control an analog signal according to the received digital signal. The plurality of resistor devices are respectively connected to the plurality of first controllers. The plurality of resistor devices include non-volatile memory devices.

Abstract: An resistor string digital-to-analog converter (DAC) that includes elements to compensate for resistor ladder loading, and/or to provide compensation for loading such as via switch current cancellation. The approach reduces output voltage sensitivity to switch resistances while also reducing INL and DNL errors. Additional resistor loops are optionally disposed at the top and bottom of one or more further segments to provide Nth order resistive current cancellation.

Abstract: A digital to analog converter (DAC) includes a pair of operational amplifiers each having a first input coupled to a reference voltage. The DAC includes a plurality of switch-controlled cells, each of which includes a resistor and two force/sense switch pairs. A first force switch may be coupled to an output of a first operational amplifier and an associated sense switch may be coupled to an inverting input of the first operational amplifier. A second force switch may be coupled to an output of a second operational amplifier and an associated sense switch may be coupled to an inverting input of the second operational amplifier. The force switches may provide selectively conductive paths to permit either operational amplifier to drive a given cell.

Abstract: A low power consumption DA converter includes a segment type DA converter and an R-2R resistance ladder DA converter. The segment type DA converter is coupled to a power source voltage VDD and outputs a current signal changing in a stepwise manner according to inputted upper bits D[7 to 5]. The R-2R resistance ladder DA converter is coupled to the segment type DA converter in series between the power source voltage VDD and a ground voltage GND, and outputs an output voltage Vout changing in a stepwise manner. The R-2R resistance ladder DA converter changes the output voltage Vout by raising or lowering a reference voltage Vref according to the lower bits D[4 to 0] and the current signal from the segment type DA converter.

Abstract: A force/sense voltage-mode DAC coupled with multiple transconductance amplifiers that generate a correction current injected to a node in one of the DAC cells is discussed. The correction current injected into the DAC cell may reduce nonlinearity produced by biasing current to the operational amplifiers in the DAC.

Abstract: A multilevel voltage generating circuit includes first and second input nodes provided on a first resistance element and supplied with first and second reference voltages. A current substantially flows in a first specific area for a line between the first and second input nodes based on a difference between the first and second reference voltages. A first group of output nodes are provided for the first resistance element to output a portion of a plurality of level voltages. A first one of the first group of output nodes for one of the plurality of level voltages which is closest to the first reference voltage is provided outside the first specific area. The first output node, the first input node, and the second input node, are arranged on a line on the first resistance element in this order.

Abstract: An equalization circuitry that includes a digital-to-analog converter having a voltage divider and a multiplexer coupled to the voltage divider is described. In one implementation, the digital-to-analog converter provides a control signal to a plurality of single-stage equalizer control logic circuits. Also, in one implementation, the multiplexer receives a plurality of inputs from the voltage divider and selects an output from the plurality of inputs. Furthermore, in one implementation, the voltage divider includes a plurality of resistors coupled in series. Also, in one implementation, the voltage divider further includes a first resistor coupled to the plurality of resistors, ground, and a lowest voltage input terminal of the multiplexer, where a voltage across the first resistor is an input voltage to the lowest voltage input terminal.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: A resistor string digital to analog converter formed of polysilicon resistor segments to each of which is applied an electric field. The approach improves the overall accuracy.