Abstract: A system and method are provided allowing for successive approximation analog to digital conversion. A first differential voltage is sampled and held during a first cycle. The first differential voltage is converted to a differential current. A second differential voltage is generated based on the differential current flowing through parallel-coupled respective first and second variable resistances. First and second portions of the second differential voltage are compared to produce a comparison result therefrom. Successive approximation is used to generate a signal based on the comparison result, the signal being an output signal and being used to control resistances of respective ones of the first and second variable resistances during subsequent cycles.

Abstract: A digital-to-analog converter has a reference value source, a reference value divider arrangement with a tap, a first switch arrangement which is designed to produce an electrical connection between the tap and a first output of the digital-to-analog converter, and a second switch arrangement which is designed to produce an electrical connection between the tap and a second output of the digital-to-analog converter.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: An adjustable voltage supply (310) may have a plurality of levels of adjustment, such as a coarse select circuit (471) and a fine select circuit (473), to generate an adjustable voltage (e.g. Vout 364 of FIGS. 3 and 4) with fine resolution across a wide voltage range. In one embodiment, the adjustable voltage may be used as an adjustable read voltage to measure the threshold voltages of bitcells in a memory array (300). From the distribution of these threshold voltages, it is possible to determine the marginality of the bitcells with regard to the voltage which is required to read the bitcells. In one embodiment, the adjustable voltage supply (310) may also be used to provide an adjustable voltage to one or more integrated circuit pwells and/or nwells in order to apply electrical stress. An adjustable voltage supply (310) may be used in any desired context, not just memories.

Abstract: A converter of 6-bit input includes a reference voltage generating circuit generating 17 reference voltages, a first switch circuit having 19 switch pairs each including MOS transistors for selecting two adjacent reference voltages in accordance with the four most significant bits, a second switch circuit including a series circuit of MOS transistors for dividing the selected two reference voltages into four to obtain three intermediate voltages, and a third switch circuit for selectively outputting the lower of the selected two reference voltages or one of the three intermediate voltages. In a second mode in which a gray level having a smaller ON-resistance of a MOS transistor than that in the first mode is selected, the number of MOS transistors used in the first and second switch circuits for voltage division is increased.

Abstract: An inverted ladder circuit for a Digital to Analog Converter (DAC) having an input binary word representing an input value and an output current corresponding to a converted analog value. The inverted ladder circuit includes at least two fine resistor ladders, including at least an upper fine resistor ladder and a lower fine resistor ladder. The inverted ladder circuit also includes a coarse resistor ladder having a corresponding plurality of coarse ladder resistors, wherein the coarse resistor ladder slides upon the at least two fine resistor ladders. The inverted ladder circuit also includes a plurality of upper fine switches and a plurality of lower fine switches, wherein the switches operate in parallel according to the lower five bits of the input binary word. The plurality of fine ladder resistors are matched with the plurality of coarse ladder resistors to obtain current proportional to the input binary word. The output resistance and parasitic capacitance are reduced.

Abstract: A resistor-based digital to analog converter (DAC) having mux fastpaths, which selectively connect a subset (or an entirety) of voltage divider nodes in a DAC to either a higher level of multiplexor hierarchy, or a DAC output node, effectively bypassing one or more levels of multiplexor devices. In addition, the fastpaths may selectively connect lower levels of multiplexor hierarchy to higher levels of multiplexor hierarchy and/or a DAC output node.

Abstract: A D/A converter circuit which converts a digital signal of n bits into an analog signal and outputs the analog signal comprises: a plurality of D/A conversion processors, each of which converting a digital signal into an analog signal, the digital signal being made by dividing the n-bit digital signal at least into two; a plurality of output resistance regulators coupled to outputs of the plurality of respective D/A conversion processors; and an output signal generator generating the analog signal that forms an output of the D/A converter circuit based on outputs of the plurality of output resistance regulators.

Abstract: A data driver capable of generating data signals with desired voltage values. The data driver includes a first digital-analog converter including a plurality of first switches, the first digital-analog converter selecting two reference voltages from among a plurality of reference voltages by turning on two of the first switches corresponding to high level bits of data; and a second digital-analog converter for dividing the two reference voltages into a plurality of voltages and for supplying any one of the two reference voltages and the divided voltages corresponding to low level bits of the data as a data signal to an output terminal, wherein the second digital-analog converter includes a transistor turned on by a bias voltage to compensate for a turn-on resistance of the two of the first switches.

Abstract: The present invention provides the voltage generator comprises providing a binary weight digital-to-analog converter (DAC) including an R-2R ladder network, and control switches, and an operation amplifier (OP) with a feedback resistance, and providing a plurality of voltages, from an input of said ladder network, in a positive polarity and a negative polarity, wherein said positive polarity and negative polarity are determined by a reference voltage, and each of said switches is switched between a connection to said OP and said reference voltage.

Abstract: A folded R-2R ladder current-steering digital-to-analog converter is disclosed. In the folded R-2R ladder current-steering digital-to-analog converter, each node in the R-2R ladder is electrically coupled with a plurality of current sources with different weights. Therefore, the numbers of the resisters and current sources can be reduced, and efficient power saving and the high-speed operation can be achieved.

Abstract: A digital to analog converter (DAC) system includes a resistor network providing enhanced response time and steady state characteristics.

Abstract: Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.

Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.

Abstract: For reducing device areas required by digital-to-analog converters used in source driving circuits of a liquid crystal display device, a compound circuit structure based on a pre-decoder, a binary decoder, and ROM decoders is set forth to meet the demand for cutting down the device areas. The pre-decoder is configured to decode a first sub-signal of a digital data signal for generating a plurality of control signals. Each of the ROM decoders is configured to select a gamma reference voltage out of one corresponding set of gamma reference voltages based on the control signals and a second sub-signal of the digital data signal. The binary decoder is configured to select one of the gamma reference voltages selected by the ROM decoders based on a third sub-signal of the digital data signal for outputting an output voltage. The number of transistors used by the compound circuit structure is then reduced significantly.

Abstract: An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.

Abstract: A digital-to-analog converter is provided. The DAC includes a R-string section, a first DAC section, a second DAC section, a multiplexer, and an operational amplifier. The R-string section provides a first group of voltage levels and a second group of voltage levels. The first DAC section provides the output voltage according to the input word when the input word corresponds to a voltage level within a range of the first group of voltages levels. The second DAC section provides a second and a third voltage levels according to the remaining bits. The multiplexer is coupled to the second DAC section to provide an intermediate voltage from the first and the second voltage levels according to the LSB bit. The operational amplifier averages the intermediate voltage and one of the first and the second voltage levels to generate the output voltage.

Abstract: A comparator compares an input voltage and a reference voltage and generates an output based on the comparison. The comparator may receive the input voltage in a normal mode of operation. Voltage band circuitry provides first and second test voltages to the comparator. The test voltages define a band around the reference voltage. An integrator adjusts an offset correction signal provided to the comparator based on outputs of the comparator that are generated using the test voltages. The output of the comparator that is generated using the first test voltage could be generated during a first auto-zeroing cycle. The output of the comparator that is generated using the second test voltage could be generated during a second auto-zeroing cycle. This technique helps to maintain the offset of the comparator with the band around the reference voltage.

Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.

Abstract: A semiconductor device includes a semiconductor substrate and a ladder resistor formed on the semiconductor substrate. The ladder resistor includes a plurality of elongated resistor portions arranged in parallel with each other, a plurality of connection portions that connect the resistor portions at predetermined intervals in a longitudinal direction of the resistor portions, and a plurality of voltage extraction portions provided in order to extract voltages at the individual connection portions.

Abstract: A system and method are disclosed for providing an ultra low power scalable digital-to-analog converter architecture. Refresh buffer circuits are provided to buffer a voltage reference resistor string. The refresh buffer circuits may be coupled to the resistor string at selected binary fold points. The refresh buffer circuits can reduce the output impedance of the resistor string. Also, each digital-to-analog converter channel can be provided with a multi-dimensional multiplexer that minimizes settling time. The number of refresh buffer circuits and the number of dimensions of the multiplexer can be selected to maximize circuit performance for a given load capacitance and bit rate of the digital-to-analog converter.

Abstract: A digital to analog converter includes a coarse resolution resistor circuit (11) coupled between a first voltage (Vin) and an intermediate voltage (V0) to produce coarse resolution node voltages (V0, . . . V240), and also includes a fine resolution resistor circuit (20) coupled between the intermediate voltage and a second voltage (GND). One of the coarse resolution node voltages is selected in response to a group of MSB bits of a digital input (D0,1 . . . ) to produce a first output voltage (Vout2), and one of the fine resolution node voltages is selected in response to group of LSB bits of the digital input to produce a second output voltage (Vout1), the second output voltage (Vout1) and the first output voltage (Vout2) providing a differential analog output signal (Vout1?Vout2). In one embodiment, the coarse resolution and fine resolution resistor circuits are string resistor circuits, and in another embodiment they are modified R-2R networks.

Abstract: A reference voltage generation circuit for a plurality of reference generation voltages and a pipe line analog-to-digital converter (ADC) using the same are provided. The reference voltage generation circuit including a charging capacitor for stabilizing the reference voltages charges the charging capacitor prior to the generation of the reference voltages, thus decreasing the time for the pipe line ADC to operate stably.

Abstract: A digital-to-analog converter (DAC) includes a decoder unit for receiving an external digital data signal operating over a first predefined voltage range (i.e., 0-5V); a resistor array for generating a plurality of gray voltages defined across a second voltage range that is substantially wider than the first predefined voltage range, and a voltage selecting unit for selecting one of the gray voltages based on an output of the decoder unit, wherein the decoder unit includes a plurality of decoder stages and first and second boost circuits for generating output signals operating over a third voltage range (i.e., 0-7V) that is substantially wider than the first predefined voltage range while not requiring an additional power supply for producing voltages of the third voltage range (i.e., 0-7V).

Abstract: A drive circuit for a display panel has a D/A conversion circuit which has a unit region serving as a circuit element that is formed in an IC. Contact pads are provided at both ends in a rectangular guard ring region and at the center thereof. Further, a plurality of MOS switch transistors are arranged and formed respectively between these contact pads. The contact pads arranged at both ends in the unit region, respectively receive one of a plurality of analog voltages. The contact pad at the center is connected to a predetermined output, and the respective switch transistors in the unit region are respectively operated as switch circuits. An analog conversion voltage is obtained by selecting ON/OFF of the plurality of switch transistors in the unit region in response to data.

Abstract: A trimdac circuit for adjusting the output of a digital-to-analog converter (DAC) is provided. The trimdac may be used to adjust a plurality of resistor segments in the DAC. The trimdac may include a programmable Read Only Memory (ROM) or other suitable memory device. The ROM may include a plurality of multi-bit digital words. Each of the multi-bit digital words may control a plurality, and most preferably a pair of variable resistance circuits. Each of the pair of variable resistance circuits may adjust a resistor segment of the DAC.

Abstract: A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence. One of the selected reference voltages is supplied through a resistor and a switching device, connected in series, to the output terminal of the converter. The other selected reference voltage is supplied through another resistor and another switching device, connected in series, to the same output terminal. This arrangement saves space, and enables variations in the output voltage levels to-be kept within tolerance by use of resistors with sufficiently high resistance values.

Abstract: A D/A converter includes: an (N?1)-stage reference resistor group; an N-stage reference resistor group; inter-stage op-amps applying a divided voltage outputted from voltage taps of the (N?1)-stage reference resistor group, across both ends of the N-stage reference resistor group as the Nth reference voltage; a dynamic range expanding means for arranging the voltage taps in the (N?1)-stage reference resistor group so as to expand upward and downward, to expand an input dynamic range in the N-stage reference resistor group; and expansion resistors arranged respectively at both upper and lower ends of the N-stage reference resistor group in response to upward and downward expanded amounts of the dynamic range.

Abstract: A digital to analog converter (DAC) converting digital data into a corresponding analog voltage is disclosed.

Abstract: A multiplexing circuit uses parallel-configured pairs of resistors and signal sources in a voltage divider network in such a way that a single analog-to-digital input can be used to specify the state of more than one signal source. One circuit includes a microprocessor having an analog-to-digital (ADC) input; a memory communicatively coupled to the microprocessor; and a voltage divider network having an output coupled to the ADC input, wherein the network includes a plurality of resistors paired with a plurality of respective signal sources, and wherein the output is unique for each combination of states of the signal sources in accordance with a known relation that is stored in the memory. The signal sources are selected from two categories of sources: continuous sources and discrete sources, where discrete sources may be binary discrete or random discrete. In one embodiment, the first signal source is either a continuous source or a random discrete source, and the second signal is a binary discrete source.

Abstract: A system, apparatus and method for providing a digital variable resistor with high resolution and efficient use of substrate area is described. In one embodiment of the invention, a digital variable resistor string comprises a serial array of resistors that is connected to a parallel array of resistors through a switching network. A compensation network is coupled in parallel to the parallel array of resistors in order to compensate for resistance drift caused by non-linear responses of components within the variable resistor. For example, the compensation network may interpolate the digital variable resistor to a preferred resistance value that is within an error margin tolerance.

Abstract: An analog-to-digital converter includes a track-and-hold circuit, a constant-voltage source, a threshold voltage selection circuit, a first comparator to a seventh comparator, an encoder, and a reference voltage output circuit. In a correction mode where the offsets of the first to seventh comparators are to be corrected, a track-and-hold circuit shuts off the input of an analog voltage to the first to seventh comparators by turning off the track-hold switch.

Abstract: A multiple-input follower amplifier is coupled through a configuration of switching devices to an upper reference voltage at a number of its inputs and to a lower reference voltage at the remaining number of its inputs to form a voltage interpolator. The output of the voltage interpolator is a voltage between the upper and lower reference voltages proportional to the number of inputs coupled to each reference voltage. The voltage interpolator may be constructed so that the interpolated voltage may be selected through a reduced number of signal lines, such as by a row/column selection scheme. A voltage reference circuit providing the upper and lower reference voltages may also implement a row/column selection mechanism, thereby allowing a decoding scheme common to both a voltage reference circuit and a voltage interpolator in a digital-to-analog converter.

Abstract: Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.

Abstract: A folding and interpolating analog,-to-digital converter (ADC) includes a preamp unit, a first folding stage, a second folding stage, a comparison unit and an encoder. The preamp unit receives an analog input signal and reference voltages to generate reference signals. The first folding stage generates a first group of folding signals based on the reference signals. The second folding stage generates a second group of folding signals based the first group. The comparison unit generates a digital code based on the folding signals in the second group. The encoder encodes the digital code. Therefore, the ADC can increase a resolution and a conversion speed, but reduce interpolating errors.

Abstract: A data driver capable of generating data signals with desired voltage values. The data driver includes a first digital-analog converter including a plurality of first switches, the first digital-analog converter selecting two reference voltages from among a plurality of reference voltages by turning on two of the first switches corresponding to high level bits of data; and a second digital-analog converter for dividing the two reference voltages into a plurality of voltages and for supplying any one of the two reference voltages and the divided voltages corresponding to low level bits of the data as a data signal to an output terminal, wherein the second digital-analog converter includes a transistor turned on by a bias voltage to compensate for a turn-on resistance of the two of the first switches.

Abstract: A common voltage adjustment circuit. The common voltage adjustment circuit is applied in a liquid crystal display panel having a plurality of display units, coupled to a common electrode. The common voltage adjustment circuit has a first register, a second register, a first digital-to-analog converter, a second digital-to-analog converter, and a regulator. The common voltage adjustment circuit adjusts AC voltage and DC voltage of the common voltage and provides the adjusted common voltage to the common electrode.

Abstract: A D/A conversion circuit for performing D/A conversion at high speeds. The D/A conversion circuit includes a resistor string including a plurality of resistor elements connected between a low-potential power supply and a high-potential power supply. A plurality of first switch groups are connected to the connection nodes between the resistor elements for selectively outputting voltages at the connection nodes. The outputs of the switches of the first switch groups are connected in common to a corresponding one of the nodes. The plurality of nodes are connected to an output terminal of the D/A conversion circuit via a second switch group. Predetermined switches of the first switch groups are connected in parallel to third switches to apply voltages to the nodes.

Abstract: A driving device for driving an image display system, which sequentially receives input image data corresponding to gradation of each pixel of a display image and outputs a driving voltage signal includes: an operation section for obtaining output image data of which a bit number is smaller than a bit number of the input image data based on input image data of a target pixel to be processed and input image data of a pixel in vicinity of the target pixel; a reference voltage generation section for generating a plurality of reference voltages of different levels; and a reference voltage selection section for selecting one of the plurality of reference voltages. The operation section is configured to obtain output image data of the target pixel so that a difference between the input image data and output image data of the target pixel and a difference between the input image data and output image data of the pixel in vicinity of the target pixel cancel out each other.

Abstract: The invention relates to fast analogue-to-digital converters having differential inputs and a parallel structure, comprising at least one network of N series resistors with value r and one network of N comparators. The series resistor network receives a reference voltage and is traversed by a fixed current Io and the row i (i varying from 1 to N) comparator essentially comprises a dual differential amplifier with four inputs; two inputs receive a differential voltage VS?VN to be converted, a third being connected to a row i resistor of the network, and a fourth input being connected to an N-i row resistor of the network. The resistor network is supplied by a variable reference voltage originating from a servoloop circuit which locks the voltage level of the middle of the resistor network at a voltage equal to the common mode voltage (VS?VSN)/2 present at the output of the sample-and-hold module.

Abstract: An overdrive digital-to-analog converter (DAC), a source driver, and a method thereof are provided. The DAC comprises a voltage divider unit, a selection unit, a buffer unit, and a detection unit. The voltage divider unit provides a plurality of reference voltages. The detection unit outputs a regulation signal according to a comparison result between a specific reference signal corresponding to an input digital signal and an output voltage output from the buffer unit. The selection unit regulates an overdrive voltage input to the buffer unit according to the regulation signal and the input digital signal. Accordingly, the output voltage of the buffer unit is changed quickly, and the conversion speed of the DAC is improved.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: An LCD driving circuit and method for increasing effective bit(s) of the source driver is disclosed. A reference voltage generator generates a group of compensated reference voltage levels that are interlaced with original reference voltage level of original reference voltage generator. One of the multiple groups of reference voltage levels is selected by one or more least significant bits (LSBs), and is then inputted to digital-to-Analog converter of the source driver under control of the one or more least significant bits (LSBs), thereby effectively and economically enhancing the gray levels of the display on the LCD panel.

Abstract: A drive circuit for a display panel has a D/A conversion circuit which has a unit region serving as a circuit element that is formed in an IC. Contact pads are provided at both ends in a rectangular guard ring region and at the center thereof. Further, a plurality of MOS switch transistors are arranged and formed respectively between these contact pads. The contact pads arranged at both ends in the unit region, respectively receive one of a plurality of analog voltages. The contact pad at the center is connected to a predetermined output, and the respective switch transistors in the unit region are respectively operated as switch circuits. An analog conversion volta e is obtained by selecting ON/OFF of the plurality of switch transistors in the unit region in response to data.

Abstract: A digital/analog converter includes a first divided-voltage generating section which divides a reference supply voltage through the voltage distribution, a decoder section which receives a digital signal so as to output a decoded selection signal, a first divided-voltage selecting section which selects and outputs a plurality of divided voltages among the divided voltages generated from the first divided-voltage generating section on the basis of the selection signal output from the decoder section, a second divided-voltage selecting section which selects and outputs a plurality of divided voltages among the divided-voltages output from the first divided-voltage selecting section on the basis of the selection signal output from the decoder section, a second divided-voltage generating section which divides the plurality of divided-voltages output from the second divided-voltage selecting section, a third divided-voltage selecting section which selects a predetermined voltage among the divided-voltages output f

Abstract: An output circuit, a digital/analog conversion circuit and a display apparatus can reduce the number of required input voltages and the number of transistors to save the necessary area. The output circuit and the digital/analog conversion circuit comprise a selection circuit for receiving as input a plurality of (m) reference voltages having mutually different respective voltage values, selecting two of the voltages according to a selection signal and outputting them and an amplifier circuit for receiving as input the voltages output from the selection circuit at two input terminals T1, T2 and outputting the voltage obtained by interpolating the voltage difference of the two input terminal voltages V(T1), V(T2) to a predetermined ratio. It may alternatively be so arranged that the selection circuit sequentially outputs the selected two voltages and the amplifier circuit sequentially receives as two input the two voltages and outputs the output voltage obtained by interpolation.

Abstract: A Digital to Analog (D/A) converter has a plurality of stages. Each of the plurality of stages has a first resistive element. A second resistive element is coupled to the first resistive element and has approximately twice a resistive value of the first resistive element. A capacitor is coupled to the second resistive element. A switching circuit is coupled to the capacitor. A summing integrator is coupled to each of the plurality of stages.

Abstract: According to this invention, there is provided a voltage output digital-to-analog converter circuit, including other ones of the second resistive elements and third resistive elements having a desired resistance value are series-connected between the other ends of the second resistive elements, which are connected to switching elements of the plurality of switching elements to which a most significant bit and a least significant bit are supplied, and the ground.

Abstract: Embodiments of a digital potentiometer are disclosed that require lesser numbers of components than conventional digital potentiometers. A first string of elemental impedance devices, and at least one bulk impedance device, are provided between first and second reference terminals. The first string of elemental impedance devices is tapped by wiper switches. The at least one bulk impedance device has an impedance greater than an impedance of the first string. If desired, second and third bypassable impedance device strings also may be provided between the first and second reference terminals, with the impedance of the respective second and third strings being between the impedance of the first string and the impedance of one bulk impedance device. One or more dummy structures each including an impedance device in parallel with a permanently-on switch also may be between the first and second reference terminals to improve linearity.

Abstract: Disclosed is a digital-to-analog converting circuit including: a reference voltage generating circuit for outputting a plurality of reference voltages having voltage values that differ from one another; a data input control circuit for exercising control based upon a control signal so as to output either one of even-numbered bits or odd-numbered bits and then the other of the even-numbered bits or odd-numbered bits from a multiple-bit digital data signal input thereto; a decoder for successively selecting first and second voltages, inclusive of voltages that are identical, from among the plurality of reference voltages, which are output from the reference voltage generating circuit, in accordance with an output signal from the data input control circuit, and outputting the selected first and second voltages successively to the single terminal; and a differential amplifier, receiving the first and second voltages output from the decoder successively from the single terminal, for outputting from an output termi