Recirculating Patents (Class 341/163)
  • Patent number: 10404264
    Abstract: A method of performing analog-to-digital conversion using a successive approximation (SAR) analog-to-digital converter (ADC). A previous digital output is compared to a range based on the first M bits of the previous digital output. If the previous digital output is within that range, a digital-to-analog converter (DAC) of the SAR ADC is preloaded with the first M bits of the previous digital output, prior to commencing bit trials. If the previous digital output is outside of that range, an offset is applied to the first M bits of the previous digital output and the DAC is preloaded based on the M bits and the offset, prior to performing bit trials. This method reduces the possibility of the next input being outside of a further range defined by the preload.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 3, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Baozhen Chen, Lalinda D. Fernando, Zhichao Tan
  • Patent number: 10348532
    Abstract: Various embodiments include apparatus and methods having a data receiver with a real time clock decoding decision feedback equalizer. In various embodiments, a digital decision feedback loop can be implemented in a data receiver circuit, while all analog signals involved are static relative to the input signal data rate. The implemented data receiver circuit can include a number of data latches with different, but static, analog unbalances and a decision-based clock decoder. In an example, the analog unbalances may be different reference voltages. The decision-based clock decoder can be structured to activate only one data latch, the one with the desired analog unbalance. The outputs of the latches attached to the same clock decoder can be combined such that only the active latch drives the final output. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Dragos Dimitriu
  • Patent number: 10284187
    Abstract: A comparator includes a differential input pair of transistors, a pair of cross coupled n-channel metal-oxide-semiconductor field-effect (NMOS) transistors, a pair of p-channel metal-oxide semiconductor field-effect (PMOS) transistors, a first inverter, and a second inverter. The differential input pair of transistors includes a first input transistor and a second input transistor. The pair of cross coupled NMOS transistors includes a first NMOS transistor and a second NMOS transistor. The pair of PMOS transistors includes a first PMOS transistor and a second PMOS transistor. The pair of PMOS transistors are coupled to the pair of cross coupled NMOS transistors. The first inverter is coupled in series with the first PMOS transistor. The second inverter is coupled in series with the second PMOS transistor.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: May 7, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Prasanth K., Jagannathan Venkataraman, Eeshan Miglani
  • Patent number: 10212375
    Abstract: An analog-to-digital converter includes a comparator, a switch, and a counter circuit. The comparator is configured to generate a comparison signal by comparing an analog signal received through a first signal line and a reference signal received through a second signal line. The switch is coupled between the first signal line and the comparator. The switch is open before the analog signal is applied to the first signal line to disconnect the first signal line from the comparator, and is closed after the analog signal is applied to the first signal line to provide the analog signal to the comparator. The counter circuit is configured to generate a digital signal corresponding to the analog signal by performing a count operation in synchronization with a count clock signal based on the comparison signal.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moo-Young Kim, Kwang-Hyun Lee, Kyoung-Min Koh
  • Patent number: 9998138
    Abstract: Multi-channel receiver circuits implemented with time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits and methods for operating such receiver circuits are disclosed. One example receiver circuit generally includes a first multiplexer having a plurality of inputs coupled to a plurality of in-phase (I) receive paths associated with different channels of the receiver circuit, a first SAR ADC circuit having an input coupled to an output of the first multiplexer, a second multiplexer having a plurality of inputs coupled to a plurality of quadrature (Q) receive paths associated with the different channels of the receiver circuit, and a second SAR ADC circuit having an input coupled to an output of the second multiplexer.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 12, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Yan Wang, Chieh-Yu Hsieh, Ji Ma, Seyed Arash Mirhaj, Dinesh Jagannath Alladi
  • Patent number: 9998162
    Abstract: Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Eshel Gordon, Sophia Maerkovich, Ofir Degani, Hasnain Lakdawala
  • Patent number: 9965223
    Abstract: Systems and methods for management of scalable storage architectures are disclosed. The system includes one or more storage backplanes, each storage backplane configured to interface with one or more hard disk drives. The system includes a baseboard management controller, which includes an interface to communicate with one or more of the storage backplanes and programmable logic configured to detect the presence of one or more hard disk drives in an interfaced storage backplane and control one or more status indicators, wherein each status indicator is related to at least one of the hard disk drives in the interfaced storage backplane.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 8, 2018
    Assignee: Dell Products L.P.
    Inventors: Shawn Joel Dube, Tim Lambert, Surender V. Brahmaroutu
  • Patent number: 9892857
    Abstract: A capacitor circuit includes: a capacitor array including a plurality of capacitors; a switch array including a plurality of switch circuits, the switch circuits being respectively connected to the capacitors of the capacitor array; a plurality of switch control signal lines supplied with a plurality of switch control signals; and a substrate having a major surface on which the switch circuits are formed. At least part of the capacitors of the capacitor array is formed of a first conductive layer. The switch control signal lines are formed of a second conductive layer provided between the major surface and the first conductive layer. The capacitor array and the switch array are disposed so as to overlap each other at least in part in a plan view when viewed in a normal direction of the major surface.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 13, 2018
    Assignee: Seiko Epson Corporation
    Inventors: Atsushi Tanaka, Hideo Haneda
  • Patent number: 9531400
    Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive appro
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: December 27, 2016
    Assignee: AVNERA CORPORATION
    Inventors: Jianping Wen, Garry Link, Wai Lee
  • Patent number: 9377967
    Abstract: Systems and methods for management of scalable storage architectures are disclosed. The system includes one or more storage backplanes, each storage backplane configured to interface with one or more hard disk drives. The system includes a baseboard management controller, which includes an interface to communicate with one or more of the storage backplanes and programmable logic configured to detect the presence of one or more hard disk drives in an interfaced storage backplane and control one or more status indicators, wherein each status indicator is related to at least one of the hard disk drives in the interfaced storage backplane.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: June 28, 2016
    Assignee: DELL PRODUCTS L.P.
    Inventors: Shawn Joel Dube, Timothy M. Lambert, Surender V. Brahmaroutu
  • Patent number: 9319057
    Abstract: Devices and methods for providing filtering for an analog-to-digital converter (ADC) are described. In one embodiment, a method for providing filtering for an ADC involves obtaining a filter coefficient of a post-filtering filter that is located after the ADC on a signal path and generating a filter coefficient of a pre-filtering filter that is located before the ADC on the signal path based on the filter coefficient of the post-filtering filter. Other embodiments are also described.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: April 19, 2016
    Assignee: NXP B.V.
    Inventors: Sujan Pandey, Hubertus Gerardus Hendrikus Vermeulen, Abhijit Kumar Deb
  • Patent number: 9252800
    Abstract: An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: February 2, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joonsung Park, Krishnaswamy Nagaraj, Mikel Ash
  • Patent number: 9209824
    Abstract: A medical device and associated method convert an analog signal using an adaptable bit number. The medical device includes an analog-to-digital (A/D) converter for receiving an analog signal. The A/D converter has a full scale range and a total number of bits spanning the full scale range. The A/D converter converts the analog signal to a digital signal over conversion cycles using an adaptable bit number so that on at least a portion of the conversion cycles an adapted number of bits spanning a portion of the full scale range less than the total number of bits is used by the A/D converter to convert the analog signal.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: December 8, 2015
    Assignee: Medtronic, Inc.
    Inventors: Xiaonan Shen, Jonathan P. Roberts
  • Patent number: 9166612
    Abstract: To provide a semiconductor device capable of accurately controlling the cycle of an internal clock signal. This semiconductor device, by using signal that is output from a sequence register of an asynchronous successive approximation type ADC when N times of comparison are completed, detects whether or not the signal and its delay signal are output when the period transitions from a comparison period to a sampling period, and generates, on the basis of the detection result, a delay control signal for controlling the cycle of an internal clock signal by controlling the delay times of the delay circuits.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: October 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Masaki Fujiwara, Yasuo Morimoto, Takashi Matsumoto
  • Patent number: 9154244
    Abstract: In accordance with some embodiments, methods for controlling the second order intercept point in a receiver are provided, the methods comprising: generating an amplitude modulated test tone; causing the test tone to be received by a receiver; determining a characteristic of a second order intercept point of the receiver based on the received test tone; and based on the characteristic, adjusting a parameter of the receiver. In accordance with some embodiments, systems for controlling the second order intercept point in as receiver are provided, the systems comprising: a test tone generator that generates an amplitude modulated test tone; a receiver that receives the test tone; a correlator that determines a characteristic of a second order intercept point of the receiver based on the received test tone; and digital logic that, based on the characteristic, adjusts a parameter of the receiver.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: October 6, 2015
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Yiping Feng, Peter Kinget
  • Patent number: 9083365
    Abstract: An encoder is provided for converting thermometer code data with bubbles to binary format. An integrated circuit may have circuitry such as digital phase-locked loop circuitry. A thermometer code data word may be used as a control signal for the circuitry. It may be desirable to monitor the thermometer code data word for testing or for downstream processing by control logic on the integrated circuit. The encoder performs thermometer code to binary encoding without requiring that the thermometer code be error corrected to remove bubbles. A bubble detection circuit may be used to detect when the thermometer code data contains bubbles. The encoder may use carry look-ahead adders and pipeline stages.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: July 14, 2015
    Assignee: Altera Corporation
    Inventors: Ping Xiao, William W. Bereza, Weiying Ding, Mohsen Moussavi
  • Patent number: 9077373
    Abstract: An A/D conversion apparatus includes a signal processor, a quantizer, and a controller. The signal processor has circuit blocks connected in a loop to process an analog input signal. The quantizer generates a quantization value by quantizing an output of at least one of the circuit blocks including a final-stage circuit block. In each circuit block, one end of a first capacitor is connected through a switch to an input terminal of an operational amplifier, and one end of each of second and third capacitors is connected directly to the operational amplifier. The controller generates an A/D conversion result of the analog input signal according to the quantization value and changes connection conditions of the capacitors so that the signal processor and the quantizer function as a delta-sigma modulator or a cyclic A/D converter.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: July 7, 2015
    Assignee: DENSO CORPORATION
    Inventor: Tomohiro Nezuka
  • Patent number: 9048860
    Abstract: An apparatus relating generally to an analog-to-digital converter (“ADC”) is disclosed. In such an apparatus, the ADC is configured for successive approximations. The ADC includes a digital-to-analog converter (“DAC”), a comparator, and a control block. The DAC is coupled to receive a reference input signal and coupled to provide an analog output signal. The analog output signal is capacitively coupled to an analog input node through a capacitor. The capacitor is coupled between the DAC and the comparator to provide capacitive coupling therebetween. The comparator is coupled to the analog input node. The comparator is further coupled to provide a comparator output signal to the control block. The control block is configured for successive approximations to provide a digital output signal to a digital output node. The DAC is coupled to the digital output node to receive the digital output signal as a feedback input signal.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: June 2, 2015
    Assignee: XILINX, INC.
    Inventor: Patrick J. Quinn
  • Patent number: 9041575
    Abstract: A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: May 26, 2015
    Assignee: MEDIATEK INC.
    Inventor: Yuan-Ching Lien
  • Patent number: 9041569
    Abstract: A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 26, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Yan Zhou, Clayton Daigle, Shouli Yan, Mohamed Elsayed
  • Patent number: 9041584
    Abstract: A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 26, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Xiaodong Wang, Shouli Yan, Axel Thomsen
  • Patent number: 9024798
    Abstract: According to a method of Successive Approximation Register (SAR) analog to digital conversion, N+1 SAR cycles are performed to obtain an output digital code having N bits. An analog signal is sampled and obtained. After execution of the first N?1 SAR cycles, the Nth SAR cycle is performed by setting a Nth tentative analog signal corresponding to a provisional digital code and comparing the Nth tentative analog signal with the sampled analog signal to obtain a Nth comparison result. The (N+1)th SAR cycle is performed by setting a (N+1)th tentative analog signal based on the Nth comparison result, comparing the (N+1)th tentative analog signal with the sampled analog signal to obtain a second comparison result, and correcting the provisional digital code based on the (N+1)th comparison result to obtain the output digital code. The Nth and (N+1)th SAR cycles each comprise a plurality sub-comparisons and yield a set of sub-results.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 5, 2015
    Assignee: ST-Ericsson SA
    Inventors: Marco Zamprogno, Francesca Girardi, Alberto Minuti
  • Patent number: 8994572
    Abstract: The objective of the invention is to provide an A/D converter that exhibits fewer malfunctions due to variations in manufacturing.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: March 31, 2015
    Assignee: Japan Science and Technology Agency
    Inventors: Hao San, Tsubasa Maruyama, Masao Hotta
  • Patent number: 8988268
    Abstract: According to the present invention, a successive approximation type analog-digital converter includes: a comparator outputting a result of comparing an analog signal and a reference voltage; a register storing a digital value corresponding to the result of comparison and outputting a digital signal; a detection unit detecting whether the comparator is in a stable state or not for each bit; and a bit determination unit storing, if the comparator is not stable, as a bit value of a bit which is one bit lower-order than a corresponding detection bit, a value obtained by inverting a final determined bit value of the detection bit in the register instead of the comparison result of the comparator.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomohiko Sugimoto, Hirotomo Ishii
  • Patent number: 8981973
    Abstract: A fixed capacitor is coupled between a top plate of an attenuation capacitor and a variable voltage reference. The error in the attenuation capacitor may be calibrated out with the variable voltage reference and the fixed correction capacitor. The variable voltage reference varies the charge on the attenuation capacitor and thereby compensates for error(s) therein. A calibration digital-to-analog converter may be used in conjunction with or substituted for the variable voltage reference, and may be programmed for different charge compensation values from the SAR logic during an iterative SAR DAC capacitive switching process.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: March 17, 2015
    Assignee: Microchip Technology Incorporated
    Inventor: Ajay Kumar
  • Patent number: 8963761
    Abstract: A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to ½ of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: February 24, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jen-Huan Tsai, Po-Chiun Huang, Shih-Hsiun Huang
  • Patent number: 8957805
    Abstract: A balanced signal processing circuit includes: a comparator; a first capacitor having a first end connected to a non-inverting input terminal of the comparator; a second capacitor having a first end connected to an inverting input terminal of the comparator; a first switch configured to apply a voltage signal to the first end of the first capacitor; a second switch configured to apply a voltage signal to the first end of the second capacitor; an operation state detection section configured to detect an operation state of the comparator; and an offset voltage correction section configured to apply a predetermined offset voltage to a second end of the first capacitor and a second end of the second capacitor when the operation state detection section detects an abnormal operation state of the comparator.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 17, 2015
    Assignee: Sony Corporation
    Inventor: Atsumi Niwa
  • Patent number: 8947277
    Abstract: A sample-and-hold circuit including an operational amplifier configured to output a result signal to the ADC; a feedback capacitor connected between an input terminal and an output terminal of the operational amplifier to form a feedback path; a plurality of sampling capacitor blocks each connected to one of a plurality of channels and configured to sample and hold an analog signal input to each of the channels; a plurality of controllers each connected between one of the sampling capacitor blocks and the operational amplifier; and a reset unit connected between a reference voltage source and the input terminal of the operational amplifier to reset the operational amplifier when the operational amplifier does not perform a holding operation. The plurality of controllers configured to switch the sampled signal so that held signals for the respective channels are sequentially input to the operational amplifier.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Hoon Lee, Michael Choi, Eun Seok Shin
  • Patent number: 8928515
    Abstract: An analog-to-digital converter (ADC) comprises a sample/hold (S/H) unit, a digital-to-analog converter (DAC), a comparing unit, and a control unit. The S/H unit samples a first analog signal. The control unit comprises a compensating unit. The compensating unit receives an indication signal, and compensates a current bit and all its less significant bits, such that the sum of the current bit and all its less significant bits approximates a bit weight of the current bit, when the indication signal indicates that the comparison result cannot be determined. The compensating unit then outputs the compensated current bit and all its less significant bits together with more significant bits of the current bit.
    Type: Grant
    Filed: March 1, 2014
    Date of Patent: January 6, 2015
    Assignee: Beken Corporation
    Inventors: Desheng Hu, Dawei Guo
  • Patent number: 8928518
    Abstract: A charge redistribution SAR analog-to-digital converter includes a source of a reference voltage, a digital-to-analog converter, and a reset circuit. The digital-to-analog converter includes converter stages that range in significance from most significant to least significant. Each converter stage includes respective capacitors and switches. The switches are controllable to selectively connect the capacitors to the reference voltage or to ground. The capacitors of the converter stages are weighted in capacitance in accordance with significance of the converter stage. The reset circuit is to control the switches to reset the converter stages with a temporal offset between at least two of the converter stages. The temporal offset between the at least two of the converter stages reduces the dependence of the charge drawn from the reference voltage source during each conversion cycle on the sample of an analog input signal converted to a digital value during the conversion cycle.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: January 6, 2015
    Assignee: Keysight Technologies, Inc.
    Inventor: Dusan Stepanovic
  • Patent number: 8922415
    Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
    Type: Grant
    Filed: August 10, 2013
    Date of Patent: December 30, 2014
    Assignee: MaxLinear, Inc.
    Inventors: Eric Fogleman, Sheng Ye, Xuefeng Chen, Kok Lim Chan
  • Patent number: 8912942
    Abstract: A SAR ADC and a method thereof are provided. Particularly, in each bit determining duration of last several bit determining durations, a comparer is used to consecutively compare a first potential with a second potential on a sampling and digital-to-analog converting circuit a plurality of times to obtain a plurality of comparison results, and then an SAR control circuit generates a corresponding output bit according to the obtained plurality of comparison results.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: December 16, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Jian-Ru Lin, Shih-Hsiun Huang
  • Patent number: 8896476
    Abstract: A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time ?MV, outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time ?MV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator. In a preferred embodiment, the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: November 25, 2014
    Assignee: Technische Universiteit Eindhoven
    Inventor: Pieter Joost Adriaan Harpe
  • Patent number: 8884801
    Abstract: The present invention is directed to signal processing systems and methods thereof. In various embodiments, the present invention provides an analog-to-digital conversion (ADC) system that includes a flash ADC portion and a time-interleaved parallel SAR portion. For an n-bit ADC process, the flash ADC portion converts k MSBs of the n bits during a single cycle, and the SAR portion converts n?k LSBs in m number of cycles. The SAR portion includes a number of SAR channels that perform A/D conversion in parallel, and the k MSB from the course flash converter is verified for errors by the SAR portion and allows a net saving of the power consumption by reducing the number of fine resolution SARs. There are other embodiments as well.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: November 11, 2014
    Assignee: Inphi Corporation
    Inventor: Mohammad Ranjbar
  • Patent number: 8878714
    Abstract: Method and apparatus for mapping the converted voltage value by electric charge value proportional to the converted voltage value and in accumulation of charge in the sampling capacitor until the voltage on this capacitor is equal to the converted voltage. Furthermore, realization of the process of that electric charge redistribution in the array of redistribution by changes of states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module. As soon as accumulation of electric charge in the sampling capacitor is terminated, electric charge is accumulated in the additional sampling capacitor then the process of that electric charge redistribution is realized and relevant values are assigned to bits of the digital word. When a trigger signal is detected, next cycle begins and electric charge is accumulated in the sampling capacitor.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: November 4, 2014
    Assignee: Akademia Gorniczo-Hutnicza Im. Stanislawa Staszica
    Inventors: Dariusz Koscielnik, Marek Miskowicz
  • Patent number: 8847811
    Abstract: Examples are provided for converting an analog signal to a digital output signal using serial-ripple analog-to-digital conversion (ADC). An ADC circuit may include conversion stages coupled in series. Each conversion stage may generate a bit for the digital output signal. A data latch may receive bits for the digital output signal from the conversion stages and to provide the digital output signal based on the bits. A conversion stage may include a comparator circuit and a multiplexer circuit. The comparator circuit may compare a sampled input signal with a reference signal and to generate the associated bit of the digital output signal based on a result of the comparison. The multiplexer circuit may provide an associated reference signal to a comparator circuit of a next conversion stage, where the next conversion stage is subsequent to the conversion stage.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: September 30, 2014
    Assignee: Semtech Corporation
    Inventors: Ark-Chew Wong, Olivier Jacques Nys, Jonathan Muller
  • Patent number: 8836549
    Abstract: A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 16, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Robert Schell, Michael R. Elliott
  • Patent number: 8816892
    Abstract: A successive approximation A/D converter which includes a sub ranging classifier that receives an input signal and classifies said input signal according to plural different highest resolution bits, to determine a range of the input signal, and creating a set of most significant bits based on said range, said subranging classifier also setting and determining an offset based on said range, and a successive approximation A/D converted that converting lowest resolution parts of the input signal as adjusted by the offset.
    Type: Grant
    Filed: October 20, 2012
    Date of Patent: August 26, 2014
    Assignee: Forza Silicon Corporation
    Inventors: Steven Huang, Ramy Tantawy, Daniel Van Blerkom, Barmak Mansoorian
  • Patent number: 8810444
    Abstract: An analog-to-digital converting circuit includes a first comparison circuit configured to compare a first analog signal associated with a first digital signal with an analog input signal and output a first selection signal based on a result of the comparison, a second comparison circuit configured to compare a second analog signal associated with a second digital signal with the analog input signal and output a second selection signal based on a result of the comparison, and a selection circuit configured to generate intermediate digital signals associated with the first digital signal and output one of the intermediate digital signals as the first digital signal and another of the intermediate digital signals as the second digital signal, based on the first selection signal and the second selection signal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hee Chang Hwang
  • Patent number: 8786483
    Abstract: Embodiments of the present invention may provide an improved apparatus and method for correcting timing errors associated with process, voltage, and temperature effects in asynchronous successive approximation register (SAR) analog-to-digital converters (ADC). A SAR ADC may include a timer comprising programmable timing circuits that may ensure that the different components of the SAR ADC are operating according to a timing scheme. Operation of the timing circuits may vary with process, voltage, and temperature, which may adversely affect the timing/accuracy of the SAR ADC. The ADC may include a reference circuit provided on the same integrated circuit as the SAR ADC that may provide a timing reference for the timing circuits. If the reference circuit indicates that the timing circuits are operating faster or slower than ideal, timing values within the timing circuits may be revised to compensate for such variations.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 22, 2014
    Assignee: Analog Devices Technology
    Inventors: Frederick Carnegie Thompson, Barry Stakely
  • Patent number: 8773298
    Abstract: A successive approximation register A/D converter that obtains an output of N bits interrupts operation at a timing when the operation of the successive approximation register A/D converter is affected on the basis of circuit timing in an integrated circuit. The A/D converter performs a comparison between a sampling signal and a comparison reference voltage by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states following the comparison period. When an operation is temporarily interrupted, the A/D converter performs a comparison operation of a bit, whereas the comparison is not performed in the reserve period.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: July 8, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Matsumoto, Masao Ito, Osamu Matsumoto, Hiroto Suzuki
  • Patent number: 8754798
    Abstract: In one embodiment, a SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, a switch controlled by a sampling signal for connecting a common node to a ground node when the sampling signal is asserted; a plurality of switching networks controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting a bottom plate of a respective capacitor to an analog input signal, a ground node, a first reference voltage, or a second reference voltage depending on the asserted signal or bit; a comparator for detecting a polarity of a voltage at the common node and outputting a binary decision along with a complementary binary decision when a comparing signal is asserted; a logic gate for receiving the binary decision and the complementary binary decision and outputting a ready signal indicating whether a decision is readily made; a timer for rec
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: June 17, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Liang Lin
  • Patent number: 8754799
    Abstract: A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: June 17, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Michael Coln, Gary Carreau, Yoshinori Kusuda
  • Patent number: 8749423
    Abstract: An analog to digital converting device includes a first digital conversion (ADC) circuit configured to convert an inputted analog signal into a first digital signal, a first multiplying digital to analog converting (MDAC) circuit configured to amplify a difference between a first converted signal and the inputted analog signal, a second ADC circuit configured to convert an output of the first MDAC circuit into a second digital signal, a second MDAC circuit configured to amplify difference between a second converted signal converted from the second digital signal and the output of the first MDAC circuit, a third ADC circuit configured to convert an output of the second MDAC circuit into a third digital signal, and a common amplifying circuit shared by the first and the second MDAC circuits, wherein the common amplifying circuit consumes current based on which MDAC circuit the common amplifying circuit operates with.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: June 10, 2014
    Assignee: SK Hynix Inc.
    Inventors: Won Seok Hwang, Seung Hoon Lee, Jung Eun Song, Dong Hyun Hwang
  • Patent number: 8742971
    Abstract: A successive approximation analog-to-digital converter includes: a comparator for comparing first and second comparison voltages from a conversion module and respectively identical to first and second input voltages, which are transmitted to the conversion module via a switch module in an ON state; and a control module for controlling the switch module and the conversion module and generating a digital output that corresponds to a difference between the first and second input voltages based on first and second comparison signals from the comparator and a clock signal. The switch module includes two switch units each having a series connection of first and second switches, and a third switch coupled to a common node between the first and second switches.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: June 3, 2014
    Assignee: National Taiwan University
    Inventors: Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen
  • Patent number: 8717221
    Abstract: A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: May 6, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young-deuk Jeon, Tae Moon Roh, Jong-Kee Kwon
  • Patent number: 8704694
    Abstract: An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to ½L that in the A/D converter circuit 103.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: April 22, 2014
    Assignee: National University Corporation Shizuoka University
    Inventor: Shoji Kawahito
  • Patent number: 8686889
    Abstract: A system for signal processing comprising a cyclic analog to digital converter structure having a first stage and a second stage, wherein the first stage is configured to receive an input signal to perform 1.5 bits/stage ADC and to generate a first stage output signal, and the second stage is configured to receive the first stage output signal and to perform fine offset tuning using a final conversion phase. The second stage further configured to perform 1.5 bits/stage ADC and to generate a second stage output that is fed back to the first stage to iteratively generate a next 1.5 bits, until (N?3) most significant bits of N bits of data are generated. A third stage configured to generate a three least significant bits of the N bits of data using a flash ADC sampling circuit that samples a residue signal at the output of the first stage.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 1, 2014
    Assignee: Conexant Systems, Inc.
    Inventors: Chandrashekar A. Reddy, Yagneshwara Ramakrishna Rao Vadapalli
  • Patent number: 8674869
    Abstract: Each of cascade-connected one-bit A/D converters includes first and second amplifier circuits receiving first and second input signals, a third amplifier circuit that outputs an interpolation value of outputs of the first and second amplifier circuits, a comparator that outputs a binary signal having value determined by a polarity of an output of the third amplifier circuit, and a selector that selects two of three outputs of the first to third amplifier circuits, based on a value of the comparator. The selector is set such that direct-current transfer characteristics of two outputs of the selector are folded and symmetrical relative to the midpoint of the first and second input signals.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: March 18, 2014
    Assignee: NEC Corporation
    Inventor: Hidemi Noguchi
  • Patent number: 8659463
    Abstract: Provided are a successive approximation register analog-to-digital converter and an operation method thereof. The method includes latching input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the input signals to a latch; latching input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a first period of amplification by using a preamplifier; and latching input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a second period of amplification by using the preamplifier.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: February 25, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Kyun Cho, Jae Ho Jung