Abstract: A successive approximation A/D converter which includes a sub ranging classifier that receives an input signal and classifies said input signal according to plural different highest resolution bits, to determine a range of the input signal, and creating a set of most significant bits based on said range, said subranging classifier also setting and determining an offset based on said range, and a successive approximation A/D converted that converting lowest resolution parts of the input signal as adjusted by the offset.

Abstract: An analog-to-digital converting circuit includes a first comparison circuit configured to compare a first analog signal associated with a first digital signal with an analog input signal and output a first selection signal based on a result of the comparison, a second comparison circuit configured to compare a second analog signal associated with a second digital signal with the analog input signal and output a second selection signal based on a result of the comparison, and a selection circuit configured to generate intermediate digital signals associated with the first digital signal and output one of the intermediate digital signals as the first digital signal and another of the intermediate digital signals as the second digital signal, based on the first selection signal and the second selection signal.

Abstract: Embodiments of the present invention may provide an improved apparatus and method for correcting timing errors associated with process, voltage, and temperature effects in asynchronous successive approximation register (SAR) analog-to-digital converters (ADC). A SAR ADC may include a timer comprising programmable timing circuits that may ensure that the different components of the SAR ADC are operating according to a timing scheme. Operation of the timing circuits may vary with process, voltage, and temperature, which may adversely affect the timing/accuracy of the SAR ADC. The ADC may include a reference circuit provided on the same integrated circuit as the SAR ADC that may provide a timing reference for the timing circuits. If the reference circuit indicates that the timing circuits are operating faster or slower than ideal, timing values within the timing circuits may be revised to compensate for such variations.

Abstract: A successive approximation register A/D converter that obtains an output of N bits interrupts operation at a timing when the operation of the successive approximation register A/D converter is affected on the basis of circuit timing in an integrated circuit. The A/D converter performs a comparison between a sampling signal and a comparison reference voltage by a sampling period in which an analog signal is sampled, a comparison period of N states in which the sampled signal is sequentially compared with a comparison voltage for each bit, and a reserve period of M states following the comparison period. When an operation is temporarily interrupted, the A/D converter performs a comparison operation of a bit, whereas the comparison is not performed in the reserve period.

Abstract: In one embodiment, a SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, a switch controlled by a sampling signal for connecting a common node to a ground node when the sampling signal is asserted; a plurality of switching networks controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting a bottom plate of a respective capacitor to an analog input signal, a ground node, a first reference voltage, or a second reference voltage depending on the asserted signal or bit; a comparator for detecting a polarity of a voltage at the common node and outputting a binary decision along with a complementary binary decision when a comparing signal is asserted; a logic gate for receiving the binary decision and the complementary binary decision and outputting a ready signal indicating whether a decision is readily made; a timer for rec

Abstract: A circuit system for performing correlated double sampling may include a signal sampling stage having an amplifier with a feedback capacitor and a pair of storage capacitors coupled to an output of the amplifier, and a differential analog to digital converter (ADC) having a pair of inputs coupled respectively to storage capacitors of the signal sampling stage. The signal sampling stage may receive reset and signal values from a sensor device and may store processed versions of those signals on respective storage capacitors. The differential ADC may generate a digital value representing a signal captured by the sensor device from a differential digitization operation performed on the processed versions of the reset and signal values. In this manner, the system may correct for any signal errors introduced by components of the sampling stage.

Abstract: An analog to digital converting device includes a first digital conversion (ADC) circuit configured to convert an inputted analog signal into a first digital signal, a first multiplying digital to analog converting (MDAC) circuit configured to amplify a difference between a first converted signal and the inputted analog signal, a second ADC circuit configured to convert an output of the first MDAC circuit into a second digital signal, a second MDAC circuit configured to amplify difference between a second converted signal converted from the second digital signal and the output of the first MDAC circuit, a third ADC circuit configured to convert an output of the second MDAC circuit into a third digital signal, and a common amplifying circuit shared by the first and the second MDAC circuits, wherein the common amplifying circuit consumes current based on which MDAC circuit the common amplifying circuit operates with.

Abstract: A successive approximation analog-to-digital converter includes: a comparator for comparing first and second comparison voltages from a conversion module and respectively identical to first and second input voltages, which are transmitted to the conversion module via a switch module in an ON state; and a control module for controlling the switch module and the conversion module and generating a digital output that corresponds to a difference between the first and second input voltages based on first and second comparison signals from the comparator and a clock signal. The switch module includes two switch units each having a series connection of first and second switches, and a third switch coupled to a common node between the first and second switches.

Abstract: A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result.

Abstract: An A/D converter 101 comprises a first cyclic A/D converter circuit 103 and an A/D converter circuit 105. The A/D converter 101 includes a record circuit 107 for storing conversion results from the A/D converter circuits 103, 105. The record circuit 107 includes an upper-bit record circuit 107a and a lower-bit circuit 107b. The cyclic A/D converter circuit 103 receives an analog value SA and generates a first digital value SD1 indicating the analog value SA and a residue value RD. The A/D converter circuit 105 receives the residue value RD and generates a second digital value SD2 having lower M bits indicating the residue value RD. The conversion accuracy in the A/D converter circuit 105 can be lowered to ½L that in the A/D converter circuit 103.

Abstract: A system for signal processing comprising a cyclic analog to digital converter structure having a first stage and a second stage, wherein the first stage is configured to receive an input signal to perform 1.5 bits/stage ADC and to generate a first stage output signal, and the second stage is configured to receive the first stage output signal and to perform fine offset tuning using a final conversion phase. The second stage further configured to perform 1.5 bits/stage ADC and to generate a second stage output that is fed back to the first stage to iteratively generate a next 1.5 bits, until (N?3) most significant bits of N bits of data are generated. A third stage configured to generate a three least significant bits of the N bits of data using a flash ADC sampling circuit that samples a residue signal at the output of the first stage.

Abstract: Each of cascade-connected one-bit A/D converters includes first and second amplifier circuits receiving first and second input signals, a third amplifier circuit that outputs an interpolation value of outputs of the first and second amplifier circuits, a comparator that outputs a binary signal having value determined by a polarity of an output of the third amplifier circuit, and a selector that selects two of three outputs of the first to third amplifier circuits, based on a value of the comparator. The selector is set such that direct-current transfer characteristics of two outputs of the selector are folded and symmetrical relative to the midpoint of the first and second input signals.

Abstract: The present inventive concept relates to an analog-digital converter. The analog-digital converter includes a clock generating unit generating a clock signal; a clock delay adjusting unit outputting one of a first clock signal to a Kth clock signal according to a control signal; a capacitive digital-analog converting unit outputting a difference between the analog signal and a reference signal; a comparison unit judging whether an output of the capacitive digital-analog converting unit is 0, a positive number, or a negative number, in response to an output of the clock delay adjusting unit; and an SAR logic unit transferring an output of the comparison unit to the capacitive digital-analog converting unit in response to an output of the clock delay adjusting unit and performing a successive approximation operation to output the N-bit digital signal.

Abstract: Provided are a successive approximation register analog-to-digital converter and an operation method thereof. The method includes latching input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the input signals to a latch; latching input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a first period of amplification by using a preamplifier; and latching input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a second period of amplification by using the preamplifier.

Abstract: A non-binary successive approximation analogue to digital converter, for converting using successive conversion steps, is operable in first and second modes. The first and second modes have different noise properties and the converter is switched between the modes during the conversion process.

Abstract: A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) includes a Sample-and-Hold Amplifier (SHA) for sampling and holding an externally input analog voltage, a comparator for comparing a level of the sampled and held analog voltage with a level of an analog signal corresponding to n bits and generating a comparison signal according to result of comparison, an SAR logic circuit for sequentially generating a digital signal from a Most significant Bit (MSB) to a Least Significant Bit (LSB) in response to the comparison signal, a Digital-to-Analog Converter (DAC) for providing the analog signal to the comparator, and an output register for holding the sequentially generated digital signal from the MSB to the LSB to generate an n-bit digital signal, wherein, upon externally receiving a start signal, the SAR logic circuit generates a digital signal of a MSB having a one-bit phase delay compared with the start signal.

Abstract: In one embodiment, a data acquisition circuit includes an analog multiplexer to receive analog signals and select an analog signal for output, an ADC coupled to the multiplexer to receive the analog signal and perform a conversion of the analog signal to a N-bit digital value in at least N clock cycles, and a controller coupled to the ADC to enable the ADC to compare the analog signal to a second analog signal in a single clock cycle.

Abstract: An apparatus implements analog-to-digital conversion with released requirement on the reference settling errors and improved immunity to the noise originated from the power supply, ground and the positive and negative references. It includes a comparator comparing the specified reference levels with the analog input, multi DAC sub-circuits with separate non-binary search schemes applied to and a digital control logic controlling the reference search process. No cross-talk occurs among the different non-binary search algorithms. Each redundancy scheme is localized in a respective DAC sub-circuit and covers the reference levels only in the current DAC. The non-binary search algorithms are fulfilled in the digital domain and trade the non-binary search step sizes with the number of the search steps to introduce redundancy to the reference levels.

Abstract: Certain aspects of the present disclosure relate to a technique for producing a difference value by offsetting a current value of an analog signal with a stored previous value of the analog signal, and generating a digital representation of the difference value. Digital representations obtained by this technique may be sent over a channel to a receiver device for reconstruction of the original analog signal. An integrator of the receiver device may be configured to process (sum) the received samples to generate a reconstructed version of the original signal.

Abstract: A SAR ADC converting an analog signal into a digital signal having N bits counting from a most significant bit to a least significant bit includes a comparator comparing a positive component with a negative component of the analog signal, two CDACs and a logic circuit. For at least one i-th bit cycle of N bit cycle except a least significant bit cycle, one of a pair of capacitors relating to (i+1)-th bit respectively arranged in the two CDACs is switched according to a first comparing result of the comparator. After one of the pair of capacitors is switched, the comparator compares the positive component with the negative component of the analog signal again and generates a second comparing result. Then whether each one of capacitors relating to i-th bit in the two CDAC is to be switched is determined according to the first and the second comparing result.

Abstract: Examples of systems and methods are provided for converting an analog input signal to a digital output signal. A system may include a current mode (CM) digital-to-analog converter (DAC) circuit to provide a DAC current. A comparator circuit may be configured to generate a comparator signal in response to an error signal determined based on the DAC current and the analog input signal. A successive approximation register circuit may be configured to generate at least one of a DAC-code signal or the digital output signal, in response to the comparator signal. The DAC-code signal may be used by the CM DAC circuit to control the DAC current.

Abstract: In accordance with an embodiment, a method of performing a successive approximation analog-to-digital (A/D) conversion includes determining a voltage range of an analog input voltage in a single cycle using a multi-bit flash A/D converter, determining an initial D/A value for a successive approximation based on determining the voltage range, and successively approximating the analog input voltage. Successively approximating includes providing the initial D/A value to a D/A converter, comparing an output of the D/A converter with the analog input voltage, and determining a further D/A value based on the comparing.

Abstract: A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN?) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage.

Abstract: A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage.

Abstract: INL values are determined for sub-segments of a DAC adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the sub-segments of the DAC, and a second set of correction codes that can be used to ensure that all values of DNL>?1 (to ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2^N possible digital input codes (that can be accepted by the DAC) to more than 2^N possible digital output codes, to ensure that all values of DNL>?1. Such stored first and second sets are thereafter used when performing digital to analog conversions.

Abstract: A current input analog-to-digital converter and a corresponding current measurement circuit is disclosed. In accordance with one example of the invention, an analog-to-digital conversion circuit includes a register for storing a digital register value and a digital-to-analog converter that is configured to provide a reference current at a circuit node which is set in accordance to the digital register value. The electric potential of the input node is responsive to the reference current set. A comparator circuit is configured to compare the potential of the circuit node with at least one threshold, thus assessing whether the potential of the circuit node is at least approximately at a desired value. Control circuitry is responsive to the comparator circuit and is configured to adjust the digital register value stored in the register and to adjust the reference current until the comparator indicates that the potential of the circuit node does not deviate from the desired value.

Abstract: An analog to digital converter converts an input analog signal to a digital representation using successive approximation logic to generate a plurality of digital values approximating the analog signal. Evaluation logic evaluates each of the digital values by converting each of the digital values in a digital to analog converter (DAC) to a DAC analog signal and comparing the DAC analog signal to the input analog signal to determine a comparison result used by the successive approximation logic to generate a next one of the digital values. An evaluation time period for one or more bits of the digital representation is longer than for one or more other bits in the digital representation. The DAC includes a resistor ladder. Reference voltages of the DAC are increased for evaluation of the least significant bit (LSB) to obtain more accurate results without increasing a number of resistors.

Abstract: Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array.

Abstract: The invention includes a successive approximation register, a digital-to-analog converter, a comparator and a control stage. The control stage initially sets the successive approximation register to a first digital value. The digital-to-analog converter converts the digital value stored in the successive approximation register to an analog value. The comparator compares the converted digital value with an analog input value. The control stage restricts subsequent analog-to-digital conversion for the analog input value to a search interval above or below the first digital value depending on whether the analog input value is greater or lower than the converted analog value of the first digital value.

Abstract: A redundant signed digit (RSD) analog to digital converter (ADC) receives a high voltage (VRH) and a low voltage (VRL) for use in converting an input signal to a digital signal. A doubling circuit receives the input signal and doubles the input signal to provide a doubled input signal using an amplifier and a first capacitor. The first capacitor has a capacitance of a first magnitude. A VR circuit continues processing the doubled input signal to provide a 2VR signal. A Vref circuit (VR+C5 and C6) provides a first RSD residue signal that is equal to a sum of a reference Vref and the 2VR signal. The first RSD residue signal is produced using the amplifier, a second capacitor, and the high power supply voltage. The second capacitor has a capacitance equal to half that of the first capacitor.

Abstract: A successive approximation analog to digital converter (SA-ADC) employs a binary-weighted digital to analog converter (DAC) to perform a non-binary search in determining a digital representation of a sample of an analog signal. In an embodiment, a subset of iterations needed to convert an analog sample to a digital value is performed using non-binary search with a radix of conversion less than two. As a result, search windows in iterations corresponding to the non-binary search overlap, and correction of errors due to a comparator used in the SA-ADC is rendered possible. Error correction being possible due to the non-binary search, the comparator is operated in a low-bandwidth, and hence low-power, mode during the non-binary search. The non-binary search in combination with the binary-weighted architecture of the DAC offer several benefits such as for example, less-complex implementation, shorter conversion time, easier and compact layout and lower power consumption.

Abstract: A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage.

Abstract: An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.

Abstract: To provide a semiconductor device including an A/D converter circuit that is capable of performing A/D conversion with high accuracy and high resolution and that can be reduced in size. One loop resistance wiring is shared by a plurality of power supply switches and a plurality of output circuits, and a reference voltage having a triangular (step-like) wave generated using the resistance wiring and the plurality of power supply switches is utilized. Thus, high-accuracy digital signals can be obtained using such an A/D converter circuit that can be reduced in size as an output circuit, without using a complicated circuit structure. Further, the number of constituent elements of the A/D converter circuit is small, whereby in the case of providing A/D converter circuits in parallel, variation between the A/D converter circuits can be made small.

Abstract: A method and an apparatus for evaluating weighting of elements of a DAC and a SAR ADC using the same are provided. An equivalent weighting of each composed element is obtained by adding a reference element with a reference weighting, an auxiliary DAC, and a search circuit into the SAR ADC, and the equivalent weighting is represented by the reference weighting. The SAR ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and the successive approximation result of each input signal. The present disclosure prevents the necessity of matching each composed element of the DAC in the SAR ADC.

Abstract: An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.

Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plu

Abstract: A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.

Abstract: A successive approximation AD conversion circuit has improved conversion accuracy without prolonging the time necessary for conversion. The successive approximation AD conversion circuit includes a plurality of amplifier stages cascaded together through coupling capacitances, and a comparator circuit which determines whether an input analog voltage is greater or less than comparison voltages. The comparator circuit includes a first comparator unit and a second comparator unit having a common initial amplifier stage among a plurality of amplifier stages, and, respectively, a first amplifier stage and second amplifier stage connected after the common stage through respective coupling capacitances; and first and second comparison point shift circuits connected respectively to input terminals of the first and second amplifier stages.

Abstract: An analog-to-digital converter (ADC) converts an analog input signal to a digital output signal by sampling an analog input signal to obtain an analog sample and then converting the analog sample to the digital output signal using a successive approximation algorithm. The method decreases ADC conversion time and increases ADC throughput.

Abstract: An analog-to-digital converter comprises a switched capacitor array configured to receive an analog input signal, a comparator having inputs coupled to respective outputs of the switched capacitor array, register circuitry having inputs coupled to respective outputs of the comparator, and a metastability detector associated with the register circuitry. The register circuitry is configured to generate control signals for application to respective control inputs of the switched capacitor array and to provide a digital output signal corresponding to the analog input signal. The metastability detector is configured to detect a metastability condition relating to signals at the respective outputs of the comparator. The register circuitry responsive to detection of the metastability condition forces bits of the digital output signal to particular logic levels.

Abstract: An A/D converter circuit includes a comparison circuit that performs a process to compare an added signal of a sampled signal of an input signal and a code signal with a D/A output signal, or a process to compare the sampled signal with an added signal of the D/A output signal and the code signal, a control circuit that outputs output data obtained based on successive approximation result data and the code data as A/D conversion data of the input signal, a first D/A converter circuit that D/A converts the data for successive approximation, a second D/A converter circuit that D/A converts code data that changes over time, and a correction section that performs a correction process, to correct the successive approximation result data so as not to overflow due to code shifting using the code data.

Abstract: A method for a successive approximation register ADC which includes at least one capacitor array and a plurality of switches is provided, in which the capacitors of the capacitor array are one-to-one corresponding to the switches. The method includes the following steps: firstly, at least one multiplexer is configured. Then, a first comparison voltage is outputted based on the terminal voltages on the terminals of the capacitor array, and a comparison result is outputted according to the first comparison voltage and a second comparison voltage. Afterwards, a sequence of comparisons is controlled based on the comparison result to enter into a sequence of comparison phases. Finally, the switches are orderly selected, by the multiplexer based on the comparison phases, to switch directly according to the comparison result.

Abstract: A solid-state image pickup device may include: an image pickup unit in which a plurality of pixels are arranged in a matrix; a sample-and-hold unit having a switch element and a capacitance element; a frequency conversion unit in which a plurality of stages of inverting circuits are connected, the pixel signal is supplied to the first power supply terminal, and a start signal for starting clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits; a counting unit that counts the clock output from the frequency conversion unit; and a buffer circuit provided between a first terminal of the capacitance element connected to the switch element and the first power supply terminal, wherein a second terminal of the capacitance element is connected to the second power supply terminal.

Abstract: A system and a method are disclosed for establishing the biasing point of a comparator in a successive approximation analog-to-digital converter (SAR ADC) by transferring an electric charge from a series of capacitors in a switched-capacitor array into a frame capacitor. The frame capacitor is formed by a parasitic capacitance between the series of capacitors and a conductive metal frame that surrounds the capacitors. To induce the charge transfer, the conductive metal frame is connected to a clock signal, which alternately drives the frame between a supply voltage and ground. By using the frame capacitor instead of a separate power source to establish the biasing point, the current consumption of the SAR ADC is reduced.

Abstract: An A/D conversion apparatus includes an N-stage pulse circulating circuit including N (N is a natural number, N?3) inverting circuits connected in a ring shape, the inverting circuits delaying an input pulse signal by a delay time corresponding to an amplitude of a separately input analog input signal, and outputting inverted pulse signals obtained by inverting the pulse signal, a counter unit that counts a number of circulations by which the pulse signal has circulated in the pulse circulating circuit within a predetermined time based on the inverted pulse signal output from one of the N inverting circuits, and a switching unit that switches an output destination of the inverted pulse signal, which is output from an inverting circuit of an Mth (M is an odd natural number, 1?M?N?1) stage of the pulse circulating circuit, according to a change in an operation environment.

Abstract: An analog-to-digital converter with a resolution booster is provided. The analog-to-digital converter may include a successive approximation analog-to-digital converter, a resolution booster, and an output combiner. The successive approximation analog-to-digital converter may be configured to convert an analog signal into digital data. The resolution booster may be selectively activated to enhance the resolution of the successive approximation analog-to-digital converter, and the output combiner may be configured to combine the respective outputs of the successive approximation analog-to-digital converter and the resolution booster.

Abstract: A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.

Abstract: An analog-to-digital converter including a voltage generation unit and a plurality of sub ADCs, each including a selection unit for selecting a voltage generated by the voltage generation unit based on a number and forwarding the selected voltage to a comparator arrangement. The selection unit includes first and second switch layers. The first switch layer includes a plurality of switch groups, each including a plurality of switch devices, each connected to a unique output terminal of the voltage generation unit with a first terminal and to a common node of the switch group with a second terminal. The second switch layer includes a switch device between the common node of each switch group and the first output terminal of the selection unit and a switch device between the common node and the second output terminal of the selection unit. A control unit generates control signals for the switch devices.

Abstract: In a successive approximation ADC, resolution is limited because a distortion occurs in an A/D conversion result due to a voltage dependence of a sampling capacitance. An A/D converter includes a sampling capacitor part in which capacitors equal in capacitance value to each other are connected inversely, a successive approximation A/D conversion part that conducts A/D conversion on the sampling charge, a digital correction part that corrects capacitance variation of internal DAC capacitors in the successive approximation A/D conversion part, and a digital correction part that digitally corrects a third-order or more factor of a voltage dependence of the sampling charge.