Abstract: Circuitry for detecting a capacitive load coupled between a first node and a second node, the circuitry comprising: drive circuitry for applying a first voltage to a first node over a first time period; processing circuitry configured to: measure a second voltage at the first node; and determine that the load is a capacitive load based on the second voltage.

Abstract: In one example, an apparatus comprises: a comparator; a sampling capacitor having a first plate and a second plate. The first plate is coupled with an output of a charge sensing unit that senses charge generated by a photodiode, whereas the second plate is coupled with an input of the comparator. The apparatus further includes a controller configured to: at a first time, set a first voltage across the sampling capacitor based on an output voltage of the charge sensing unit; reset the charge sensing unit to set the first plate at a second voltage and to set the second plate at a third voltage based on the first voltage and the second voltage; compare, using the comparator, the third voltage against one or more thresholds; and generate, based on the comparison result, a quantization result of the output voltage of the charge sensing unit at the first time.

Abstract: An imaging sensor comprising: an imaging chip in which a plurality of pixel are arranged in a matrix; and a signal processing chip that is each provided for one or more pixel columns or one or more pixel rows, has a device that performs signal processing on a pixel signal output from a pixel, and is stacked with the imaging chip is provided. For example, the device that performs signal processing is an A/D converter that converts a pixel signal output from the pixel into a digital signal, and when a pixel signal output from the pixel is converted into a digital signal, at least two or more A/D converters among the A/D converters are controlled in parallel.

Abstract: A display panel, a pressure detection method of the display panel and a display device are disclosed. The display panel includes: a plurality of pressure sensors including first and second sensing signal measurement terminals; a detection module; a first multiplexer and a second multiplexer. Each first signal inputting terminal of the first multiplexer is electrically connected to one of the first sensing signal measurement terminals. Each second signal inputting terminal of the first multiplexer is electrically connected to one of the second sensing signal measurement terminals. First and second signal outputting terminals of the first multiplexer are electrically connected to first and second detection signal terminals, respectively. The first multiplexer controls a connection between one of the first signal inputting terminals and the first detection signal terminal and a connection between one of the second signal inputting terminals and the second detection signal terminal.

Abstract: The embodiments described herein provide analog-to-digital converters (ADCs) and systems and methods for calibrating ADCs, including ADCs with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from an ADC with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values. These correction values can then be used to calibrate the ADC during later operation. Such a calibration technique can provide effective calibration for a variety of ADCs, including ADCs that use inverter-based voltage-to-current (VI) converters and current-controlled ring oscillators.

Abstract: A semiconductor device includes: an element array portion in which unit elements are disposed in a matrix; and a signal processing portion including a signal processing circuit executing predetermined signal processing based on unit signals outputted from the circuit elements, respectively, every column, in which a function of the signal processing circuit is controlled in such a way that power consumption of the signal processing circuit concerned corresponding to the unit elements each not required becomes lower in a phase of an element selection mode in which only information on a part of the unit pixels for one row in the element array portion is required than in a phase of a normal operation mode.

Abstract: To suppress detection accuracy of a measurement resistance from decreasing by an on-resistance of a selector switch. The selector switch is provided between a first node coupled to a first voltage through a reference resistance and multiple second nodes coupled to the second voltage through measurement resistances, and selects the second node to be coupled to the first node with the selector switch. A correction circuit generates a voltage obtained by adding the second voltage to a voltage between the second node and the first node as a correction voltage. A double integral ADC finds a first integral time elapsed when a difference voltage of the correction voltage to a voltage of the first node is integrated to the first voltage and a second integral time elapsed when the difference voltage of the first voltage to the voltage of the first node is integrated to the correction voltage.

Abstract: An apparatus including a detecting unit that detects information indicating a state of an organism from the organism or an organism specimen extracted from the organism and outputs the detected information as a current, a current-voltage conversion circuit that converts the current output from the detecting unit into a voltage, a double-integration-type A/D conversion circuit having an integration capacitor that is charged based on a voltage output from the current-voltage conversion circuit and is thereafter discharged, and a counter that measures a charge time during which the integration capacitor is charged and a discharge time during which the integration capacitor is discharged, the A/D conversion circuit converting into digital quantities the charge time and the discharge time measured by the counter, and outputting the digital quantities, and an information processing unit that calculates a state quantity of the organism based on the digital quantities output from the A/D conversion circuit.

Abstract: An imaging device includes a comparator that compares a noise signal with each of a first reference signal and a second reference signal having potentials with different changing quantities per unit time, and that compares a photoelectric conversion signal with each of the first reference signal and the second reference signal. Also, the imaging device AD-converts signals obtained by amplifying the noise signal by a first gain and a second gain having different gains, and AD-converts a signal obtained by amplifying the photoelectric conversion signal by one of a first gain and a second gain.

Abstract: Disclosed is a time-to-digital (TDC) converter comprising an analog voltage source. An analog-to-digital converter quantizes two voltage samples in response to receiving a first input signal at a first time t1 and a second input signal at a second time t2. The first and second digital signals are combined to produce a digital signal that represents the difference (t2?t1).

Abstract: A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed.

Abstract: One or more techniques and/or systems described herein implement, among other things, a parabolic curve for a ramp signal in a data acquisition component, where the curve can be effectively calibrated and used to provide a settling period to mitigate noise. That is, a ramp generator can generate a ramp signal that has a parabolic voltage curve with two substantially mirroring halves. A comparator can compare a first portion of the parabolic voltage curve with a voltage signal indicative of a number of photons detected by a detection array. A second portion of the parabolic voltage curve is used as a temporal delay so that circuitry, such as the ramp generator, can settle.

Abstract: Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first condition and generating a second value by sensing the data location under a second condition. The method may further include combining the first value with the second value to identify data conveyed by the data location.

Abstract: A method of an aspect includes acquiring analog image data with a pixel array, and reading out the analog image data from the pixel array. The analog image data is converted to digital image data by performing an analog-to-digital (A/D) conversion using a multiple slope voltage ramp. At least some of the digital image data is adjusted with calibration data. Other methods, apparatus, and systems, are also disclosed.

Abstract: An apparatus including a detecting unit that detects information indicating a state of an organism from the organism or an organism specimen extracted from the organism and outputs the detected information as a current, a current-voltage conversion circuit that converts the current output from the detecting unit into a voltage, a double-integration-type A/D conversion circuit having an integration capacitor that is charged based on a voltage output from the current-voltage conversion circuit and is thereafter discharged, and a counter that measures a charge time during which the integration capacitor is charged and a discharge time during which the integration capacitor is discharged, the A/D conversion circuit converting into digital quantities the charge time and the discharge time measured by the counter, and outputting the digital quantities, and an information processing unit that calculates a state quantity of the organism based on the digital quantities output from the A/D conversion circuit.

Abstract: A ramp wave output circuit includes a ramp wave generation circuit generating a ramp wave, and a low-pass filter having a variable cutoff frequency, which receives the ramp wave. The low-pass filter operates at a first cutoff frequency for a predetermined time period after the receipt of the ramp wave, and at a second cutoff frequency, which is larger than the first cutoff frequency, after the predetermined time period has passed.

Abstract: A current mode dual-slope temperature-to-digital conversion device is disclosed. The conversion device comprises a temperature dependent current source and a reference current source. Firstly, a capacitor is charged by the temperature dependent current source. Next, the capacitor is discharged by the reference current source. The capacitor is coupled to at least one trigger, and the trigger sends out a first digital signal to a logic controller by the voltage of the capacitor. Then, the logic controller sends out a second digital signal to a time-to-digital converter according to the first digital signal. When the capacitor is discharged by the reference current source and before the first digital signal is varied, the converter receives the second digital signal and a clock signal to generate a corresponding digital output value.

Abstract: A coding method, apparatus, and medium with software encoded thereon to implement a coding method. The coding method includes encoding cluster of consecutive non-zero-valued coefficients, the encoding of a cluster including jointly encoding joint events that each are defined by at least two parameters: the number of zero-valued coefficients preceding the cluster, and the number of non-zero-valued coefficients in the cluster. The encoding of the cluster also includes encoding a parameter indicative of the number of amplitude-1 trailing non-zero-valued coefficients in the cluster, in one version with the parameter indicative of the number of trailing amplitude-1 coefficients part of the joint events such that the coding is according to a 3-dimensional joint variable length coding table. The method further includes encoding the amplitudes of the non-zero-valued coefficients that are not encoded by the joint encoding, e.g., encoding the amplitudes of the other than the trailing amplitude-1 coefficients.

Abstract: A coding method, apparatus, and medium with software encoded thereon to implement a coding method. The coding method includes jointly encoding joint events that each are defined by a cluster of consecutive non-zero-valued coefficients, each joint event defined by three parameters: the number of zero-valued coefficients preceding the cluster, the number of non-zero-valued coefficients in the cluster, and an indication of which trailing coefficients up to a maximum number of M trailing coefficients have amplitude greater than 1, with the coding using a 3-dimensional joint VLC table. The method further includes encoding the amplitude of the non-zero-valued trailing coefficients that have amplitude greater than 1 encoding the amplitude of any remaining non-zero-valued coefficients in the clusters that have more than M non-zero-valued coefficients.

Abstract: A double-integration signal processing apparatus for pulse width amplification and A/D conversion is provided. The current mode double-integration conversion apparatus includes: a current mode double-integration unit which integrates an input current in a predetermined time interval and outputs an integration voltage; a comparison unit which compares the integration voltage output from the current mode double-integration unit with a predetermined comparison voltage V k and outputs an comparison pulse signal; and a gate logic unit which performs a logic operation by using the comparison pulse signal of the comparison unit and an internal signal and outputs an logic operation pulse signal. Accordingly, the current mode double-integration conversion apparatus can be applied to various sensors.

Abstract: A method and apparatus are provided for sigma-delta (??) analog to digital conversion, the method including receiving an analog signal, sampling the received signal, comparing the sampled signal with a constant reference voltage, providing at least one high-order bit responsive to the constant reference comparison, comparing the sampled signal with a variable reference voltage, providing at least one low-order bit responsive to the variable reference comparison, and combining the at least one high-order bit with the at least one low-order bit; and the apparatus including a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least one low-order bit.

Abstract: Measurement amplification methods and devices for detecting the detuning of a measurement bridge (10) to which a bipolar, rectangular supply voltage (Us) is supplied. The methods and devices use integrating A/D conversion and are characterized in that a reference voltage (Uref) used for the A/D conversion undergoes polarity changes synchronized with the polarity changes of the supply voltage (Us). Offset and drift are eliminated by totaling an even number of individual measurements.

Abstract: Dual ramp analog-to-digital converters and methods allow for performing analog-to-digital conversion of an analog signal. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal and a coarse ramp to a same input of a comparator, and applying a fine ramp to another input of the comparator. Some dual ramp analog-to-digital converters and methods allow for applying the analog signal, a coarse ramp, and a fine ramp to a same input of a comparator. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal to an input of a first comparator, applying a coarse ramp to the input of the first comparator through a coarse ramp switch, applying the analog signal to an input of a second comparator, and applying a fine ramp to another input of the second comparator.

Abstract: A measuring device is disclosed for capacitive pressure and/or temperature measurement, particularly for tire pressure control systems, having at least one sensor, which has a capacitive measuring element to detect a state value, which is applied at an output-side measuring node of the measuring element, with at least one A/D converter operating according to the dual-slope method, with a charging/discharging circuit, for mutual charging and discharging of the measuring element and for generating a sawtooth-shaped measuring potential at the measuring node as a measure for the capacitance of the measuring element, with a period counter, which determines the periods of the measuring potential, and with a clock counter, which determines the cycles of a clock signal, which lie within the duration of at least one period of the measuring potential. The invention relates to a measuring method for capacitive pressure and/or temperature measurement.

Abstract: An AD converter includes an analog data storing unit, a first DA converter for converting an input digital data into a first analog reference voltage which varies within a first voltage range in a range of every possible signal voltage of the input analog data, a second DA converter for converting the input digital data into a second analog reference voltage which varies within a second voltage range in the range of every possible signal voltage of the input analog data, a first comparator for comparing the input analog data with the first reference voltage, a second comparator for comparing the input analog data with the second reference voltage and a digital data storing unit for storing a digital data corresponding to a point of time when a change of state occurs in the comparison results of each of the first and second comparators.

Abstract: An analog-to-digital converter (ADC) is presented. The ADC includes an error amplifier, a ramp generator, and a counting circuit. The error amplifier is used for receiving an output voltage and a reference voltage, and amplifying a difference between the output voltage and the reference voltage, so as to obtain a first voltage and a second voltage. The ramp generator is used for generating a ramp voltage which is increased along with time. The counting circuit is used for starting counting a digital value when the ramp voltage is larger than or equal to the first voltage, and stopping counting and outputting the digital value when the ramp voltage is larger than or equal to the second voltage.

Abstract: A solid state image pickup apparatus capable of reading a signal at a high speed while securing a wide dynamic range is provided. A signal based on a part of charges having overflown a photoelectric conversion unit (201) to a floating diffusion region (205) is quantified at an upper bit of an AD converter (206), and a signal based on charges stored in the photoelectric conversion unit (201) is quantified at a lower bit of the AD converter (206). Thereby, multi-bit data having a wide dynamic range can be taken out at a speed as high as possible without increasing the number of devices.

Abstract: A periodic signal is sampled. The sampling frequency is less than the Nyquist rate of the periodic signal. A period of the periodic signal is determined. A phase of the periodic signal is tracked to determine a sample's position on the period of the periodic signal. A replica of the periodic signal is reconstructed. A measurement of the periodic signal is determined based on a measurement of the replica of the periodic signal.

Abstract: Polarity independent precision measurement of an input voltage signal is accomplished using a voltage integrating circuit that receives a first positive reference voltage and the input voltage signal, wherein the first positive reference voltage is greater in magnitude than the input voltage signal. A resetting circuit is coupled to the voltage integrating circuit for stabilizing its output. A pair of comparators, each connected to the output of the voltage integrating circuit, make voltage comparisons against a second reference voltage and a third reference voltage respectively, wherein the second and third reference voltages are greater in magnitude than the first reference voltage. A time interval measurement circuit receives the outputs of the pair of comparators, and operates to measure the time taken for the output of the voltage integrating circuit to transit to the second reference voltage level and the third reference voltage level.

Abstract: A transmission line analog-to-digital converter uses an unterminated transmission line driven by a current source to generate a stair-step waveform having equal time step periods for measuring the conversion time as a digital output value of an analog input. The converter has the advantages of simplicity, accuracy, high speed, low transistor count, and low power consumption. Fast successive approximation converters can be used for improved speed and accuracy of digital conversion of analog signals.

Abstract: An integration type A/D converter has two sets of integration type A/D converter sections which can be periodically switched over at a predetermined period, with one converter section integrating an input signal to give an integral output voltage and another converter section performing A/D conversion of the integral output voltage. Further, use is made of a residual time interval in the period of A/D conversion, for the integration of the ground voltage and a reference voltage and for A/D conversions of the integrated voltages. The inventive A/D converter permits accurate measurement of continuous integral values of a given input signal.

Abstract: A multi-channel dual slope analog-digital converter with offset cancellation an hysteresis input is provided in the present invention, wherein a charge reset period and an auto zero period are eliminated, so as to shorten cycle time. An offset cancel capacitor is also eliminated, so that large chip area is avoided. With inserting a dummy cycle in between each measurement cycle, coupling error can be avoided between different conversion channels. Also, hysteresis property of a Schmitt comparator in the comparator unit manages to filter out minute residual voltage offset, so that the output of converter retains its residual voltage level. A multi-channel dual slope analog-digital converting method is also provided in the invention.

Abstract: A rail to rail dual slope analog to digital converter (ADC) is provided in the present invention. The circuit scheme has an input stage, an integrator stage, and a comparator stage, where an operational amplifier (OPAMP) can be comprised of each stage respectively. The positive input of the integrator OPAMP coupling to an analog ground, and switching the negative feedback loop of the input stage between an input voltage, a reference voltage, and a short circuit, controlling a plurality of switches among circuit connections results in different phases of the dual slope ADC. A finer resolution is thus obtained according to rail to rail input voltage range. Also, the integrator OPAMP can be eliminated from the circuit of the present invention in order to reduce pins, with connecting an end of the external integrator capacitor to ground.

Abstract: A reduced power analog-to-digital (A/D) converter is disclosed herein. Reference current to an op-amp used in an A/D converter is reduced during later conversion cycles in an A/D conversion process. The reference current to the op-amp can be reduced without sacrificing overall accuracy of the output of the analog-to-digital converter, even though reducing the current to the op-amp reduces the accuracy of the op-amp. This is possible because the op-amp only needs to operate at maximum accuracy during the first conversion cycle, and can operate at reduced levels of accuracy during later conversion cycles.

Abstract: A double ramp ADC within an image sensor. The double ramp ADC divides the analog-to-digital conversion process into two steps. During the first step of the conversion, the ADC runs through the potential digital values roughly, using coarse counter steps, and maintains a coarse digital output value. During the second step, the ADC runs through the individual digital values within the range of values associated with the coarse digital value. Thus, the second step runs through the fine digital values associated with the coarse digital value. The coarse and fine digital values are output as the converted digital value of the analog input voltage. The double ramp ADC should reduce the analog-to-digital conversion cycle time by up to 2(n/2−1) times that of the conventional analog-to-digital conversion cycle using ramp ADCs, where n is a number of bits of digital output (i.e., resolution) of the ADCs.

Abstract: A dual-slope analog-to-digital converter and a comparison circuit for the dual-slope analog-to-digital converter. The dual-slope analog-to-digital converter includes a buffer, an integrator coupled to the buffer and the comparison circuit. The comparison circuit includes a differential output comparator and a comparison unit. The differential output comparator is coupled to the integrator and produces a pair of differential signals to output. The comparison unit receives the differential signals and chooses a signal, whose voltage is from a first level to a second level, from the differential signals to produce an output signal.

Abstract: In the invention, an integrator integrates a current indicative of an input signal to generate at its output end a voltage (referred to as integral output voltage) by means of a condenser. At a point in time when the integral output voltage has reached a predetermined level, or at a point in time determined by timing of a predetermined period, the integral output voltage is reduced in absolute value by flowing into or out of the condenser a constant current supplied by a constant current source. The direction of the constant current depends on the polarity of the output of the integrator. A counter counting up or down clocks stops counting while the constant current is flowing. This permits use of a low-frequency A/D converter to convert the input signal at a reduced power and extend the dynamic range of the A/D converter.

Abstract: For the realization of a unipolar analog input range, in addition to the provision of an analog input sampling circuit having an input capacitor, a charge transfer circuit, an integrator having an integrating capacitor, a comparator, and a D-type flip-flop, there is further provided a reference voltage sampling circuit for selectively adding either of a subtraction and addition voltages which are different from each other to a sampled analog input voltage in response to a delayed comparator output. The reference voltage sampling circuit has a subtraction and addition capacitors differing in capacitance value from each other.

Abstract: An integration voltage obtained by continuously integrating an input voltage and a reference voltage is compared with a base voltage GND by a voltage comparator. The time that is required until a comparison result is inverted is counted by a counter And a count result is outputted as a digital signal OUT. In voltage comparators, the integration voltage is compared with a voltage that is higher than the base voltage GND by a predetermined voltage and with a voltage that is lower than the base voltage GND by a predetermined voltage, respectively. A difference between the inversion time of the comparison result of the voltage comparator and that of the voltage comparator is measured by a subtractor.

Abstract: A multislope, continuously integrating analog-to-digital converter includes a first switch coupled to a first reference voltage, a second switch coupled to a second reference voltage, a third switch coupled to an input voltage, and an integrator operably coupled to the first, second, and third switches. The analog-to-digital converter utilizes a primary discharge current of opposite polarity to a secondary discharge current. The analog-to-digital converter has a high resolution due to a small reference voltage, and a high dynamic range due to a large reference voltage. The analog-to-digital converter can operate in either a conversion mode or a calibration mode. During the calibration mode, a calibration factor is calculated for use during the conversion mode. When applied to the conversion mode, the calibration factor corrects for errors in the conversion process.

Abstract: An integration voltage obtained by continuously integrating an input voltage and a reference voltage is compared with a base voltage GND by a voltage comparator. The time that is required until a comparison result is inverted is counted by a counter and a count result is outputted as a digital signal OUT. In voltage comparators, the integration voltage is compared with a voltage that is higher than the base voltage GND by a predetermined voltage and with a voltage that is lower than the base voltage GND by a predetermined voltage, respectively. A difference between the inversion time of the comparison result of the voltage comparator and that of the voltage comparator is measured by a subtractor.

Abstract: An analog/digital converter including an amplifier (1) wired as an integrator, a comparator (2) electrically downstream from the integrator, a time counter (6) which continually counts the pulses of a pulse generator (5), a bistable element (4), and additional circuitry. The bistable element (4) drives the input network of the amplifier (1) with at least one switch (3) in such a way that in one of its two positions (“off” condition) a current Ix proportional to the analog measured value is integrated, and in the other position (“on” condition) a constant reference current Iref with opposite polarity to the current Ix is integrated in addition to current Ix.

Abstract: An analog-to-digital or digital-to-analog system contains a converter (706). The converter is supplied with a clock signal (CLK1) at a frequency fs derived from a crystal of a frequency fs/N. The frequency fs is derived from the fs/N crystal frequency by using an edge-triggered clock multiplier 705 which multiplies the crystal frequency by the factor N. The result is a low-cost clock solution that incorporates clock jitter around a localized frequency of fs/N. Sigma delta processing circuitry (702) is then used to place a null (e.g., low gain area) in the quantization noise at the same frequency where clock jitter noise is high in order to cancel the adverse cumulative effects of these two types of noise.

Abstract: A method and system for calibrating analog integrated circuits. Initially, a single calibration circuit is formed integral with a group of analog integrated circuits. A control signal and a calibration signal are generated from the calibration circuit. Next, the control signal and the calibration signal are selectively coupled to an input of a particular analog integrated circuit among the group of analog integrated circuits. The particular analog integrated circuit is then selected for calibration via the control signal.

Abstract: A new self calibration technique for pipe line A/D converters is presented. It consists of calibration by correcting the reference voltage to each stage by means of a tunable MOSFET attenuator. This simplifies the calibration circuit in each stage and shifts most of the calibration task to a hardware that is shared by all the stages.

Abstract: A method and apparatus for measurement signal compensation comprises providing an analog-to-digital converter that includes a dual slope integrator. A microprocessor controls the reference voltage applied to the integrator. An amplifier having a switchable gain, controls the amplification of the input signal to the integrator during the various phases of integration. An off-set compensation value is stored in a memory device for providing off-set compensation by charging a capacitor connected to the integrator. A full-scale rough adjust value is also stored on the memory device and is used as a specific reference to produce a reference voltage that is, in turn, used in the integrator during the negative slope phase. During the positive slope phase, the integration time is controlled by means of full-scale fine adjust values. The temperature dependent full-scale fine adjust values are produced from the preprogrammed values in memory by using interpolation techniques.

Abstract: According to the present invention, standard analog to digital converter circuitry may be utilized to measure an unknown analog value and to produce a digital value after conversion that automatically contains an offset value with respect to a given measurement range. The digital value produced according to the present invention is not representative of a raw measurement value but rather is representative of a value with respect to a given measurement range; thus, a digital value of 0 may indicate the minimum value of a given measurement range rather than a value of 0 Ohms, 0 volts, or 0 Amps. This may be expressed in equation form where the desired conversion value is represented by:k(X.sub.unknown -X.sub.offset)where k is a constant, X.sub.unknown is the unknown analog value being measured, and X.sub.offset is the offset value. X.sub.offset the offset value may or may not be equal to a reference value.

Abstract: A current-input, autoscaling, dual-slope A/D converter includes means for adjusting the integration period of the input current to effectively adjust a scale factor associated with the converter. An integrator circuit of the converter includes means for precharging an integration capacitor of the integrator circuit to an off-set voltage associated with an amplifier of the integrator circuit, so as to effectively eliminate integration error due to the off-set voltage. A PMOS switching transistor associated with precharging the integration capacitor is formed in an n-well biased to a voltage approximately equal in magnitude to a voltage held across the integration capacitor, so as to minimized leakage current from the capacitor through the PMOS switching transistor.

Abstract: A unified zero-reset phase is used in a dual-slope analog-to-digital converter (ADC) to: (1) derive a correction voltage to cancel any error due to offset and/or residue voltages in the components of the ADC in the subsequent integration phase and the de-integration phase; (2) reset the output of the integrator in the ADC to zero quickly when there is a overflow condition due to excessive analog input signals. The combined function is accomplished by negative feedback from the output of the comparator to the input of the buffer. The negative feedback resets the integrator output to zero quickly under overflow condition. The correction voltage is stored in the integrating capacitor and a coupling capacitor to the integrating amplifier.

Abstract: A motor starter includes separable contacts interconnected between an alternating current (AC) power source and an AC motor for switching an AC load current which flows from the power source and through the separable contacts; a dual-slope analog-to-digital (A/D) conversion circuit for sensing the load current and generating a current value; and a microcomputer with a coil drive circuit for selectively opening the separable contacts as a predetermined function of the current value. The dual-slope A/D conversion circuit includes current transformers for sensing the AC load current and for selectively providing a received current therefrom, a current reference for selectively providing a reference current, a multiplexer for multiplexing the currents, and a class B preamplifier for amplifying and rectifying the multiplexed AC current.