Abstract: An integrating circuit includes first and second amplifiers for use during a zero-integrate mode and a X10 mode, respectively. The first amplifier is a low gain amplifier to ensure stability, whereas the second amplifier is a high gain amplifier to improve accuracy. During the zero-integrate mode, switches couple an integrator input lead to the first amplifier output lead and decouple it from the second amplifier output lead. During the X10 mode, the switches decouple the integrator input lead from the first amplifier output lead and couple it to the second amplifier output lead.

Abstract: An analog-to-digital converter converts multiple analog signals to multiple digital signals during a single conversion period. The converter comprises a multiple input integrator stage which provides an output voltage that is selectively compared to a multiplicity of voltages. The comparison voltages include reference voltages and additional signal inputs. A plurality of UP counters measure the number of clock pulses generated by a clock generator and enable the calculation of the output function.

Abstract: An analog-to-digital converter (ADC) includes a capacitor array coupled to switches, an integrator stage connected to the switchable capacitors and a comparator stage connected to the output of the integrator stage. Means coupled to the comparator stage include a feedback loop to effectuate switching reference signals of opposite polarity for use during respective phases of operation of the ADC. The values of the capacitors can be programmed by the user of the ADC and switched to provide a desired total capacitance. For any fixed ratio of the input voltage to reference voltage, the duty cycle remains constant over a wide range of temperatures. Multiple stages afford large effective capacitor ratios with a small range of actual capacitance values and enable a reduction in silicon chip area for an ADC integrated circuit.

Abstract: An improved dual slope integrating analog-to-digital converter for use in a Digital Multi-Meter includes an input portion, an A/D core portion, and a digital portion. The A/D core portion includes an auto zero function capability for automatically compensating for any existing offset voltages in various measurement modes such as voltage, resistance, or current measurement modes. The improved A/D converter of the present invention operates at high speed and with high resolution.

Abstract: An improved integrating type A/D converter has a set of analog switches and a control logic unit for selectively connecting a pair of input terminals for an unknown analog input voltage signal with a pair of input leads across a buffer and integrator in order to apply, first in an integrate phase, the analog input signal in a polarity direction that causes the integrator to ramp up in the same direction regardless of the polarity of the analog input signal, and then in a deintegrate phase, reference voltages are applied across the input leads in a fixed direction opposite to the applied input voltage such that a zero crossing signal is output by the comparator. The ramping-up and ramping-down of the integrator in the same direction eliminates rollover error in the A/D reading of inputs of different polarities but of the same magnitude. The invention is particularly useful for monolithic A/D converters using BiMOS technology.

Abstract: The present invention can provide an integral A-D converter of high frequency and of high accuracy and capable of reducing the influence of the integrating capacitor caused by the electric charge absorption property thereof because it compensates the measured data by substracting the compensating data from the measured data, the compensating data being the repeatedly A-D converted data of the ground voltage during the standardized initiating time of the integrating capacitor.

Abstract: A high resolution and high speed analog to digital converter for use with a transducer in measuring parameters such as weight, which may stay the same or which may change in the system, the converter having an integrator which integrates for a fixed period the output voltage from the transducer, and subsequently deintegrates a known reference voltage, the deintegration times varying depending upon the magnitude of the transducer output voltage which has been integrated, a comparator comparing the deintegration times of successive conversions and shortening the integration times for the transducer output so as to obtain more conversions per time period to provide a high speed readout when the transducer output is changing, but lengthening the integration times to provide a high resolution readout when the comparison of deintegration times does not reveal any change in the transducer output.

Abstract: A digital and programmable measuring and control instrument comprising a digital-analog converter receiving an analog signal from a pressure transducer and converting it into a digital signal and dividing the same in about 4,000 parts separated in thousands, hundreds, tens and units. The so divided signal is delivered to programmable memories that evaluate the level thereof and refer it to stored values, in such a way as to produce a signal to be shown by display means indicating the precise and actual measurement. The output digitalized and linearized signals from the programmable memories are also delivered to additional programmable memories that evaluate them and in turn transmit programmed signals to a digital-analog converter that generates in response a signal to be used for commanding operative units. Additional control signals from the programmable memory are used as actuatable signals for control or alarm units.

Abstract: An integrating analog-to-digital converter (ADC) which calculates the coarse portion of its output by integrating an input analog signal over a predetermined number of time intervals during runup using a known technique to define the analog signal in terms of a slope count. The invention is particularly characterized in that an ADC is used in lieu of rundown of the integrator voltage to calculate the fine portion of the ADC output also in terms of slope count. This is accomplished by converting the residual analog signal remaining at the end of runup into a fractional slope count which can be added to the slope count determined during runup so that the resulting total slope count is directly proportional to the input voltage. To maintain linearity, calibration of the circuit is necessary and is accomplished by calculating a calibration constant which relates the ADC reading to slope count.

Abstract: An integrating analog-to-digital converter system in which alternating and different combinations of signals are integrated, and which are selected for such integration both periodically and through an integrating result reaching a reference value in the periods. A digit count is provided as a system output indicating the time duration of integration of a selected signal combination in each period.

Abstract: A process and arrangement for evaluating a measurable analog electronic quantity based on the principle of the timekeeping mechanism, in which the measurable analog quantity is digitalized by counting integration processes. To exploit the simplicity and precision of the timekeeping mechanism principle also far fast and precise digital data conversion units, a deviation coding phase (AV) is inserted between the timekeeping mechanism periods (T), in which post-adjustment of the timekeeping mechanism timing ratio is possible with rapid digital circuits even in the event of abrupt fluctuations of the quantity to be measured. The invention is generally applicable for highly precise and rapid digital data conversion of analog quantities, and is especially advantageous in high-precision measuring instruments with measuring sensors in bridge circuits, for example in weighing cells based on the DMS principle in electronic balances.

Abstract: An analog to digital converter system (10) is disclosed which comprises an SAR logic circuit (12) which controls capacitor array control switches (14) which themselves control a capacitor array (16). A top plate (18) of the capacitor array (18) is selectively coupled to a coarse comparator (24) and a fine comparator (26). The outputs of the coarse comparator (24) and the fine comparator (26) are input into an error correction circuit (28). In operation, the coarse comparator (24) is used to approximate a predetermined number of the most significant bits of the digital word to be output by the system (10) while the fine comparator (26) is used to approximate the remaining bits of the digital word. In this manner, the coarse comparator (24) alone is subjected to the high voltages which might cause errors as a results of the hysteresis effect in the threshold voltages of the MOSFETs used to construct the comparators.

Abstract: An analog-to-digital converter employs a capacitor circuit for integrating a sample of an input signal during a predetermined interval of time and, thereafter, the capacitor is discharged at a predetermined rate until the integration voltage is equal to that of a reference. The discharge time serves as a measure of the amplitude of the input signal. A measurement interval is established which is equal to an integral number of cycles of each of the possible values of frequency of the A.C. excitation. The signal integration interval has a duration less than or approximately equal to the shortest period of the A.C. excitation, this being the period of the highest frequency A.C. excitation. The signal integration is repeated periodically at each third half-cycle of the highest frequency excitation so that the total integration time experienced during positive half cycles is equal to that experienced during negative half cycles of any of the plurality of excitation frequencies.

Abstract: An analog-to-digital converter includes a constant current source that alternately charges and discharges the capacitor between predetermined levels. The difference between the rate of charging and the rate of discharging of the capacitor provide information permitting a digital representation of the input signal. The single current source operates without change during the charging and discharging of the capacitor and has temperature compensation that eliminates potential errors due to instabilities in the ambient temperature.

Abstract: The present invention provides an analog to digital converter, including an integrator for producing an output signal and having an input, a connection for an input signal to the integrator input, and a controller for periodically applying a reference signal to the integrator input for causing the integrator output signal to have a predetermined average value, for measuring the amount of time that the reference is applied to the integrator input, and for calculating a digital representation of the analog signal.

Abstract: A dual-slope A/D converter circuit has an oscillator (14) whose timing frequency is determined by the value of an oscillator resistor (70) and a oscillator capacitor (72). An integrator (66) integrates an input voltage at a rate determined by an integrating resistor (64) and an integrating capacitor (68). The oscillator resistor (70) and integrator resistor (64) are designed such that their ratio will remain constant despite variations in actual value due to manufacturing inaccuracies. The oscillator capacitor (72) and integrating capacitor (68) are similarly designed. Consequently, an optimum peak integration value can be obtained at full scale input despite variations in actual resistive and capacitive values.

Abstract: Apparatus for control of the range of input voltage values to be measured and for compensation of the changes in the supply voltage of an analog to digital dual slope converter circuit is described. The selection of a range for input voltage measurements in the analog to digital converter circuit permits the conversion to take place over a relatively long time period, thereby increasing the resolution of the resulting conversion. Changes in the supply voltage are combined with the input analog signal (during the capacitance charging period) and with the reference voltage (during the capacitance discharge cycle) providing compensation for the effects of time, temperature and the tolerance of the supply voltage.

Abstract: There is provided according to the invention a method and apparatus for eliminating or minimizing the error due to amplifier offset or drift error in an integrating dual slope analog-to-digital converter. The converter is provided with a switching and control arrangement whereby the integrating capacitor is charged for one-half of the predetermined charging time as a function of the sum of the levels of the unknown signal and the error signal. The integrating capacitor is charged for the remaining half of the predetermined time period as a function of the difference of the levels of the unknown signal and the error signal so that the capacitor reaches a level of charge which is a function of the level of the unknown signal substantially unaffected by the level of the error signal.

Abstract: An analogue to digital multi-slope converter has an integrator 10 to which an analogue input signal 30 is continuously applied. A reference voltage 36, 37 is superimposed onto the integrator input 30 in pulse form, being switched on and off according to a predetermined program controlled by a clock and modified by a comparator 11 such that reference voltage pulses occur in pairs of opposite polarity. The sequence of pulses is applied in such a manner that the final pulse of a sequence causes the integrator output to move towards a comparator 11 reference level, the reference voltage then being maintained until the reference level is reached after which a new cycle is started.

Abstract: An analog-to-digital converter is provided based on supplying various multiplexed inputs, including analog input signal samples, to a voltage-to-current converter charging and discharging an integrated capacitor. A comparator determines the status of this capacitor to a control counter to provide digital representations.

Abstract: A dual-slope A/D converter circuit has an oscillator (14) whose timing frequency is determined by the value of an oscillator resistor (70) and a oscillator capacitor (72). An integrator (66) integrates an input voltage at a rate determined by an integrating resistor (64) and an integrating capacitor (68). The oscillator resistor (70) and integrator resistor (64) are designed such that their ratio will remain constant despite variations in actual value due to manufacturing inaccuracies. The oscillator capacitor (72) and integrating capacitor (68) are similarly designed. Consequently, an optimum peak integration value can be obtained at full scale input despite variations in actual resistive and capacitive values.

Abstract: An integrator of a Sigma-Delta modulator includes an amplifier having an inverting input terminal and an output terminal. AN integrating capacitor is coupled between the input and output terminals. An input signal is coupled via a switched capacitor arrangement to the input terminal. The switched capacitor arrangement includes first and second transmission gates, operating at a first frequency, and a second capacitance that are coupled in series. In each period of the operation of the transmission gates, the first transmission gate is turned off before the second transmission gate for preventing a charge injected by the second transmission gate when the second transmission gate is turned off from being coupled to the input terminal of the amplifier.

Abstract: A clock-controlled pulse width modulator comprising an integrator for receiving a variable input voltage and producing an output having a triangular waveform, the integrator including a capacitor which is charged at a rate proportioal to the input voltage and discharged at a rate proportional to the difference between a reference voltage and the input voltage, the charging and discharging occurring during a time interval T.sub.o, a clock pulse source for generating a continuous series of clock pulses, a counter receiving the clock pulses and producing a binary control signal which changes state in response to the counting of a preselected number of clock pulses, the control signal having a period T.sub.

Abstract: An analog to digital converting device which can convert analog input signals individually into digital values of accurately corresponding magnitudes even when there is some difference in the input signals. The device comprises an integrating circuit which includes an operational amplifier for receiving an analog signal, an integrating capacitor connected between an input terminal and an output terminal of the operational amplifier, and a reset switch connected in parallel to the integrating capacitor. The integrating circuit is controlled to first perform an integrating operation and then an inverse integrating operation. A comparator is connected to an output terminal of the integrating circuit. A diode or transistor is connected in parallel to the integrating capacitor for limiting an amount of charge to be accumulated in the integrating capacitor by an inverse integrating operation to below a predetermined value.

Abstract: There is provided according to the invention a method and apparatus for eliminating or minimizing the error due to amplifier offset or drift error in an integrating dual slope analog-to-digital converter. The converter is provided with a switching and control arrangement whereby the integrating capacitor is charged for one-half of the predetermined charging time as a function of the sum of the levels of the unknown signal and the error signal. The integrating capacitor is charged for the remaining half of the predetermined time period as a function of the difference of the levels of the unknown signal and the error signal so that the capacitor reaches a level of charge which is a function of the level of the unknown signal substantially unaffected by the level of the error signal.