Abstract: A solid-state image pickup device includes a pixel array including pixels arranged in a matrix, a pixel signal readout unit, and a timing control unit for controlling processing of the pixel signal readout unit by using a timing signal. The pixel signal readout unit includes: a plurality of comparators for comparing a readout signal potential with a reference voltage to generate a determination signal and outputting the determination signal, and a plurality of counters. Each counter counts a comparison time of each corresponding one of the comparators. The timing control unit (a) divides a predetermined processing period into at least a first-time readout period, a first comparison period, a second-time readout period, and a second-time comparison period, (b) classifies the periods into two periods, and (c) generates a timing signal of processing of each divided period by counting for each divided period in the counter.

Abstract: Circuits and methods that improve the performance of voltage reference driver circuits and associated analog to digital converters are provided. A voltage reference driver circuit that maintains a substantially constant output voltage when a load current is modulated by an input signal is provided. The voltage reference driver circuit synchronously decouples a voltage regulation circuit from the load circuit when modulating events such as pulses caused by the load circuit during a switching interval are generated, preventing disturbance of the regulation circuitry and keeping its output voltage substantially constant.

Abstract: An analogue/digital converter arrangement and a method. A differential input voltage is converted by means of a differentially implemented capacitative voltage divider that comprises two programmable capacitor banks (3, 4), and with the aid of the comparator (6) into a digital output signal.

Abstract: An angular velocity sensor has a stable output characteristic using a sigma-delta type analog-to-digital converter. The sigma-delta type analog-to-digital converter includes an integrator unit for integrating electric charges output from an input switching device and a digital-to-analog converter unit, and holding at least two integrated values, a comparator unit for comparing at least the two integrated values output from the integrator unit with a predetermined value. The sigma-delta-type analog-to-digital converter also includes an arithmetic operation unit for operating an output signal of the comparator unit, the arithmetic operation unit being provided with a differential operation unit for computing a difference between at least two comparison signals output from comparator unit.

Abstract: A successive approximation analog-to-digital converter (ADC) includes a binary-weighted capacitor array, quantizer, and control block. One end of each capacitor is connected to the input of the quantizer, and a second end of each capacitor is controlled by the control block through a driver. A voltage is sampled, quantized, and stored as the most significant bit of the ADC's output. Depending on the result of the quantization, the control block toggles the driver of one of the capacitors corresponding to the most significant bit. The voltage at the common node is sampled again to obtain a second bit of the ADC's output. The operations are repeated as needed to obtain and store additional bits of the ADC's output. Similar configuration and process are described for a differential ADC. The operation is asynchronous, allowing extra time for metastable states only when such states occur.

Abstract: Disclosed is a flash analog to digital converter (ADC) capable of reducing area requirements and using successive approximation. The ADC includes a reference voltage generating unit receiving an external voltage and outputting M reference voltages. A reference voltage selecting unit outputs N reference voltages less than the number of the voltages outputted by the reference voltage generating unit according to a supplied control signal. A digital signal output unit compares the N reference voltages outputted by the reference voltage selecting unit with an external analog input signal and outputs the comparison result as an N-bit digital signal.

Abstract: A conversion operation B is performed with respect to a sample value R in an A/D conversion stage 101 to generate a conversion result D3, and a sampling operation A is performed with respect to this conversion result D3 in an A/D conversion stage 103. The conversion operation B is performed with respect to a sample value in an A/D conversion stage 105 to generate a conversion result D4, and the sampling operation A is performed with respect to the conversion result D4 in an A/D conversion stage 107. The conversion operation B is performed with respect to a sample value in an A/D conversion stage 107 to generate a conversion result D5, and the sampling operation A is performed with respect to this conversion result D5 in an A/D conversion stage 101. The conversion operation B is performed with respect to a sample value in the A/D conversion stage 103 to generate a conversion result D6, and the sampling operation A is performed with respect to the conversion result D6 in the A/D conversion stage 105.

Abstract: Several methods and a system of noise limitation of a signal dependent multibit digital to analog signal conversion are disclosed. An exemplary embodiment provides a method that includes receiving an output of a multibit analog to digital circuit of a continuous time sigma delta converter. The method further includes limiting a noise generation by adaptively selecting a digital to analog converter element out of a plurality of digital to analog converter elements in accordance with an input signal magnitude. In addition, the method includes implementing a selected digital to analog converter element to generate an analog signal.

Abstract: An A/D converting apparatus includes a first A/D converter to sample an analog input signal having a D/A converter to generate a comparative signal for successive comparison with the analog input signal, a signal generator generate a differential signal between the analog input signal and the comparative signal, and a comparator to compare the comparative signal with a standard value to generate a first digital signal exhibiting high-order bit; an amplifier to amplify the differential signal to generate a residue signal; and a second A/D converter to sample the residue signal to generate a second digital signal exhibiting low-order bit.

Abstract: Disclosed is a sample and hold circuit including a differential circuit, an amplifier stage and a sampling voltage supply circuit. The differential circuit includes first and second capacitance elements, electric charge of which is distributed by a first switch, a first MOS transistor having a gate connected via a second switch to one end of the first capacitance element and also connected via a third switch to an output terminal, and having a source connected to a first current source, a second MOS transistor having a gate connected to one end of the second capacitance element and having a source connected to a second current source and also connected via a forth switch to the source of the first MOS transistor, and a load circuit connected between the drains of the first and second MOS transistors and a terminal of a second power supply. The amplifier stage receives an output of the differential circuit and has an output connected to the output terminal.

Abstract: An apparatus is provided. The apparatus comprises a sample switch, a sampling capacitor, an amplifier, feedback branches, a second hold switch, an N-bit converter pair, a third hold switch, and an M-bit converter pair. The sample receives an input signal and is actuated by a sample signal. The sampling capacitor is coupled to the sample switch. The amplifier has a first input terminal that is coupled to the sampling capacitor. The feedback branches are coupled between the output terminal of the amplifier and the first input terminal of the amplifier, with each feedback branch including a feedback capacitor, and a first hold switch that is coupled to the feedback capacitor. The second hold switch is coupled to the sampling switch. The N-bit converter pair is coupled to the sampling switch and to the second hold switch. The third hold switch is coupled to at least one of the feedback branches, and the M-bit converter pair is coupled to the output terminal of the amplifier and to the third hold switch.

Abstract: There is disclosed a sample-and-hold circuit. An operational amplifier includes an inverting input terminal, a non-inverting input terminal, an inverting output terminal, and a non-inverting output terminal. First and second groups of capacitors are operated in first to third modes periodically. Positive and negative input signals are input to charge an electric charge in the first mode, electric charge are held while positive and negative output signals are output from the operational amplifier by connecting between the inverting input terminal and the non-inverting output terminal and by connecting between the non-inverting input terminal and the inverting output terminal in the second mode, and electric charge are discharged in the third mode. Second group of capacitors shifts to the third mode when first group of capacitors is in the first or second mode, and shift to the first or second mode when first group of capacitors is in the third mode.

Abstract: A circuit for converting a charge signal into a binary format of output bits comprises: an integration circuit including an operational transconductance amplifier having an inverting input terminal and an output terminal, an integrating capacitor connected between the inverting input terminal and the output terminal, the integrating capacitor for storing a charge input selectively provided by a sensor diode; and a folding circuit having a fold capacitor, the fold capacitor switchably coupled either to a fold voltage source via a fold buffer for charging the fold capacitor to a predetermined fold charge value, or to the integrating capacitor for selectively removing at least a portion of the stored charge input.

Abstract: The present invention discloses a 1-bit cell circuit used in a pipelined analog to digital converter. The 1-bit cell circuit comprises a reference buffer for providing a reference voltage; a sample and charge transfer circuit for receiving an input signal to generate an output signal; and a dump circuit for dumping said reference voltage; wherein said reference buffer selectively connects to one of said sample and charge transfer circuit and said dump circuit according to said input signal.

Abstract: Methods and systems to amplify and convert a single-ended analog signal to a differential signal and to convert the differential signal to a digital value, including to time-multiplex a plurality of windowed single-ended analog error signals, amplify a difference between the time-multiplexed analog signals, sample a corresponding amplified difference signal and an inverted amplified difference signal, amplify and center the samples about a common mode, and convert a corresponding amplified differential signal to digital values in a pipeline fashion. Bias adjustable features may be implemented to control a bandwidth, and clock rates may be adjustable to correspond to the bandwidth.

Abstract: A conversion circuit for converting a differential input signal into an output signal includes an amplifier that has an input terminal and an output terminal; a first capacitor in which, in a first period, a difference voltage of the differential input signal is applied across first and second terminals, and in a second period the first terminal is coupled to the output terminal of the amplifier and the second terminal is coupled to the input terminal of the amplifier; and a second capacitor in which, in the second period, a reference voltage in accordance with the differential input signal is applied to a first terminal, and the second terminal of the first capacitor is coupled to a second terminal of the second capacitor.

Abstract: A comparator includes a plurality of switches, a capacitor, an amplifier, and a latch. The switches provide an input signal during a first period and provide a reference signal during a second period. A first switch among the switches is composed of a first transistor. The capacitor receives the input signal during the first period and receives the reference signal during the second period. The amplifier is coupled to the capacitor for receiving a difference voltage between the input signal and the reference signal and amplifies the difference voltage during the second period to generate an amplified result. The determining circuit provides a digital signal according to the amplified result.

Abstract: A system for randomizing aperture delay in a time interleaved ADC system that includes a plurality of selection switch stages corresponding to each of the ADCs in the system and a second selection switch stage coupled to a voltage source. A plurality of conductors extend between the second selection switch stage and each of the selection switch stages, in excess of the number of ADCs in the system. For each of N ADCs in the system, the selection switch stages and the second selection switch stage support at least N+1 selectable conductive paths extending from each of the sampling capacitors of the ADCs to the voltage source. Random selection of the N+1 paths can randomize aperture delay.

Abstract: Measurement amplification methods and devices for detecting a monopolar input signal (UE) by integrating A/D conversion. Before being digitized, the input signal (UE) is inverted according to the so-called Chopper principle and converted into a bipolar intermediate signal (UZ). A reference voltage (Uref) used in A/D conversion undergoes polarity changes synchronized with the polarity changes of the intermediate signal (UZ). Offset and drift are eliminated by totaling an even number of individual measurements.

Abstract: A chopping transconductor includes an transconductor input stage coupled with input signals of the chopping transconductor; a chopping switch coupled with an output of the transconductor input stage, the chopping switch having a switch output; and a cascode transistor, wherein the switch output is coupled to an output of the chopping transconductor through the cascode transistor. The chopping transconductor may be used in an analog-to-digital converter to isolate chopping switches from junctions with quantization noise.

Abstract: The A/D converting circuit 20 is provided with a differential amplifying portion 21, a first variable capacitance portion 22A, a second variable capacitance portion 22B, a comparing portion 23, a connection controlling portion 24, a first feedback portion 25A and a second feedback portion 25B. Voltage values output as a differential signal from the first output terminal and the second output terminal of the differential amplifying portion 21 are converted to 6-bit digital values by a successive approximation type A/D converting circuit (made up of a first variable capacitance portion 22A, a second variable capacitance portion 22B, a comparing portion 23 and a connection controlling portion 24) and output.

Abstract: An analog-to-digital converter (ADC) and a battery operated electronic device comprising the ADC. The ADC comprising an input switch; an array of binary-weighted capacitors, the array of capacitors receiving the input voltage signal via the input switch in an on state of the input switch; a plurality of switches, each switch connected in series with a respective one of the capacitors at an opposite side compared to the input switch, wherein a VDD signal is applied to each switch in one switching state and ground in another switching state; a comparator having as one input a voltage from the input switch side of the array of capacitors and as another input a voltage of VDD/2; and a switch control unit coupled to an output of the comparator for controlling the switches based on the output from the comparator.

Abstract: A switched capacitor circuit includes a capacitor that performs sampling, a first switch that is provided between the capacitor and an input terminal, and a second switch that is provided between the capacitor and an output terminal. The first switch and the second switch receive an input of a clock signal and turn on and off. The capacitor is a variable capacitance element in which the value of the capacitance changes in synchronization with the clock signal.

Abstract: In an A/D converter, three capacitors are connected to a comparator. The A/D converter also includes three switching circuits that each input a first reference voltage, a second reference voltage, and a third reference voltage in the three capacitors. A control circuit selects at least two of the three switching circuits during a charging period of stray capacitance of each of the capacitors. The control circuit turns on one of the switching devices in the selected switching circuits simultaneously, and during a comparing period by the comparator, selects one of the three capacitors for each comparison, and selects another capacitor in the next comparison.

Abstract: A pipeline-type A/D converter includes: N number of stages cascade-connected; and a digital correction circuit that receives digital signals outputted from the N number of stages and outputs a final digital signal. In the converter, an Mth stage in the N number of stages includes: a sub A/D converter A/D-converting an input analog signal; a sub D/A converter D/A converting a digital signal outputted from the sub A/D converter; a differential amplifier circuit that includes a sample hold circuit and an operational amplifier, performs an sampling operation and a holding operation to obtain a difference between the input analog signal and an output signal of the sub D/A converter, and amplifies the difference; and a compensation circuit compensating a gain error of the operational amplifier in an operation of the differential amplifier circuit, the gain error being caused by parasitic capacitance between an input terminal and an output terminal of the operational amplifier, and 1?M<N.

Abstract: A device comprises a first circuit that generates a first phase component and a second phase component. A pipelined analog to digital converter comprises N stages, wherein N is an integer greater than one. At least one of the N stages includes a sample and integrate circuit that selectively samples the first phase component and integrates a sampled second phase component to generate an integrated second phase component during one portion of a first clock phase of the sample and integrate circuit, and that selectively integrates the sampled first phase component to generate an integrated first phase component and samples the second phase component to generate the sampled second phase component during another portion of the first clock phase of the sample and integrate circuit.

Abstract: A successive approximation analog-to-digital converter includes a capacitor array having a plurality of switch capacitors therein with varying weights, each having a common plate connected to a common node and a switched plate. A SAR controller samples an input voltage on said capacitor array in a sampling phase and redistributes the charge stored therein in a conversion phase by selectively increasing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm. Circuitry controls the sampling of the input voltage by the capacitor array and is responsive to at least one applied bias current. The at least one applied bias current operates at a first level responsive to a first mode of operation of the SAR ADC and operates at a second level responsive to a second mode of operation of the SAR ADC.

Abstract: An apparatus for converting MEMS inductive capacitance to digital is provided, for converting the induced analog voltage of MEMS element into digital signal. The apparatus includes an ADC, a reference voltage circuit and a controller. With the integral circuit and the comparator of the ADC and the reference voltages generated by the reference voltage circuit, the apparatus of the present invention uses the switch signals generated by the controller to generate digital signals. The present invention can also be integrated with MEMS element into a single chip to achieve single-chip MEMS.

Abstract: Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.

Abstract: In each of a plurality of stages, an input analog signal is quantized, so that a digital signal corresponding to each part of bits is generated. ADA conversion portion generates an analog reference signal based on the digital signal, and a remainder operation portion performs addition/subtraction and amplification by a predetermined factor with respect to the input analog signal. Then, the signal thus obtained is supplied to a subsequent stage. The DA conversion portion in the first stage where A/D conversion of a plurality of bits is performed includes primary voltage supply portions capable of outputting a reference voltage at one of a plurality of levels, and an auxiliary voltage supply portion capable of outputting a reference voltage at an auxiliary level different from the above-described level. The respective voltage supply portions selectively output the reference voltages based on a digital signal generated by an AD conversion portion.

Abstract: A hybrid Analog-to-Digital Converter (ADC) has a binary-weighted capacitor array and a sub-voltage capacitor array that are coupled together by a coupling capacitor. The sub-voltage capacitor array uses a minimum capacitor size that matches the minimum capacitor size of the binary-weighted capacitor array. The coupling capacitor is double the minimum size and reduces a voltage effect on a charge sharing line by half. Second coupling capacitors in the sub-voltage capacitor array each reduce the voltage effect by half, so that first, second, and third sub-voltage capacitors in the sub-voltage capacitor array produce ½, ¼, and ? voltage swings using the minimum size capacitance. Only MSB capacitors in the binary-weighted capacitor array sample the analog input voltage. During conversion, MSB's from a Successive-Approximation-Register (SAR) are applied to binary-weighted capacitors while LSB's are applied to sub-voltage capacitors.

Abstract: An A/D conversion circuit includes a continuous-time filter that performs a filtering process on an input signal, an SCF that is provided in a subsequent stage of the continuous-time filter and performs a filtering process utilizing the continuous-time filter as a prefilter, a cut-off frequency of the SCF being variably set corresponding to a frequency band of the input signal, an A/D converter that is provided in a subsequent stage of the SCF and performs an A/D conversion operation utilizing the continuous-time filter and the SCF as prefilters, and a digital filter that is provided in a subsequent stage of the A/D converter and performs a digital filtering process utilizing the continuous-time filter and the SCF as prefilters, a cut-off frequency of the digital filter being variably set corresponding to the frequency band of the input signal.

Abstract: A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

Abstract: A direct capacitance-to-digital converter is provided, including a plurality of switches, an ADC, a reference voltage circuit and a trigger unit. By using trigger unit to control a plurality of switches, and combining the reference voltages outputted by the reference voltage circuit, the converter can directly sense the external to-be-measured capacitor and related stray capacitor, and directly convert the capacitance of the to-be-measured capacitor into accurate digital signal. The present invention can be integrated with other sensors into a single chip to form an integrated direct capacitance-to-digital converter.

Abstract: An analog to digital converter (ADC) containing a sub-ADC to resolve at least some of the bits using successive approximation principle (SAP), while providing various improvements. According to one aspect, another sub-ADC is used to resolve some of the bits in parallel. According to another aspect, the sub-ADC using SAP is implemented using a charge redistribution principle, while another sub-ADC does not rely on charge conservation. According to yet another aspect of the present invention, a same component operates as a comparator when the sub-ADC using SAP resolves the corresponding bits, and operates as an amplifier when the sub-ADC generates a residue signal.

Abstract: The analog-to-digital converter provided herein includes a capacitor bank comprising a plurality of binary-weighted capacitors, an operational amplifier having an inverting input node, a noninverting input node coupled to analog ground, and an output node, a reset switch, and an input switch. The reset switch is located between the capacitor bank and the operational amplifier, and it selectively couples the capacitor bank to the inverting input node. The input switch has its common terminal coupled to the capacitor bank, and the input switch selectively couples the capacitor bank to either an analog input voltage, a floating terminal, or analog ground. The capacitor bank includes N binary-weighted capacitors and one balancing capacitor that has a unit capacitance. During operation, the analog-to-digital converter generates an N-bit digital output and one polarity bit from the analog input voltage.

Abstract: A digital demodulator includes a resonator having a resonance frequency same as a carrier frequency to store a charge corresponding to a digital signal modulated by phase shift keying, a capacitor to store the charge of the resonator, an amplifier including an input node and an output node between which the capacitor is connected to convert a stored charge of the capacitor into a voltage signal, and a controller configured to accumulate in the resonator the charge induced by the frequency signal modulated by phase shift keying in a first control mode and configured to transfer the charge of the resonator to the capacitor in a second control mode, to output the voltage signal corresponding to the stored charge of the capacitor from the output node of the amplifier.

Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal or a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal.

Abstract: A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply.

Abstract: A device and method for correlation-based background calibration of pipelined converters with a reduced power penalty. A pipelined analog-to-digital converter (ADC) utilizes a random or pseudorandom signal to reduce the quantization error of subconverting stages. Stages within the ADC comprise an injection circuit having a plurality of capacitive branches in parallel. Less than all of the branches can function during a given clock cycle of the ADC. This allows a subconverting stage within the ADC to be accurately trimmed before operation using a large amplitude signal. At the same time, the capability to inject smaller amplitude random or pseudorandom signals into the subconverting stage during operation is maintained, saving valuable dynamic range and power. The various capacitive branches are cycled through either randomly or in sequence such that the quantizer manifests the same average gain error over time for which the quantizer was initially trimmed.

Abstract: With high speed analog to digital converters (ADCs), components within the ADC can enter a saturation region when an input exceeded the input range of the ADC, which can cause errors. Here, a sample of an input signal to an ADC is compared with the upper and lower full-scale levels of the ADC. If input overload is detected, inputs to amplifiers in an input stage of the ADC are forced to zero for the duration of the input overload, and are thus prevented from going into saturation. Input overload conditions are signaled directly to an output digital block of the ADC, which provides output digital codes equivalent to either the upper or the lower full scale level depending on whether the input overload is signaled as exceeding the upper level or the lower level. Input overload recovery time of the ADC may thus be minimized.

Abstract: A digital-to-analog converter is disclosed for converting a digital signal into its analog equivalent. The digital-to-analog converter includes a two switches capable of coupling circuit nodes to ground, a scaling capacitor having a capacitance value that equals a unit capacitance value, a first array of capacitors coupled to the first circuit node and a first switching array which couples the first array of capacitors to either ground or a reference voltage depending on the digital values of the least significant bits of the digital word being converted, a second array of capacitors coupled to the second circuit node and a second switching array which couples the second array of capacitors to either ground or the reference voltage depending on the digital values of the most significant bits of the digital word being converted.

Abstract: A successive approximation type A/D converter includes a main capacitance array connected with a common connection node; a correction capacitance array; a voltage comparator configured to detect a voltage of the common connection node; and a successive approximation register in which a value is set based on an output of the voltage comparator. A first control circuit changes voltages applied to capacitance elements of the main capacitance array and the correction capacitance array based on a value set in the successive approximation register. A second control circuit responds to a control signal to connect the main capacitance array to an input voltage signal or a first predetermined voltage, and the correction capacitance array to the common connection node or a second predetermined voltage.

Abstract: A direct capacitance-to-digital converter is provided, including a plurality of switches, an ADC, a reference voltage circuit and a trigger unit. By using trigger unit to control a plurality of switches, and combining the reference voltages outputted by the reference voltage circuit, the converter can directly sense the external to-be-measured capacitor and related stray capacitor, and directly convert the capacitance of the to-be-measured capacitor into accurate digital signal. The present invention can be integrated with other sensors into a single chip to form an integrated direct capacitance-to-digital converter.

Abstract: The present invention is intended to attain simplified circuit configuration and low current consumption in a discrete time amplifier circuit and an AD converter, to improve the convergence from the transient response state to the steady state of the amplifier circuit and to reduce noise and distortion owing to the variation in the output common-mode voltage. The discrete time amplifier circuit and the AD converter are provided with a switched-capacitor common-mode feedback (CMFB) circuit capable of detecting and feeding back the output common-mode voltage at every sampling timing in the case that the circuit operates at double sampling timing (every ½ cycle).

Abstract: An analog to digital converter is provided in which the outputs of first and second digital to analog converters DAC1 and DAC2 are combined in a combining circuit so as to form a plurality of decision thresholds. This enables two or more bits to be determined in a single trial.

Abstract: A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.

Abstract: A method for analog-to-digital conversion is provided using successive approximation and a plurality of capacitors including a first set of capacitors and a second set of capacitors, a first side of each of the plurality of capacitors being coupled to a common node. The method includes sampling an input voltage on the first set of capacitors, after the step of sampling leaving a side of at least one capacitor of the first set of capacitors floating, coupling a capacitor of the first set of capacitors, which is not floating, with a capacitor of the second set of capacitors so as to redistribute the charge on the coupled capacitors, comparing the voltage on the common node with a comparator reference voltage level to receive a comparison result to be used for a bit decision, and switching the floating side of the floating capacitor of the first set of capacitors to either a first reference voltage or a second reference voltage in accordance with the bit decision.

Abstract: The A/D converting circuit 20 is provided with a differential amplifying portion 21, a first variable capacitance portion 22A, a second variable capacitance portion 22B, a comparing portion 23, a connection controlling portion 24, a first feedback portion 25A and a second feedback portion 25B. Voltage values output as a differential signal from the first output terminal and the second output terminal of the differential amplifying portion 21 are converted to 6-bit digital values by a successive approximation type A/D converting circuit (made up of a first variable capacitance portion 22A, a second variable capacitance portion 22B, a comparing portion 23 and a connection controlling portion 24) and output.

Abstract: Embodiments include integrator systems, switched-capacitor circuits, and methods of their operation. An integrator system comprises a differential amplifier and first and second sampling modules. The first sampling module includes a first capacitor and a first set of switches. The first set of switches changes a connection status between the first capacitor and first and second amplifier input terminals when a change in a polarity of a differential input signal does not occur between consecutive switching cycles, and refrains from changing the connection status when the change in the polarity does occur. The second sampling module includes a second capacitor and a second set of switches. The second set of switches changes a connection status between the second capacitor and the first and second amplifier input terminals when the change in the polarity does occur, and refrains from changing the connection status when the change in the polarity does not occur.