Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased.

Abstract: An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage.

Abstract: A switched-capacitor circuit which comprises a first sampling capacitor, a second sampling capacitor, an op-amp, a third capacitor, and a fourth capacitor is provided. The first sampling capacitor is disposed to sample an input signal in a sampling phase. The second sampling capacitor is disposed to sample the input signal in the sampling phase. Wherein, in a first amplify phase, the third capacitor stores an offset voltage of the op-amp, the fourth capacitor stores the electric charges which are flowed from the first sampling capacitor and the second sampling capacitor, and in a second amplify phase, the fourth capacitor gives the stored electric charges back to the first sampling capacitor and the second sampling capacitor.

Abstract: A switched-capacitor circuit which comprises a first sampling capacitor, a second sampling capacitor, an op-amp, a third capacitor, and a fourth capacitor is provided. The first sampling capacitor is disposed to sample an input signal in a sampling phase. The second sampling capacitor is disposed to sample the input signal in the sampling phase. Wherein, in a first amplify phase, the third capacitor stores an offset voltage of the op-amp, the fourth capacitor stores the electric charges which are flowed from the first sampling capacitor and the second sampling capacitor, and in a second amplify phase, the fourth capacitor gives the stored electric charges back to the first sampling capacitor and the second sampling capacitor.

Abstract: A switched capacitor circuit, which may be an SAR ADC, includes a plurality of bit switching circuits (33) each including a high-voltage sampling switch circuit (18) having a first terminal (28) coupled to a first terminal of a corresponding capacitor (22) and a second terminal coupled to receive an analog input signal (VSIG). A third terminal of the sampling switch circuit is coupled to an intermediate conductor (19). Each switching circuit (33) also includes a low-voltage conversion switch circuit (30) coupled to the intermediate conductor (19) and a combinational logic circuit (12) applying low-voltage signals to the conversion switch circuit and a level-shifting circuit (16) that generates corresponding high-voltage signals (HV_SIG_DRV) which control coupling of the first terminal (28) to the analog input signal and the intermediate conductor.

Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.

Abstract: A successive approximation A/D converter, includes a reference voltage generation circuit, a sample/hold circuit, a D/A converter circuit, a comparator, and a control circuit. A potential difference between the comparison target voltage generated by the D/A converter circuit and the internal analog voltage is applied to one input terminal of the comparator through a first signal line, and the reference voltage generation circuit is connected to the other input terminal of the comparator through a second signal line and a switch. Capacitive elements are disposed between the high potential power supply and the second signal line, and between the second signal line and the low potential power supply, respectively. The control circuit turns ON the switch to charge the first and second capacitive elements during a period when the sample/hold circuit samples and holds the internal analog voltage and turns OFF the switch in response to end of the period.

Abstract: A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages.

Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

Abstract: A device may include a programmable gain amplifier and an analog-digital converter with pipeline architecture having several stages. The first stage of the analog-digital converter may incorporate the programmable gain amplifier and an analog-digital conversion circuit with a programmable threshold.

Abstract: An analogue to digital converter uses charge sampling in combination with a successive approximation conversion technique in order to combine anti-alias filtering and quadrature downconversion functions into the data converter. The conversion method is an energy-efficient realization for wide-band radio systems with moderate resolution specifications such as 4G or ultra-wideband radio (UWB). The converter uses two capacitor matrices, one to perform charge sampling, and one to be used simultaneously in the successive approximation technique, so that full use of an input signal is made and efficiency is maximized.

Abstract: Successive approximation register (SAR) analog-to-digital converters (ADCs) generally use one or more comparators to convert an analog signal to a digital signal. These comparators, however, can consume a great deal of power, so it is desirable to have a comparator configuration that consumes less power. Here, a multi-bandwidth comparator is provided, which can be switched between different coarse resolution and fine resolution. By using this single multi-bandwidth comparator, lower power consumption with a small amount of area can be achieved.

Abstract: An analog to digital converter that comprises a successive approximation register (SAR) having an n bit binary output, a first capacitor array connected to receive some of the bits of the binary output, a second capacitor array connected to receive the remaining bits of the binary output, and a comparator including an output connected to the SAR. The first and second capacitor arrays each have an analog output indicative of the charge stored by capacitors of that array. The comparator includes a pair of inputs, one of which is connected to the analog output of the first capacitor array and the other of which is connected to the analog output of the second capacitor array.

Abstract: For high voltage applications, multi-channel successive approximation register (SAR) analog-to-digital converters (ADCs) are often plagued with numerous problems that are generally associated with parasitics (which are present in high voltage components). Here, a different architecture is provided where the sampling capacitors are separated from conversion capacitors so as to have low voltage components in the conversion path. Additionally, to improve the acquisition time and reduced total harmonic distortion (THD) multiple channels can use the same sampling capacitors.

Abstract: An A/D converter and a semiconductor device simple in configuration are provided which can keep a constant noise shaping characteristic without depending on manufacturing variations or a temperature change. A semiconductor device includes a delta-sigma modulator, an input changeover switch, and a control logic circuit. The delta-sigma modulator can change a time constant of an internal circuit according to a control signal. The input changeover switch selectively inputs any one of an input amplitude voltage and a reference voltage to the delta-sigma modulator. A control logic circuit is coupled to an output of the delta-sigma modulator, and generates the control signal.

Abstract: A switched-capacitor input circuit which receives an analog input signal, and samples and holds the analog input signal, comprising a differential amplifier, a first capacitor, one terminal of the first capacitor being connected to a non-inverting input terminal of the differential amplifier, a second capacitor, one terminal of the second capacitor being connected to an inverting input terminal of the differential amplifier, a first switch configured to connect the other terminal of the first capacitor to one of a first reference voltage and a second reference voltage, a second switch configured to connect the other terminal of the second capacitor to one of the first reference voltage and the second reference voltage, and a third switch configured to connect the other terminal of the first capacitor to the other terminal of the second capacitor.

Abstract: Some embodiments include apparatus and methods having an amplifier, a capacitor network coupled to the amplifier, and switching circuitry coupled to the amplifier and the capacitor network. The switching circuit is configured to successively apply a selected reference voltage selected from among a first reference voltage, a second reference voltage, and a third reference voltage to the capacitor network in response to a digital input code to generate an output voltage. Additional embodiments are disclosed.

Abstract: A capacitor array circuit receives a plurality of input signals, generate a single output signal by combining the plurality of input signals, and output the single output signal. A comparator receives the output signal of the capacitor array circuit. A current source, which is disposed between a predetermined fixed voltage source and an output terminal of the switched-capacitor circuit, supplies the current to the output terminal until the output signal of the comparator changes. A plurality of input capacitors in the capacitor array circuit receives a plurality of input signals in parallel with each other. At least one additional regulating capacitor in the capacitor array circuit store the charge to compensate for an offset component caused by the delay in the comparator. The respective output terminals of the plurality of input capacitors and the at least one additional regulating capacitor are combined into one.

Abstract: A Sigma-Delta modulator with a shared operational amplifier (op-amp) includes an integrated circuit, having two integrators sharing the op-amp, capable of integrating two input signals of the two integrators; a plurality of quantizers, coupled to the integrating circuit, for comparing outputting signals of the integrators with a predetermined signal and then generating digital outputting signals; a plurality of DACs, respectively coupled to the quantizers, for converting the digital outputting signals to analog feedback signals to the integrators; and a clock generator, for providing clock signals to the integrating circuit and the quantizers. Accordingly, layout area and power consumption of the modulator are reduced due to the shared op-amp.

Abstract: A switched capacitor circuit, which is operable in two or more kinds of operation modes including a first and second operation modes, includes an amplifier and two or more internal capacitors with switches for controlling connection/disconnection of the capacitor. In the first operation mode that precedes the second operation mode, the switched capacitor circuit generates the first analog output voltage by using the first internal capacitor connected between an input terminal and output terminal of the amplifier by using its switches, the other internal capacitances connected between an input terminal of the amplifier and each analog input voltage supply by using its switches. In the second operation mode, the switched capacitor circuit generates the second analog output voltage with larger feedback factor of the amplifier than it in the first operation mode, by removing some of the internal capacitors, except the first internal capacitor, from the first operation mode.

Abstract: In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion (7, 8) based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (9). A test can be performed by supplying a test signal in place of the input analog signal. A control portion (14a) performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal.

Abstract: Provided is an analog digital converter (ADC). The ADC includes: a capacitor array generating a level voltage; a comparator outputting a compare signal by comparing the level voltage; and a logic circuit determining digital bits of an analog signal based on the compare signal, wherein the logic circuit determines at least one digital bit among digital bits of the analog signal while a sampling operation of the analog signal is performed in the capacitor array.

Abstract: An offset canceling circuit stores charge corresponding to a voltage difference between a reset voltage received from a unit pixel and a reference voltage, thereby canceling an offset of the unit pixel.

Abstract: An analog-digital converter includes converter units and a control unit. The converter units each including a comparator for performing a comparison using an input voltage, one or more capacitor ladders each having a signal line connected with first terminals of capacitors and with one input of the comparator, and switches each of which is associated with one of the capacitors, connected to a second terminal of the respective capacitor with a first or a second reference potential, the input voltage being shifted when switching one or more of the switches. The control unit controls the number of converter units, and to set the switching states of the plurality of switches in conversion cycles and to obtain comparison results from each of the comparators in a comparison subsequent to each setting of the switching states.

Abstract: Traditionally, successive approximation register (SAR) analog-to-digital converters (ADCs) using binary search algorithms have consumed power by performing unnecessary switching of a capacitive digital-to-analog converter (CDAC) when a CDAC voltage is relatively close to a sampling analog input signal. Here, a SAR ADC is provided that reduces the number of switching events. To accomplish this, a multi-stage comparator is provided that generates multiple output signals for SAR logic. Based on these outputs, the SAR logic can more efficiently switch its CDAC using a ternary search algorithm to reduce power consumption and improve efficiency.

Abstract: A differential amplifier circuit comprising a differential amplifier capacitor and a mismatch error cancellation circuitry, a first pair of capacitors, a second pair of capacitors consisting of switching network. The switching network is arranged to operate in a first configuration wherein the first pair of capacitors is operably coupled to differential inputs of the differential amplifier circuit. The switching network is further arranged to operate in second configuration wherein each capacitor of the first pair of capacitors is operably coupled within a feedback loop between an output and an input of the differential amplifier such that the differential amplifier outputs signals representative of the sampled input voltage signals, and the second pair of capacitors are operably coupled in parallel between the outputs of the differential amplifier such that the second pair of capacitors sample the voltage difference between the outputs.

Abstract: A capacitance-to-digital converter for an extended range of capacitances includes a reference capacitor and one or more offset capacitors. Electrical charge accumulated in the offset capacitors is used to at least partially cancel the charge accumulated in a sensed capacitance to facilitate matching with a charge accumulated in the reference capacitor. The residual charge is passed to an integrator, the output from which is quantized and used to control switching of the capacitors. Immunity to tonal external noises and improved conversion speed are achieved by controlling the capacitor switching with a spread spectrum clock. The capacitance-to-digital converter may be used, for example, for sensing of the capacitances of capacitive elements in touch and proximity displays or other user interfaces.

Abstract: A capacitive-to-digital converter is provided which includes: sensor, offset and reference capacitors, an integrator circuit and a demodulation circuit. The sensor capacitor is switched according to a first clock and the offset capacitor according to a second clock, which has a higher switching frequency. The reference capacitor is switched according to a return signal from the converter's output. The integrator circuit includes an integrator capacitor, and has first and second nodes, with the sensor, offset and reference capacitors each being switched to the first and second nodes based on the respective first clock, second clock or return signal. The demodulation circuit receives and converts output of the integrator circuit into a digital output. The higher frequency clocking of the offset capacitor allows for a reduction in capacitance of the offset, reference or integrator capacitor, and the multiclocking of the converter allows for use of a multireferencing to the sensor capacitor.

Abstract: A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage.

Abstract: The present invention introduces a sub-converter stage used in a pipelined analog-to-digital converter. The sub-converter stage comprises an amplifier with a gain A, a sub analog-to-digital converter with comparators and a digital unit, a first capacitor with capacitance C, a second capacitor with capacitance C??C, and customized reference signal Vrefk, where ? ? ? C C = 4 A + 2 and V refk = V ref ? ( 1 - ? ? ? C 2 ? C ) . If the gain A of the amplifier is adjustable, the sub-converter stage needs an error detector to detect the difference between the output of the amplifier and reference signal Vref and adjust the gain A of the amplifier. The present invention also introduces a pipelined analog-to-digital converter employing the sub-converter stage.

Abstract: A switched capacitor circuit, which may be an SAR ADC, includes a plurality of bit switching circuits (33) each including a high-voltage sampling switch circuit (18) having a first terminal (28) coupled to a first terminal of a corresponding capacitor (22) and a second terminal coupled to receive an analog input signal (VSIG). A third terminal of the sampling switch circuit is coupled to an intermediate conductor (19). Each switching circuit (33) also includes a low-voltage conversion switch circuit (30) coupled to the intermediate conductor (19) and a combinational logic circuit (12) applying low-voltage signals to the conversion switch circuit and a level-shifting circuit (16) that generates corresponding high-voltage signals (HV_SIG_DRV) which control coupling of the first terminal (28) to the analog input signal and the intermediate conductor.

Abstract: A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2V-1 less than the number of a bit, a second conversion unit configured to differentially operate with the first conversion unit, a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units, a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal, and a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal.

Abstract: With Successive Approximation Register (SAR) analog-to-digital converters (ADCs), there are several different architectures. One of these architectures is a “convert and shut down” architecture, where an internal amplifier is powered down during the sampling phase to reduce power consumption. This powering down comes at a price in that a portion of the convert phase is lost waiting for the amplifier to be powered back up. Here, an apparatus is provided that makes use of the entire convert phase by coarsely resolving a few bits during the period in which the amplifier is powering up to have an increased resolution over conventional SAR ADCs with “convert and shut down” architecture, while maintaining low power consumption.

Abstract: The A/D conversion circuit according to one aspect of the present invention includes: a first sampling capacitor; a first sampling switch; a buffer circuit; a second sampling capacitor; a second sampling switch; a first converter; a first reset switch; and a second reset switch. The first and second sampling switches are turned on to track voltage to the first sampling capacitor and to sample buffer voltage to the second sampling capacitor through the buffer circuit. The first sampling switch is turned off to hold voltage. The second sampling switch is turned off so that the first converter reads the voltage from the second sampling capacitor to perform A/D conversion thereon. After that, the first and second reset switches reset the first and second sampling capacitors.

Abstract: An SAR-ADC includes input and reference terminals, first and second capacitor sets, a dummy capacitor, a comparator, a switch, and a logic. The first and second capacitor sets include first and second capacitors, respectively. The first capacitor has a first capacitance. The second capacitor has a second capacitance. The dummy capacitor has a third capacitance. The comparator compares an output voltage with a ground voltage and outputs a digital output code in accordance with a difference between the output and ground voltages. The switch is connected among the first capacitors of the first and second capacitor sets, and the reference terminal. The logic turns the switch based on the digital output code. The input terminal is located between the first and second capacitors of the first capacitor set. The second capacitor of the first capacitor set is located between the first and second capacitors of the second capacitor set.

Abstract: In an A/D converter, isolation switches are used between the capacitors and the conversion switches. The conversion switches are those switches used to selectively couple the plates of the binary weighted capacitors to either Vref or 0 volts during the A/D conversion process. During sampling of the input voltage signal, the isolation switches are opened to isolate the conversion switches from the wide range of possible input voltages at the bottom plates of the capacitors. Therefore, the voltage across the conversion switches is substantially limited to Vref. Hence, the conversion switches can be very fast low voltage switches. After sampling of the input voltage, when the sampled input voltage is locked in, the conversion switches operate normally to selectively connect the capacitor plates to either Vref or 0 volts for successively approximating the input voltage, whereby a digital code representing the sampled input voltage is generated.

Abstract: A differential chopper comparator compares an input signal voltage and a first voltage, and includes a first capacitor, a second capacitor, and a differential amplification unit including a differential amplification circuit. Either the input signal voltage or the first voltage is applied to one end of the first capacitor via a first switch unit. A fixed voltage is applied to one end of the second capacitor via a second switch unit. Either a non-inverting input terminal or an inverting input terminal of the differential amplification circuit is connected to the other end of the first capacitor, and the other terminal is connected to the other end of the second capacitor. An impedance of the first switch unit side viewed from one end of the first capacitor and an impedance of the second switch unit side viewed from one end of the second capacitor are substantially same.

Abstract: A single operational transconductance pipelined ADC incorporating a sample/hold amplifier and multiple MDAC stages. An input signal is sampled on input signal sampling capacitors, and then coupled around an operational transconductance amplifier (OTA) so that the output of the OTA is equal to the sampled voltage. There is no net charge transfer in this operation, so the noise and power dissipation normally associated with an input sample and hold circuitry (SHA) in a pipelined ADC is substantially eliminated. A pipelined ADC using a shared OTA for sample/hold and two MDACs is disclosed.

Abstract: A capacitor array includes a plurality of capacitor components each having a first node and a second node, and first nodes of the capacitor components are coupled to each other. A calibration method for the capacitor array utilizes a calibration capacitor component to couple the first nodes. Then, the calibration method determines a capacitance indication value regarding the specific capacitor component by coupling different references voltage to a second node of the specific capacitor component and coupling different test voltages to a second node of the calibration capacitor component. Accordingly, the calibration method calibrates the capacitance mismatches of the capacitor array in the digital domain.

Abstract: A solid-state imaging device includes: a plurality of pixels which are arranged in a matrix; a sequential scanning device that selects each row of pixels; and an analog-to-digital conversion unit having a first analog-to-digital converter that is connected to a vertical signal line to which a pixel signal is supplied from the pixel and performs a first bit-length analog-to-digital conversion on an output signal from the vertical signal line or a pixel output signal obtained by sampling the output signal, and a second analog-to-digital converter that, when the first analog-to-digital converter completes the conversion operation, subtracts an analog signal corresponding to the first bit-length from the pixel output signal and then performs a second bit-length analog-to-digital conversion.

Abstract: A switched capacitor sigma-delta modulator or another analog-to-digital converter (ADC) uses chopper stabilization. Chopping clock transitions are performed during non-active periods of the sampling clock phases, reducing disturbance of the circuit caused by chopping and increasing the time available for settling of the circuit given a particular sampling frequency. An asynchronous state machine may govern sampling and chopping clock transitions. In embodiments, inactive transition of a first sampling clock causes inactive transition of a second chopping clock, which in turn causes active transition of a first chopping clock. The next inactive transition of the first sampling clock causes inactive transition of the first chopping clock, which causes an active transition of the second chopping clock.

Abstract: A digital-to-analog conversion circuit operates by selectively discharging members of a plurality of capacitors. Charging of the capacitors occurs during a reset period while digital-to-analog conversion occurs as the capacitors are discharged. Those capacitors that are discharged are selected from the plurality of capacitors based on a digital input. The analog output includes the charge discharged from the capacitors. The capacitors are optionally divided into separate capacitor banks.

Abstract: A cable gateway, such as compatible with version 3.0 of the Data Over Cable Service Interface Specifications and other audiovisual standards, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline of at least two stages.

Abstract: A device that includes an internal data storage location coupled to an electrical conductor and an analog-to-digital converter coupled to the internal data storage location via the electrical conductor. In some embodiments, the analog-to-digital converter includes a comparator having an input coupled to the electrical conductor and a switch coupled to the electrical conductor.

Abstract: In order to minimize noise and current consumption in a hearing aid, an input converter comprising a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage comprises an amplifier (QA) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (Ca, Cb, Cc, Cd). The invention further provides a method of converting an analog signal.

Abstract: In order to minimize noise and current consumption in an EEG monitoring system (40) which can be continuously carried by a person to be monitored, an input converter (44) for an EEG monitoring system is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage comprises an amplifier (QA) and an integrator (RLF). A voltage transformer (IT) is placed in the input converter upstream of input stage. The transformation ratio of the voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage, thereby multiplying the signal voltage for the input stage by a fixed factor. The voltage transformer (IT) is a switched-capacitor voltage transformer having at least two capacitors (Cx, Cy, Cz). The invention further provides a method of converting an analog signal, and an EEG monitoring system comprising the input converter (44).

Abstract: In one embodiment, the modulator in an analog-to-digital converter includes a first reset switch and second reset switch, each controlled by a reset signal. The first reset switch is connected in a first reset feedback path between an input and an output of an integrator stage, and the second reset switch connected in a second reset feedback path between the input and the output of the integrator stage.

Abstract: An analog-to-digital converter includes a sample and hold unit, a successive control unit, a look-up memory, and a calibrating comparator, which further includes a positive input end, a negative input end, a timing signal input end, a data port, a latch unit, an enable switch, a first controllable resistor, a second controllable resistor, a reset switch assembly, a controllable capacitive device, and an output end.

Abstract: A charge-domain pipeline of at least two stages is provided. Each stage comprises a charge-storage node, a charge-transfer circuit for conveying charge from said charge-storage node out of said stage, a charge-control capacitor connected to said charge-storage node and driven by a periodic clock voltage, a comparator which compares the voltage of said charge-storage node to a reference voltage, and a digital latch which latches the state of said comparator output under control of a second periodic clock voltage and provides a latched digital output from said stage. The second stage of the pipeline further includes a first charge-redistribution capacitor connected to the charge-storage node of the second stage and driven by a conditional voltage responsive to the latched digital output from the first stage. The charge output from each stage of said pipeline is substantially similar to the charge input to said stage.

Abstract: A technique for operating a source follower buffer circuit, such as employed in a charge domain pipeline, to eliminate floating diffusion signal charge contamination from downstream circuits. The method and apparatus places an output of the circuit in a known state immediately prior to charge transfer into a floating diffusion, and again in known state immediately prior to charge transfer out of the floating diffusion.