Abstract: The analog-to-digital converter provided herein includes a capacitor bank comprising a plurality of binary-weighted capacitors, an operational amplifier having an inverting input node, a noninverting input node coupled to analog ground, and an output node, a reset switch, and an input switch. The reset switch is located between the capacitor bank and the operational amplifier, and it selectively couples the capacitor bank to the inverting input node. The input switch has its common terminal coupled to the capacitor bank, and the input switch selectively couples the capacitor bank to either an analog input voltage, a floating terminal, or analog ground. The capacitor bank includes N binary-weighted capacitors and one balacing capacitor that has a unit capacitance. During operation, the analog-to-digital converter generates an N-bit digital output and one polarity bit from the analog input voltage.

Abstract: In an analog-to-digital converter, when a capacitive element with a small capacitance is used in order to reduce power consumption, the characteristics of the analog-to-digital converter deteriorate due to the variation in the specific accuracy. Further, the method of reducing the variation with the specific accuracy causes an increase in the size of the circuit and power consumption. An analog-to-digital converter includes an analog core unit having at least one capacitive element. The capacitive element includes a capacitive bank having plural capacitive element units having substantially the same capacitance value, and the capacitive bank is configured to select one capacitive element unit from the plural capacitive element units with substantially equal probability.

Abstract: The present invention discloses a capacitive button device, comprising: a signal input unit, a first amplifier, a first switching unit, a second amplifier, a second switching unit, an analog-to-digital converting unit, a third switching unit, a data output unit, a data storage unit and a digital-to-analog converting unit. Thereby, the present invention overcomes the problem due to poor resolution of conventional capacitive buttons and can be used with touch panels. Moreover, the digital-to-analog converting unit is downsized with improved resolution and reduced cost in design and fabrication.

Abstract: A charge corresponding to an analog signal Vi is accumulated in first and second capacitors 25, 27, respectively. A digital signal VDIGN having a digital value (D1, D0, for example) corresponding to the analog signal Vi is generated. By connecting the second capacitor 27 between an output 21c and an inversion input 21a of an operational amplifier circuit 21 and supplying a first capacitor end 25a with an analog signal VD/A corresponding to the digital signal VDIGN, a first conversion value VOUT1 is generated in the output 21c of the operational amplifier circuit 21. By connecting the first and third capacitors 25, 33 between the output 21c and inversion input 21a of the operational amplifier circuit 21 and supplying a second capacitor end 27a with the analog signal VD/A, a second conversion value VOUT2 is generated in the output 21c of the operational amplifier circuit 21.

Abstract: An analog-to-digital converter circuit includes: a capacitor array including a plurality of first capacitors, each having a first terminal connecting to a common node and having a capacitance represented by the nth power of 2 (2n) on the basis of the smallest of the capacitances of the first capacitors=1; a second capacitor for contributing to attenuation of the voltage on the common node; a switch array, each switch of the switch array supplying and disconnecting one of a first reference voltage, a second reference voltage, and the voltage of an input signal to and from a second terminal of an associated one of the first capacitors; a second switch supplying and disconnecting a third reference voltage to and from the common node; a comparator comparing a voltage on the common node with the third reference voltage; and a control circuit controlling the first switches and the second switch.

Abstract: An A/D conversion device including a first A/D conversion section and a second A/D conversion section that each include a D/A converter that has a plurality of bit capacitors corresponding to bits of input data, a comparing section that compares a reference voltage with a difference voltage obtained by subtracting an analog input voltage from an output voltage of the D/A converter, and a control section that detects a data value of the input data at which the difference voltage is substantially the same as the reference voltage and outputs the data value as digital data according to the input voltage, and an adjusting section that serially connects the bit capacitors of the D/A converter of the first A/D conversion section and the bit capacitors of the D/A converter of the second A/D conversion section that correspond to the same bits, and adjusts a capacity of at least one of the bit capacitors so that a voltage between the two bit capacitors approaches a middle point of voltages of the two bit capacitors.

Abstract: Techniques for adaptively generating bias current for a switched-capacitor circuit are described. The switched-capacitor circuit charges and discharges at least one switching capacitor at a sampling rate and may be a ?? ADC that digitizes an analog signal at the sampling rate and provides digital samples. The switched-capacitor circuit may support multiple modes associated with different sampling rates. A bias circuit generates a bias current for the switched-capacitor circuit to be proportional to the sampling rate for a selected mode, to provide a bandwidth proportional to the sampling rate for an operational transconductance amplifier (OTA) within the switched-capacitor circuit, and to track changes in the switching capacitor(s) due to variations in integrated circuit (IC) process and temperature. The settling time of the switched-capacitor circuit may track with the multiple modes and across IC process and temperature variations.

Abstract: A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.

Abstract: A charge-domain pipeline of at least two stages is provided. Each stage comprises a charge-storage node, a charge-transfer circuit for conveying charge from said charge-storage node out of said stage, a charge-control capacitor connected to said charge-storage node and driven by a periodic clock voltage, a comparator which compares the voltage of said charge-storage node to a reference voltage, and a digital latch which latches the state of said comparator output under control of a second periodic clock voltage and provides a latched digital output from said stage. The second stage of the pipeline further includes a first charge-redistribution capacitor connected to the charge-storage node of the second stage and driven by a conditional voltage responsive to the latched digital output from the first stage. The charge output from each stage of said pipeline is substantially similar to the charge input to said stage.

Abstract: A sample and hold circuit includes an op-amp, inverting-side capacitors, and non-inverting-side capacitors paired with the inverting-side capacitors. At least one capacitor pair serves as a feedback capacitor in a holding phase. A total capacitance of the inverting-side capacitors to which an input voltage is applied in a sampling phase is ?, a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the sampling phase is ?, a total capacitance of the inverting-side capacitors to which the input voltage is applied in a holding phase is ?, and a total capacitance of the non-inverting-side capacitors to which the input voltage is applied in the holding phase is ?. ? is substantially different from ?. A total capacitance of a feedback capacitor pair is substantially equal to (?????+?)·(N/2), where N is a positive number.

Abstract: An A/D conversion device including a first A/D conversion section and a second A/D conversion section that each include a D/A converter that has a plurality of bit capacitors corresponding to bits of input data, a comparing section that compares a reference voltage with a difference voltage obtained by subtracting an analog input voltage from an output voltage of the D/A converter, and a control section that detects a data value of the input data at which the difference voltage is substantially the same as the reference voltage and outputs the data value as digital data according to the input voltage, and an adjusting section that serially connects the bit capacitors of the D/A converter of the first A/D conversion section and the bit capacitors of the D/A converter of the second A/D conversion section that correspond to the same bits, and adjusts a capacity of at least one of the bit capacitors so that a voltage between the two bit capacitors approaches a middle point of voltages of the two bit capacitors.

Abstract: A successive approximation analog-to-digital converter includes a capacitor array having a plurality of switch capacitors therein with varying weights, each having a common plate connected to a common node and a switched plate. A SAR controller samples an input voltage on said capacitor array in a sampling phase and redistributes the charge stored therein in a conversion phase by selectively increasing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm. Circuitry controls the sampling of the input voltage by the capacitor array and is responsive to at least one applied bias current. The at least one applied bias current operates at a first level responsive to a first mode of operation of the SAR ADC and operates at a second level responsive to a second mode of operation of the SARADC.

Abstract: A track and hold amplifier is provided. The track and hold amplifier includes an input node receiving an analog signal, a buffer coupled between a first node and an output node, a first switch coupled between the input node and the first node, a plurality of switching circuits and a voltage generating unit. Each of the switching circuits includes a capacitor coupled between the first node and a second node. The voltage generating unit selectively provides a common signal and a reference signal to the capacitors of the switching circuits, wherein the reference signal is independent from the analog signal and the common signal.

Abstract: An analogue to digital converter uses charge sampling in combination with a successive approximation conversion technique in order to combine anti-alias filtering and quadrature downconversion functions into the data converter. The conversion method is an energy-efficient realization for wide-band radio systems with moderate resolution specifications such as 4G or ultra-wideband radio (UWB). The converter uses two capacitor matrices, one to perform charge sampling, and one to be used simultaneously in the successive approximation technique, so that full use of an input signal is made and efficiency is maximised.

Abstract: A successive approximation analog-to-digital converter (ADC) includes a binary-weighted capacitor array, quantizer, and control block. One end of each capacitor is connected to the input of the quantizer, and a second end of each capacitor is controlled by the control block through a driver. A voltage is sampled, quantized, and stored as the most significant bit of the ADC's output. Depending on the result of the quantization, the control block toggles the driver of one of the capacitors corresponding to the most significant bit. The voltage at the common node is sampled again to obtain a second bit of the ADC's output. The operations are repeated as needed to obtain and store additional bits of the ADC's output. Similar configuration and process are described for a differential ADC. The operation is asynchronous, allowing extra time for metastable states only when such states occur.

Abstract: A solid state image pickup element includes a pixel unit having a plurality of pixels for photoelectric conversion disposed in a matrix shape and a pixel signal read circuit for reading pixel signals in the unit of a plurality of pixels from the pixel unit. The pixel signal read circuit includes a plurality of comparators disposed in correspondence with a pixel column layout for performing comparison judgment between a read signal potential and a reference voltage and outputting a judgment signal and a plurality of counters each for counting a comparison time of a corresponding one of the comparators, an operation being controlled by an output from a corresponding one of the comparators.

Abstract: Pipelined converter systems include a plurality of converter stages in which some stages generate and pass a residue signal to a succeeding stage for further conversion. The generation of the residue signal can inject spurious charges into a reference source that is used in the generation. The spurious charges reduce the accuracy of the residue signal and the accuracy of the system. Residue generator embodiments are thereby formed to provide reduction charges to the reference source that are arranged to oppose and reduce the spurious charges. This reduction of spurious charges significantly enhances system accuracy and linearity.

Abstract: A device that includes an internal data storage location coupled to an electrical conductor and an analog-to-digital converter coupled to the internal data storage location via the electrical conductor. In some embodiments, the analog-to-digital converter includes a comparator having an input coupled to the electrical conductor and a switch coupled to the electrical conductor.

Abstract: A technique for correcting errors in Bucket Brigade Device (BBD)-based pipelined devices, such as Analog-to Digital Converters (ADCs). The gain between pipeline stages is desired to be a specific amount, such as unity: that is, all net charge present in each stage ideally is transferred to the next stage. In practical BBD-based circuits, however, the charge-transfer gain is less than ideal, resulting in errors. The approach described herein provides analog correction of such errors due to both capacitor mismatch and to sub-unity charge-transfer gain. In certain embodiments the adjustment circuit may use an adjustable current source and Field Effect Transistor to introduce the correction. In still other embodiments, the adjustment circuit may determine a voltage-feedback coefficient.

Abstract: A cable gateway, such as compatible with version 3.0 of the Data Over Cable Service Interface Specifications and other audiovisual standards, that uses an analog front end having a charge-domain analog-to-digital converter that uses a charge-domain pipeline of at least two stages.

Abstract: An A/D converter is provided. The A/D converter determines a digital output value according to the resistance of the TMR device, resistance of which changes according to the magnetic field generated by at least one electrode into which current flows according to an analog input signal. Accordingly, an A/D converter to implement high resolution and high speed with low power consumption can be provided.

Abstract: The present invention provides a signal converting apparatus with built-in self test, including a first signal converting circuit, a second signal converting circuit, a comparing apparatus, a control logic apparatus and a voltage divider. The first and the second signal converting circuit take a first and a second reference voltage and are respectively controlled by a first and second set of control signals from the control logic apparatus for the comparing apparatus to generate a comparing result.

Abstract: Circuits and methods for determining component ratios are provided. An analog to digital converter circuit may include comparison capacitors arranged in an upper group and a lower group for quantizing analog signals into the digital domain. In addition to determining the lower bits during an analog to digital conversion of an input sample, the lower group of comparison capacitors may also be used during calibration mode to quantize a ratio signal that represents the capacitor mismatches of the upper group rather than using a dedicated digital-to-analog converter to perform this function.

Abstract: Provided are a method of algorithmic analog-to-digital conversion and an algorithmic Analog-to-Digital Converter (ADC). The algorithmic ADC includes a Multiplying Digital-to-Analog Converter (MDAC). The MDAC includes a Digital-to-Analog Converter (DAC) for converting a first digital signal into an analog signal, a subtractor for calculating a difference between the signal output from the DAC and an analog signal input from a first Sample and Hold Amplifier (SHA), an amplifier for amplifying the difference, a first capacitor unit connected with an output end of the first SHA and an input end of the amplifier through a first switching unit, a second capacitor unit connected with the input end and an output end of the amplifier through a second switching unit, and a third capacitor unit connected with the input end and the output end of the amplifier through a third switching unit.

Abstract: A gain matching method for a single bit gain ranging analog to digital converter including selecting, in response to a gain setting, a number of gain elements to be enabled in a multi-element gain controlled array interconnected between an analog input and an analog to digital converter, and patterning the enablement of the selected number of gain elements among the gain elements for matching the gain of the analog to digital converter for a range of gain settings of the converter to reduce in-band gain error due to gain element mismatch.

Abstract: A parallel type analog-to-digital conversion circuit, including a reference signal generating portion and a comparison amplification portion, the comparison amplification portion including a plurality of amplifiers, input resetting switches, first sampling capacitors, second sampling capacitors, first sampling switches, and second sampling switches.

Abstract: Disclosed is a pipeline ADC in which an operational amplifier is shared between circuit blocks that construct local A/D converters of nth and (n+1)th stages, a sampling capacitor of the nth stage is divided into a plurality of sampling capacitors, and some of the plurality of sampling capacitors thus divided in the nth stage are adopted as sampling capacitors of the (n+1)th stage.

Abstract: A single-ended charge-domain pipeline of at least two stages is provided. Each stage comprises a charge-storage node, a charge-transfer circuit for conveying charge from said charge-storage node out of said stage, a charge-control capacitor connected to said charge-storage node and driven by a periodic clock voltage, a comparator which compares the voltage of said charge-storage node to a reference voltage, and a digital latch which latches the state of said comparator output under control of a second periodic clock voltage and provides a latched digital output from said stage. The second stage of the pipeline further includes a first charge-redistribution capacitor connected to the charge-storage node of the second stage and driven by a conditional voltage responsive to the latched digital output from the first stage. The charge output from each stage of said pipeline is substantially identical to the charge input to said stage.

Abstract: This disclosure relates to systems and methods for analog to digital conversion using delta sigma modulation. To this end, the delta sigma modulator includes a double sampling DAC and integrator and a 1-bit comparator, with reference loading insensitivity.

Abstract: Provided is a current sampling mixer that can be applied to a broadband broadcasting system. The current sampling mixer can change a structure of a current sampler including a plurality of capacitors to select and sum capacitors having a weight value given in the output, thereby performing a finite impulse response filter function and a harmonic rejection function.

Abstract: An SAR ADC provides increased immunity to noise introduced by time varying noise components provided on reference potentials (VREF). Reference voltage noise contributions are canceled by introducing a reference voltage component to a pair of binary weighted capacitor arrays (NDAC and PDAC) during bit trials, which are presented to a differential comparator as a common mode signal and rejected. During sampling, select elements in either the PDAC or the NDAC also obtain a reference voltage contribution. Although the sampled VREF signal may have a noise contribution, the noise is fixed at the time of bit trials, which can improve performance. Generally, the scheme provides a 50% reduction in noise errors over the prior art for the same VREF noise. Additional embodiments described herein can reduce noise errors to 25% or even 12.5% over prior art systems.

Abstract: A filter applied in a sigma-delta modulator includes an integrator, a signal attenuator and a feedback circuit, in which these components are connected in series sequentially to form a local feedback circuit. The integrator integrates an input signal to output an integral signal. Accordingly, the signal attenuator attenuates the integral signal to output an attenuation signal to the local feedback circuit so as to share a part of attenuation amount to reduce the chip area of the sigma-delta modulator.

Abstract: Circuits, methods, and apparatus that provide sampling networks that avoid undesired transient voltages. One example provides a sampling network that includes a switch such that charge is transferred to an integrator in two separate steps instead of one. This switch connects the first side of a capacitor to an intermediate voltage after it is connected to an input voltage and before it is connected to a reference voltage, where the reference voltage is the output of a one-bit digital-to-analog converter. This intermediate switching allows charge to be transferred from a sampling capacitor to an integrating capacitor in two steps, thus avoiding undesirable transient voltages.

Abstract: An analog front end for a multi-channel signal processor is provided. The analog front end includes a first stage that is operable to receive a plurality of channel inputs. The first stage includes a ping/pong capacitor array corresponding to each of the channel inputs and an operational amplifier that may be coupled successively to each of the ping/pong capacitor arrays.

Abstract: A method is for processing an incident signal, in which the incident signal is delivered to a transconductor stage, and a current output of the transconductor stage is coupled to an output capacitor so as to deliver to the output capacitor a current signal lasting for at least part of the first half-period of each period of a periodic signal and to thus obtain a frequency-transposed signal at the output capacitor. Upon the occurrence of each part of the first half-period, the voltage of the current output, seen from the output capacitor, is reset to a value equal to that of the voltage of the output capacitor.

Abstract: Systems and methods for a jitter insensitive 1-bit digital to analog converter (DAC) are described. The jitter insensitive 1-bit DAC employed in the feedback loop of a delta sigma analog to digital converter (ADC) converts a 1-bit digital data into the corresponding analog output.

Abstract: An electronic device that includes an internal data storage location coupled to an electrical conductor and a quantizing circuit coupled to the internal data storage location via the electrical conductor. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and an output, where the input is coupled to the electrical conductor and a digital filter coupled to the output of the analog-to-digital converter.

Abstract: An integrated circuit includes a plurality of circuit groups, each circuit group containing a plurality of analog inputs, a buffer, a sample/hold circuit and a comparator. Each buffer has an input to which any of the analog inputs in its group may be programmably connected. The output of each buffer is coupled to the input of the sample/hold circuit in the group. The output of each sample/hold circuit is coupled to one input of a multiplexer. The output of the multiplexer is coupled to the input of an amplifier having programmable gain and programmable offset. The comparator in each group has inputs that may be programmably coupled to at least one analog input in the group or to a reference voltage source.

Abstract: A digital analog converter has an input terminal receiving a digital input signal, a lower-side capacitor group coupled to a lower-side common terminal in parallel, an upper-side capacitor group coupled, in parallel, to an upper-side common terminal at which an analog output signal is generated, a coupling capacitor provided between the lower-side common terminal and the upper-side common terminal, a switch group coupled to the upper-side capacitor group and the lower-side capacitor group and controlled as a conduction state and a non-conduction state in accordance with the digital input signal, and an adjusting capacitor coupled to the lower-side common terminal and having a variable capacitance value.

Abstract: An analog-to-digital converter circuit and method with reduced non-linearity are described. The circuit includes an amplifier module having at least one active input coupled to at least three capacitor devices. The circuit further includes multiple switches coupled to each respective capacitor device. One switch coupled to each capacitor device is further coupled to an output of the amplifier module, such that each capacitor device can be selectively coupled to the output of the amplifier module. At least one switch coupled to each capacitor device is further coupled to a reference voltage source to receive at least one reference voltage signal. Finally, at least one switch coupled to each capacitor device is further coupled to receive an input voltage signal.

Abstract: A digital to analog converter including a first capacitor, a second capacitor, an operational amplifier, and a switch is disclosed. During a first period, the first capacitor stores a first voltage and the second capacitor stores a second voltage. The operational amplifier comprises an input and an output. The switch parallels the first and the second capacitors with the operational amplifier at the input and output according to a digital signal during a second period.

Abstract: An analog-to-digital converter comprising a capacitor array having a plurality of unit capacitors, each having first and second inputs; a comparator having a pair of inputs and at least one output; and a controller configured to couple one input of each unit capacitor of the plurality of capacitors to the inputs of the comparator, and to control a feedback loop between the pair of inputs and the at least one output of the comparator.

Abstract: An electronic device is provided for analog to digital conversion using successive approximation. The device comprises a first ADC stage. The first ADC stage includes a first plurality of capacitors adapted to sample an input voltage, and adapted to be coupled to either a first reference signal level or a second reference signal level. At least one capacitor of the first plurality of capacitors is adapted to be left floating. A control stage is adapted to switch the at least one floating capacitor to the first reference signal level or the second reference signal level in response to an analog to digital conversion decision made by a second ADC stage.

Abstract: An analog-digital converter performs AD conversion of an upper m bits by sequential comparison, and performs AD conversion of a lower n bits by integration. This increases accuracy, reduces power consumption during operation, reduces variation between analog signals and digital signals, and reduces the required layout area by decreasing the number of capacitor elements needed. Also, the AD conversion of the n bits by integration is performed by ramp voltage quantized with a margin of k bits of the lower n bits. As such, preferable AD conversion characteristics can be obtained when offset or the like is produced in a DA conversion circuit for generating ramp voltage.

Abstract: The method and device include the filtering and the analog/digital conversion of an intermediate signal. The intermediate signal is processed by a filtering and analog/digital conversion circuit that is configurable using switched passive capacitor technology. The various configurations successively adopted by the circuit provide filtering and analog/digital conversion to be successively carried out.

Abstract: Embodiments of the present invention provide a pipeline ADC front-end sampling structure that provides a continuous time input signal to a flash comparator for sampling. By providing a continuous time input signal to the flash comparator, no delay is introduced from the need to transfer a DC charge representing the sampled input to the flash comparator. Matching sampling networks in the residual generator and the flash comparator are avoided due to the high bandwidth response requirements of the residual generator and the flash comparator when operating on high frequency input signals.

Abstract: A low-power column parallel cyclic analog-to-digital converter and an imaging device using the same. The analog-to-digital converter comprises one stage and is optimized to reduce power, noise and capacitor settling time. The one stage analog-to-digital converter comprises a multiplying circuit for performing a multiplication operation during conversion phases and a sub-analog-to-digital converter connected to receive analog output signals from the multiplying circuit. The sub-analog-to-digital converter converts, during the conversion phases, the analog output signals into portions of an N-bit digital code. The multiplying circuit switches configurations between conversion phases and uses the portions of the digital code during the conversion phases to generate new analog output signals for subsequent conversion by the sub-analog-to-digital converter.

Abstract: An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.

Abstract: A successive approximation A/D converter includes a capacitive D/A converter including capacitors, and generates a voltage based on the input voltage and a first digital signal including J bits; a resistive D/A converter that generates a voltage based on a second digital signal; a capacitor that capacity-couples the voltage to an output node; a comparator that generates a result based on the voltage; a control circuit that supplies the first digital signal to the capacitive D/A converter according to the result and outputs a third digital signal indicating a correction and a fourth digital signal including K bits; and a digital calculating circuit that generates the second digital signal including K bits based on the third digital signal and the fourth digital signal, and supplies the second digital signal to the resistive D/A converter, a (J+K) bit digital data is generated based on the input signal.

Abstract: A filter intended to receive a discrete time signal at a sampling dock frequency, comprising a determined number, greater than 2, of filtering units, each filtering unit comprising head capacitors in a number equal to the determined number, assembled in parallel between an input terminal and the terminal of an integration capacitor; and means for connecting, in successive clock cycles in a number equal to the determined number, successively each head capacitor to the input terminal, and for then simultaneously connecting the head capacitors to the integration capacitor, and in which the successive dock cycles during which the head capacitors of a filtering unit are connected to the input terminal are offset by one dock cycle from one filtering unit to the next one.