Abstract: Methods and systems for storing a set of two or more variable length data blocks in a memory. Each variable length data block having a maximum size of N*B, wherein N is an integer greater than or equal to two, and B is a maximum data size that can be written to the memory using a single memory access request. The methods include: storing, for each variable length data block of the set, the first P non-overlapping portions of size B of the variable length data block in a chunk of the memory allocated to that the variable length data block, wherein P is a minimum of (i) a number of non-overlapping portions of size B of the variable length data block and (ii) X which is an integer less than N; storing any remaining portions of the variable length data blocks in a remainder section of the memory that is shared between the variable length data blocks of the set; and storing, in a header section of the memory, information indicating the size of each of the variable length data blocks in the set.

Abstract: A weight data compression method includes: generating a 4-bit data string of 4-bit data items each expressed as any one of nine 4-bit values, by dividing ternary weight data into data items each having 4 bits; and generating first compressed data including a first flag value string and a first non-zero value string by (i) generating the first flag value string by assigning one of 0 and 1 as a first flag value of a 1-bit flag to a 4-bit data item 0000 and assigning an other of 0 and 1 as a second flag value of the 1-bit flag to a 4-bit data item other than 0000 among the 4-bit data items in the 4-bit data string and (ii) generating the first non-zero value string by converting the 4-bit data item other than 0000 into a 3-bit data item having any one of eight 3-bit values.

Abstract: Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.

Abstract: Embodiments are provided for reducing data using a plurality of compression operations in a computing storage environment. A speed of data writing to a virtual tape device and an availability of one or more processor devices for the virtual tape device may be monitored. One or more requests may be received for writing data to the virtual tape device. Data to be written to the virtual tape device, corresponding to a selected number of the one or more requests for writing the data, may be compressed according to both the speed of data writing to the virtual tape device and the availability of one or more processor devices for the virtual tape device. The compressed data may be stored in the virtual tape device in record units. Non-compressed data may be compressed in the virtual tape device at a subsequent period of time (e.g., future time period).

Abstract: According to one embodiment, a memory system includes a storage device and a controller. The controller is configured to control data write to the storage device and data read from the storage device based on a request from a host device. The controller is configured to maintain or invert logic of first data that is part of transmit data to be transferred to the storage device by N bits per 1 unit interval (UI) through N data signal lines (N is a natural number of one or more), create second data indicating presence or absence of inversion of the logic of the first data, and transfer the first data and the second data to the storage device through the N data signal lines.

Abstract: A multi-node communication network may include a plurality of nodes including a first node and a second node. Each of the plurality of nodes may include a communication interface and a controller. The first node may be configured to: obtain an uncompressed packet, the uncompressed packet having uncompressed header data and a payload; compress the uncompressed header data into compressed header data having a tag and at least one compressed unit (CU), the tag indicating at least one type of compression for the at least one CU; and transmit a packet having the compressed header data and the payload to the second node. The second node may be configured to: receive the packet having the compressed header data and the payload; and based at least on the tag, decompress the at least one CU.

Abstract: Techniques are provided for multiset encoding and evaluation. One method comprises encoding a multi set comprised of entities as a product of a prime number assigned to each entity in the multiset to obtain an integer representation of the multiset; adding a first entity to the multiset by multiplying the integer representation of the multiset by the prime number assigned to the first entity; removing a second entity from the multiset by dividing the integer representation of the multiset by the prime number assigned to the second entity; and identifying the entities in the multi set by decomposing the integer representation into a product of the prime numbers assigned to each of the entities in the multiset. The entities in the multiset can be, for example, devices that a given user was connected to at the given time; and/or the users connected to a given device at the given time.

Abstract: Mechanisms to reduce noise and/or energy consumption in PAM communication systems, utilizing conditional symbol substitution in each burst interval of a multi-data lane serial data bus.

Abstract: Within a storage array, allocation of physical storage capacity within a storage array may be managed in standard size allocation units of uncompressed data, e.g. 128kb tracks, while smaller sub-allocation unit compression domains, e.g. 32kb quarter tracks, are used for compressed data. The data within a sub-allocation unit may be compressed to a size that is less than the capacity of the sub-allocation unit. Data associated with sub-allocation units that are not required to service a read or write may not need to be compressed or decompressed in order to service the read or write. Consequently, resource usage may be more efficient.

Abstract: A device for compressing first data which are to be compressed comprises a control unit configured to compress the first data based upon further data to obtain compressed data. The control unit is configured to provide memory area information indicative of a memory location of the further data.

Abstract: A method of encoding a stream of data bits includes encoding a bit 1 of the data stream as a first symbol if a bit immediately preceding the bit 1 is encoded as 0 and a bit of the data stream immediately succeeding the bit 1 is 0, encoding the bit immediately succeeding the bit 1 as 1, encoding a bit 0 of the data stream as a second symbol if a bit immediately preceding the bit 0 is encoded as 1 and a bit of the data stream immediately succeeding the bit 0 is 1, and encoding the bit immediately succeeding the bit 0 as 0.

Abstract: Embodiments of the present disclosure relate to a method and device for migrating data. The method comprises identifying cold data in a primary storage system. The method further comprises, in response to determining that the cold data is in a non-compression state, obtaining the cold data from the primary storage system via a first interface, the first interface being configured for a user to access the primary storage system. The method further comprises obtaining, in response to determining the cold data is in a compression state, the cold data in the compression state from the primary storage system via a second interface that is different from the first interface. The method further comprises migrating the obtained cold data from the primary storage system to a secondary storage system.

Abstract: A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. This disclosure describes a hardware-based programmable data compression accelerator for the data processing unit including a pipeline for performing string substitution. The disclosed string substitution pipeline, referred to herein as a “search block,” is configured to perform string search and replacement functions to compress an input data stream. In some examples, the search block is a part of a compression process performed by the data compression accelerator. The search block may support single and multi-thread processing, and multiple levels of compression effort.

Abstract: Methods, apparatus, and system to compress a data file to form a compressed data file. The data file may be used to configure control of hardware, such as peripheral hardware. The compressed data file may be stored locally or transmitted to another computer device. The compressed data file may be stored in a flash memory. The compressed data file may require less space in flash memory components, relative to flash memory suitable to hold the (original, pre-compressed) data file. Compression and/or decompression may be performed by, for example, a flash memory controller. The compressed data file may be decompressed dynamically, on an as-needed basis, to provide code for execution by a processor and/or to configure a computer device to use hardware or other components. Other software and hardware components do not need to be aware that the data file is compressed in the flash memory.

Abstract: This application discloses a precoding matrix index (PMI) reporting method, and related communications apparatus and medium. The method includes: determining an rank indicator (RI) and a PMI, where the PMI is used to determine R precoding matrices W1, . . . , WR. An rth precoding matrix Wr in the R precoding matrices satisfies Wr×W1×W2, r, where an lth row of W2, r is obtained by performing DFT transform on an lth row of a matrix V2,rand R is indicated by the RI. The PMI includes first indication information and second indication information. The first indication information includes location index information. The location index information is used to indicate Km,r element locations tr,m,1, . . . , tr,m,Kmj?{1, . . . , T} on an mth row of V2,r. The second indication information is used to indicate Km,r complex coefficients ar,m,tr,mj at the element locations tr,m,1, . . . , tr,m,kmj on the mth row of V2,r. V2,r is determined based on the Km,r element locations and the Km,r complex coefficients.

Abstract: According to one embodiment, a system in response to a request to back up a virtual machine to a backup storage system, generates a snapshot of the virtual machine. The system identifies one or more files within the snapshot that satisfy a predetermined criterion. If the one or more files are identified, the storage system backs up a modified representation of the snapshot by, analyzing the snapshot to determine addresses of the identified one or more files within the snapshot, and substituting content of the identified one or more files at the addresses with a predetermined data pattern. The system deduplicates the modified representation of the snapshot to remove duplicated data segments and copies data segments of the modified representation of the snapshot to the backup storage system such that data segments to be copied to the backup storage system is minimized.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.

Abstract: A system that includes an administrative device in signal communication with the one or more devices in the network. The administrative device is configured to access a first node table for a first node and access a second node table for a second node. The administrative device is further configured to obtain a correlithm object key, to re-encode the first set of output correlithm objects using the correlithm object key, and to shuffle the order of the re-encoded first set of output correlithm objects. The administrative device is further configured to re-encode the second set of input correlithm objects using the correlithm object key and to shuffle the order of the re-encoded second set of input correlithm objects. The administrative device is further configured to overwrite the first node table with the reconfigured first node table and the second node table with the reconfigured second node table.

Abstract: An electronic device for maintaining a distributed ledger, which is maintained by multiple electronic nodes, wherein the distributed ledger includes multiple blocks which are associated at least with one of the previously recorded blocks and wherein a block can be added to the distributed ledger based on a mining process, has circuitry configured to perform a mining process of a block to be added to the distributed ledger, wherein the mining process by at least a part of the multiple electronic nodes includes compressing data of the block to be added to the distributed ledger.

Abstract: An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.

Abstract: A processor includes a binary translator an a decoder. The binary translator includes logic to analyze a stream of atomic instructions, identify words by boundary bits in the atomic instructions, generate a mask to identify the words, and load the mask and the plurality of words into an instruction cache line. The words include atomic instructions. At least one word includes more than one atomic instruction. The decoder includes logic to apply the mask to identify a first word from the instruction cache line and decode the first word based upon the applied mask.

Abstract: Dynamic history multistream long range compression (DHC) techniques are described for efficiently compressing multiple, prioritized data streams received over a channel. A history buffer is associated with each received stream and a DHC compressor dynamically allocates fixed sized history sections to and from each history buffer. In implementations, the DHC compressor makes stream history size adjustments prior to compressing a block of data and sends information identifying the change in history size to a DHC decompressor. The DHC decompressor sends signaling information to the DHC compressor that is used to ensure that the DHC decompressor can operate with a fixed amount of total history memory.

Abstract: A system that includes an administrative device configured to send a first remap node command that includes a correlithm object key and identifies an output correlithm object type. The system further includes a first device configured to receive the first remap node command and to obtain the correlithm object key from the first remap node command. The first device is further configured to access the first node table linked with the first node, to determine the first remap node command identifies an output correlithm object type, to re-encode the first set of output correlithm objects using the correlithm object key in response to determining the first remap node command identifies an output correlithm object type, and to shuffle the order of the re-encoded first set of output correlithm objects.

Abstract: A precoding matrix determining method and apparatus are provided. A terminal determines a precoding matrix, where the precoding matrix includes at least two column vector sets, a column vector associated with any column vector set of the at least two column vector sets exists in the at least two column vector sets, and both the any column vector set and the associated column vector are applied on different polarization antennas; the terminal determines a first precoding matrix indicator (PMI) and a second PMI based on the precoding matrix; and the terminal sends the first PMI and the second PMI to a base station. In this solution, different column vectors are applied to different polarization antennas. Therefore, a prior-art defect of unbalanced beam coverage performance is overcome.

Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

Abstract: A method for error detection in transmissions on a multi-wire interface includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal.

Abstract: An apparatus and method for performing efficient lossless compression.

Abstract: A computer implement format preservation based masking system and method is provided. The system obtains a first set of letters and a private key, and encrypts the first set of letters to obtain an encrypted letters list using the first set and private key. The encrypted letters list comprises a set of encrypted letters. A dynamic map is generated based on the encrypted letters, which includes one or more keys, each key being specific to a letter in the first set letters. A position of each of maskable letters in a second set of letters is calculated using the dynamic map, and performs masking of the maskable letters based on the position of each of the maskable letters to obtain masked data using the dynamic map.

Abstract: A data compression/decompression apparatus, for example, acquires sampling data obtained by sampling an audio signal with a predetermined period, and converts the sampling data into frequency domain data. The data compression/decompression apparatus divides a data sequence of the converted frequency domain data into a plurality of blocks such that the number of pieces of data included in each block is variable, and compresses each block.

Abstract: The present disclosure relates to gateway path variable detection for metric collection. In some embodiments, a gateway receives a plurality of requests from one or more clients, wherein each request of the plurality of requests is directed to a service and comprises a path. In some embodiments, the gateway separates the path of each request into one or more sub-paths and inserts nodes representing each sub-path into a tree hierarchically based on the path, excluding redundant nodes. If a node has a parent node in the tree, in some embodiments, the gateway determines whether a number of child nodes of the parent node exceeds a variance threshold and, if so, identifies the sub-path as a variable and collapses all nodes at the same level into one node representing the variable, inserting child nodes of collapsed nodes as child nodes of the one node, and removing redundant child nodes.

Abstract: The present invention relates to a method for transmitting, by a base station, a downlink signal using a plurality of transmission antennas comprises the steps of: applying a precoding matrix indicated by the PMI, received from a terminal, in a codebook to a plurality of layers, and transmitting the precoded signal to the terminal through a plurality of transmission antennas. Among precoding matrices included in the codebook, a precoding matrix for even number transmission layers can be a 2×2 matrix containing four matrices (W1s), the matrix (W1) having rows of a number of transmission antennas and columns of half the number of transmission layers, the first and second columns of the first row in the 2×2 matrix being multiplied by 1, the first column of the second row being multiplied by coefficient “a” of a phase, and the first column of the second row being multiplied by “?a”.

Abstract: The embodiment of the disclosure discloses a base station, a mobile station and a method thereof. The base station includes a processor and a transceiver. The processor determines a first subgroup to which a first mobile station belongs, wherein the first mobile station is one of a plurality of mobile stations, the plurality of mobile stations are grouped into G groups based on spatial correlation, the mobile stations in each of the G groups are further grouped into S subgroups based on polarization, the mobile stations in a same subgroup have a same polarization and the mobile stations in different subgroups have different polarizations. The transceiver communicates with the first mobile station according to the polarization of the first subgroup. The embodiments of the disclosure utilize polarization jointly with the spatial correlation in dual structured procoding so that feedback overhead can be reduced.

Abstract: An output adjustment device of an analog output module may include: a microprocessor unit (MPU) performing an arithmetic operation on a digital signal, an analog output module including an analog signal output unit receiving a signal output from the MPU to output an analog signal, and an output signal adjustment unit outputting a control signal for controlling a magnitude or amplitude of the output analog signal to the MPU.

Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.

Abstract: A buffer circuit (403) includes a primary interface (404), a secondary interface (405), and an encoder/decoder circuit (407A, 407B). The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

Abstract: A method, an apparatus, and a computer program product for wireless communication are provided in which a first pre-coding matrix for use on a portion of a set of resource blocks (RBs) is determined. At least one beamforming vector of the set of beamforming vectors is modified by applying a phase rotation to generate a modified pre-coding matrix. The modified pre-coding matrix is applied to one or more demodulation reference signals and data associated with the portion of the set of RBs for transmission using at least one antenna.

Abstract: The present invention relates to a method for transmitting, by a base station, a downlink signal using a plurality of transmission antennas comprises the steps of: applying a precoding matrix indicated by the PMI, received from a terminal, in a codebook to a plurality of layers, and transmitting the precoded signal to the terminal through a plurality of transmission antennas. Among precoding matrices included in the codebook, a precoding matrix for even number transmission layers can be a 2×2 matrix containing four matrices (W1s), the matrix (W1) having rows of a number of transmission antennas and columns of half the number of transmission layers, the first and second columns of the first row in the 2×2 matrix being multiplied by 1, the first column of the second row being multiplied by coefficient “a” of a phase, and the first column of the second row being multiplied by “?a”.

Abstract: A storage apparatus includes a semiconductor storage device, and a storage controller coupled to the semiconductor storage device, and which stores data to a logical storage area provided by the semiconductor storage device. The semiconductor storage device includes one or more non-volatile semiconductor storage media, and a medium controller coupled to the semiconductor storage media. The medium controller compresses data stored in the logical storage area, and stores the compressed data in the semiconductor storage medium. The size of a logical address space of the logical storage area is larger than a total of the sizes of physical address spaces of the semiconductor storage media.

Abstract: An encoding apparatus detects a bit repeating portion in a mantissa part bit string. The mantissa part bit string is a part of a bit string of a floating point number and corresponds to a mantissa of the floating point number. The floating point number has a sign, an exponent, and the mantissa. The bit repeating portion includes repetitions of a particular bit pattern up to a tail of the mantissa part bit string. The encoding apparatus encodes the bit string of the floating point number into a converted bit string with a first part bit string and a second part bit string. The first part bit string includes a sign part bit string, an exponent part bit string, and a part of the mantissa part bit string that exclude a bit string portion after a secondary repetition of the particular bit pattern. The second part bit string specifies the particular bit pattern in the first part bit string.

Abstract: The disclosed embodiments provide a system for densely storing strings within the memory of a software program. During operation, the system receives a set of characters to be stored in a string, wherein each character is encoded using a multi-byte public encoding. The system then stores the set of characters in the string at least in part by performing the following steps. The system determines whether every character of the set can be encoded using a first private encoding that consumes less space per character than the multi-byte public encoding. Responsive to determining that every character of the set can be encoded using the first private encoding, the system stores a particular value associated with the first private encoding in a particular field of the string. The system then stores the set of characters in the string in the first private encoding.

Abstract: Various methods and apparatuses are described for performing high speed format translations of incoming data, where the incoming data is arranged in a delimited data format. As an example, the data in the delimited data format can be translated to a fixed field format using pipelined operations. A reconfigurable logic device can be used in exemplary embodiments as a platform for the format translation.

Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for recognizing patterns in log files with unknown grammar. A computer replaces one or more alphanumeric strings with a first alphanumeric character to generate a first resulting string. The computer then replaces one or more identical pairs of characters of the first resulting string with a second alphanumeric character to generate a second resulting string. The computer then replaces one or more consecutive instances of the second alphanumeric character, in the second resulting string, with one instance of the second alphanumeric character to generate a compressed string.

Abstract: An output sequence of data elements is processed. The output sequence of data elements represents a sequence of input data elements in a compressed format. An output data element includes a backward reference for each string in the input data elements that occurs again in an input data element that is used to produce the output data element. A backward reference identified in a selected output data element is used for selecting the string to which it refers in the stored input data elements. The selected string is combined with strings of one or more subsequent output data elements. A matching sequence in the stored input data elements matching at least part of one or more combined strings is found. A combined string of the one or more combined strings having the longest matching sequence is selected. The backward reference is redefined to indicate the longest matching sequence.

Abstract: Concurrently writing an uncompressed data element, if the uncompressed data element comprises an indication that it is valid, in a main hash table using a first address generated by a first hash function, and reading a first data element from the main hash table using the first address. Introducing a first pipeline delay for maintaining the uncompressed data element in a first data path until the first data element is read. Concurrently writing the first data element to a victim hash table, if the first data element comprises an indication that it is valid, using a second address generated by a second hash function, and reading a second data element from the victim hash table using a third address generated by the second hash function. Introducing a second pipeline delay for maintaining the uncompressed data element in the first data path until the second data element is read.

Abstract: An apparatus has a shared fuse array and a plurality of x86-compatible microprocessors disposed on a die. The shared fuse array has a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes accessible by a plurality of x86-compatible microprocessors and another plurality of semiconductor fuses programmed with uncompressed system hardware configuration data that is employed to initialize control circuit elements within the plurality of x86-compatible microprocessors. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessors is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of microprocessors.

Abstract: A computer-implemented process, computer program product, and apparatus for computing excluded data. A web page of interest is identified to form an identified page. The identified page is loaded a first time to form a first load, and responsive to a determination that a delta has not been computed for the identified web page, the identified page is loaded a second time to form a second load. Whether portions of the first load differ from portions of the second load is determined. Responsive to a determination portions of the first load differ from portions of the second load, the portions that differ to form a delta are identified. The delta is stored to form stored delta and the stored delta is excluded from a document object model associated with the identified page to form a modified document object model.

Abstract: It is an objective of the present invention to provide a solution to automatically remove the redundancy among the user's files, and to efficiently use the memory area of the server without placing an unreasonable cost on a service provider and on a user. In order to attain the above objective, a file storage apparatus, which replaces a bit sequence, which matches a bit sequence correlated with a code and managed, with said code, thereby performing compression and storage of a file correlated with the user identification information and inputted, comprising a distribution unit for management cost, which performs distribution of management cost with respect to each user identification information, is provided. Here, the management cost for code and/or bit sequence corresponds to cost necessary for storage or maintenance of the code and/or bit sequence. Examples of the cost include cost for size of required storage area, and cost for required operation of CPU.

Abstract: A device for communications over a multimedia communication interface. The device can be a source device including a scrambling circuit that receives control data associated with multimedia data to be transmitted over the multimedia channel of the multimedia communication interface, and generates scrambled control codes based on the control data. An encoding circuit generates transition minimized control codes based on the scrambled control codes. The device transmits the transition minimized control codes to a sink device via the multimedia channel. The sink device may also decode and de-scramble the transition minimized control codes received from the source device via the multimedia channel.

Abstract: Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power.