Abstract: A method for decoding includes receiving a message at a decoding device, where the message includes a code corresponding to a sequence of data symbols. Based on the code, a first data symbol of the sequence of data symbols is determined. The first data symbol is determined based at least in part on a first radix used to generate the code. Based on the code, a second data symbol of the sequence of data symbols is also determined. The second data symbol is determined based at least in part on a second radix and at least in part on the first data symbol.

Abstract: A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the “balance” of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used.

Abstract: Provided is a code conversion device that is capable of converting codes even if an input code sequence is invalid, and is able to reduce the amount of processing. When a first code sequence is input, the code conversion device generates a decoded signal by decoding the codes of normal frames of the first code sequence at Step S1, stores and holds the decoded signal at Step S2, generates a signal corresponding to an invalid frame by interpolation with the decoded signal that is stored and held, at Step S3. Subsequently, the code conversion device generates codes corresponding to the invalid frame by encoding the generated signal at Step S4, and makes the normal frames of the first code sequence without conversion be the frames of the second code sequence while making the generated codes be the frame of the second code sequence, in place of the codes of the invalid frame, at Step S5.

Abstract: The invention provides a method of encoding a binary data message for transmission over a data network. The method comprises allocating consecutive six bit sequences from the binary data message to consecutive respective bytes of an encoded data message; adding a predetermined bias value to some or all of the byte values of the encoded data message; and replacing respective selected data byte values in the encoded data message with one or more corresponding replacement data byte values. The invention further provides a method that comprises forming two or more message fragments from the binary message, each message fragment comprising respective bit sequences of the binary message; encoding each message fragment by the method outlined above to form two or more encoded message fragments; and adding a header to each encoded message fragment. The invention further provides an encoding engine for encoding a binary data message for transmission over a data network.

Abstract: A method and system allows for fast compression and decompressing of data using existing repetitive interleaved patterns within scientific data (floating point, integer, and image). An advantage of the method and system is that it is so fast that it can be used to save time due to a lower amount of data transferred/stored in scenarios like network transfer, disk or memory storage, cache storage or any other real-time applications where time plays a crucial role.

Abstract: A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals.

Abstract: An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry terminal, each of which receives data, performs an operation on the received data, and outputs a sum and a carry. A DBI determining unit determines a logic value of each of the data on the basis of the sum and the carry that are transmitted from the full adder, and generates a DBI signal.

Abstract: A data encoder-decoder which generates an encoded data element which can be stored in and retrieved from a reduced space memory element.

Abstract: A computer implemented method converts a data set of a first type to a data set type of a second type. The method includes casting up a first data set of a first type to a prescribed data set type that is large enough to encompass a data set of a second type. The method then includes casting down the casted up first data set from the prescribed data set type to the second data set of the second data set type.

Abstract: Embodiments of the invention generally provide methods, systems, and articles of manufacture for selecting a data bus inversion (DBI) mode of operation. A comparison circuit of a device may receive multiple packets of data to be transmitted to another device over a bus connecting the devices. The comparison circuit may compare the multiple packets of data and select a DBI mode of operation that conserves power and reduces noise on the bus.

Abstract: Method and apparatus are configured to assign a code of less than N number of bits in length to a pattern of bits of a first polarity value distributed within a block of N binary bits. The method basically comprises (1) determining a number of bits of the first value in the block of N binary bits; (2) selecting a base value based on the determined number of bits of the first value; (3) determining a displacement value representative of a particular distribution of the determined number of bits of the first value in the block of N binary bits; and (4) adding the base value and the displacement value to obtain a sum and using the sum to form an assigned code. The base value is preferably selected by evaluating an Expression Io=NC1+NC2+NC3 . . . +NCK?1, wherein K is the determined number of bits of the first value in the block of N binary bits.

Abstract: Multiple files a served using a server coupled to a data network. A plurality of files is determined, wherein a file includes an integer number of blocks, and wherein each block includes at least one input symbol. For each file, an indication of at least one channel on which to serve the file is determined, and, for each file, a rate at which to serve the file is determined. Also, a schedule for processing the blocks is determined, and output symbols for the blocks are generated according to the schedule. The output symbols are transmitted on the corresponding at least one channel, wherein the files are concurrently served at their corresponding rates.

Abstract: A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the “balance” of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used.

Abstract: A method and computing device is provided for converting between Chinese calendar dates and Julian day numbers in any specified date range using tables stored in the memory of the computing device containing the lengths of the months and which (if any) months are leap months, together with one or more reference pairs of Julian day numbers and Chinese date.

Abstract: A method and apparatus for reducing power consumption needed to refresh a memory may receive data having been encoded using data bus inversion (DBI), the DBI data having a first delta between a number of zeros for different cases between zero and a DBI maximum, balance code the DBI data to balance the number of zeros across the DBI data, and output data having a number of zeros for different cases between a minimum number greater than zero and less than or equal to the DBI maximum and a maximum number equal to the minimum number plus a second delta, the second delta being less than the first delta.

Abstract: A method, a component, a system, and a computer program for changing an encoding mode of an encoded data stream from a first encoding mode to a second encoding mode are disclosed. The encoded data stream at the first encoding mode is represented by first encoding parameters. For the encoding mode change the steps of selecting (20) a first set of the first encoding parameters to be used unchanged at the second encoding mode, selecting (30) a second set of the first encoding parameters, changing (40) the second set according to an algorithm being adapted to change the second set to match to the second encoding mode when combined with the first set, and combining (50) the first set and the changed second set for representing the encoded data stream by second encoding parameters at the second encoding mode are performed.

Abstract: Briefly, within a computer or digital data processing system, embodiments describe a method, article and apparatus for compressing data is described, which may be used for communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system, and/or for communicating between two or more computers or digital data processing systems via an interconnection medium such as a network.

Abstract: Embodiments described herein may include example embodiments of a method, article and/or apparatus for coding data which may be used for communicating between two or more components connected to an interconnection medium (e.g., a bus) within a single computer or digital data processing system, and/or for communication between computing platforms via a network or other interconnection medium.

Abstract: A data processing apparatus for processing a plurality of input signals to increase the number of bits thereof to disperse 0s and 1s therein and then converting the input signals into a serial signal. A signal generating unit generates including signal generating means for generating the serial signal having a second bit rate which is represented by the product of a first bit rate of the input signals, the number of the input signals, and a ratio of a bit length after the number of bits is increased to a bit length before the number of bits is increased.

Abstract: A character string processing apparatus converting a character string encoded by a first encoding method to a second encoding method selected from a plurality of encoding methods is disclosed. The character string processing apparatus includes an encoding method determination part that selects the encoding methods, obtains, with respect to each selected encoding method, at least one of the number information and the position information of one or more replacement codes at the time of converting the character string to the selected encoding method, and determines the second encoding method based on at least one of the number information and the position information.

Abstract: A data processing circuit comprises an encoder circuit for encoding a data word, wherein each digit may have any one of three or more digit values. The data word is encoded so that digit counts in the data word satisfy predetermined criteria (the digit counts are counts of the numbers of the digits in the encoded data word that assume respective digit values). The encoder defines at least two digit maps, each digit map defining assignments of each of the available digit values to a respective different output digit value. The encoder selects at least two groups of digits within the input data word. Each group is associated with a respective one of the digit maps, the groups being selected so that when each digit map has been applied selectively to the digits from its associated group, digit counts of the number of times respective digit values occur in the data word will satisfy predetermined criteria.

Abstract: An apparatus for generating a DBI signal in a semiconductor memory apparatus includes a data switching detection unit that detects whether or not previous data is consistent with current data and outputs a detection signal according to a detection result, and a DBI detection unit that outputs a DBI signal according to a difference in charge sharing level using the detection signal. Therefore, it is possible to minimize current consumption. Further, since there is no effect due to resistance skew of a transistor, an error in DBI signal generation and an error in data transfer accordingly can be prevented. Therefore, it is possible to improve the reliability of a system to which a semiconductor memory apparatus is applied.

Abstract: Under block-aware encoding, a bitmap represented by atoms comprises a series of bitmaps for each data block in a database. Each bitmap in the series is referred to herein as a block bitmap. Each block bitmap may have a different number of bytes or bits. Gaps are represented in atoms using a pair of numbers referred to as a gap code. A gap code includes a block-skip code and slot-skip code. A block-skip code represents how many block bitmaps to advance to reach a subsequent block bitmap; a slot-skip code represents how many bytes to advance within the block bitmap to reach a byte with at least one bit set. A gap code is represented by bit positions within a byte, with some bit positions allocated to represent the block-skip code and some to represent the slot-skip code. The allocation is adjusted dynamically during encoding and decoding.

Abstract: A data input/output circuit of a semiconductor memory device has a data inversion determination function. In an input mode, the data input/output circuit inverts an input data group in response to an input inversion flag and transmits the inverted input data group to a memory cell array. In an output mode, the data input/output circuit inverts a data group, output from the memory cell array, when the output data group satisfies a predetermined inversion condition, and transmits the inverted output data group to the outside of the data input/output circuit. In this case, an output inversion flag, indicating that the output data group is to be inverted, is generated. Further, the data input/output circuit stores the input inversion flag in the memory cell array in the input mode, and compares the input inversion flag, stored in the memory cell array, with the output inversion flag in the output mode.

Abstract: An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every two data bits. Two consecutive bits of data in the original non-return-to-zero (NRZ) data stream are grouped and are converted by an encoding circuit into two new consecutive data bits of the same duration as the original bits. The new encoded bits in each group will necessarily transition between two of three possible data states, and specifically will transition between ‘?1’ and ‘0’ logic states, or ‘+1’ and ‘0’ logic states. Pursuant to this encoding scheme, no more than two consecutive encoded bits will ever be of the same logic state, which prevents any particular data state from predominating and causing DC creep.

Abstract: A method includes receiving an original string of bits where each of the bits represents one of two possible logic levels. The string of bits also carries information. A new string is formed, based on the original string, which contains all of the information of the original string by using fewer bits of one of the logic levels.

Abstract: A method for coding a sequence of data bits (B1-B5), at least one of said bits having a logical on value or a logical off value. The data bits are organized in a sequence of time slot frames (Fr1-FR5). At least one time slot frame has a plurality of time slots (ZS11-ZS13). Each of the plurality of times slots are capable of having an on value or an off value (Z1 or Z0). The coding comprises preloading a time slot (ZS14, AF) from the plurality of time slots with an off value (Z0). Each of the time slots (ZS11-ZS13) other than the preloaded time slot (ZS14) are loaded with an on value or an off value to form a logical on value or logical off value for the at least one of said data bits. A time slot with an off value from the plurality of time slots always follows another time slot with an on value from the plurality of time slots. The logical on value is complementary to the logical off value.

Abstract: An interface circuit capable of controlling a noise margin and a time margin for producing an output a binary data is realized. The circuit comprises a detecting unit for detecting a transition state of logic levels in received binary data corresponding to preceding two clock signals, an output signal producing unit for producing an output binary data based on the received binary data by using a reference voltage and by latching the binary data using the clock signal, a reference voltage control unit for controlling the reference voltage, and a clock phase control unit for controlling a phase of the clock signal. The noise margin can be controlled by changing the reference voltage in accordance with the detected transition state, and the time margin can be controlled by changing the clock phase in accordance with the detected transition state.

Abstract: In a network having transaction acceleration, for an accelerated transaction, a client directs a request to a client-side transaction handler that forwards the request to a server-side transaction handler, which in turn provides the request, or a representation thereof, to a server for responding to the request. The server sends the response to the server-side transaction handler, which forwards the response to the client-side transaction handler, which in turn provides the response to the client. Transactions are accelerated by the transaction handlers by storing segments of data used in the transactions in persistent segment storage accessible to the server-side transaction handler and in persistent segment storage accessible to the client-side transaction handler.

Abstract: The invention can be used to play back an audiovisual or audio document received in a first encoding format within a local area network. A first device plays back the document in the received format, then a user decides to play back the document on a device having a second encoding format. Playback is first stopped on the first device and the document is stored. The user starts playing back the document on the second device at the moment at which playback of it was stopped on the first device. Depending on the decoding means of the second device, the document is transcoded from the first encoding format to the second encoding format. The invention also relates to a management device for issuing storage and transcoding requests so that a document played back from a first device can be transferred to a second device regardless of the capabilities for playing back encoded documents on the first and second devices.

Abstract: A denoising process statistically processes a series of frames of a motion picture to construct respective data structures for the frames. Each data structure indicates for each of multiple contexts, occurrences of symbols that have the same context and are in the corresponding one of the frames. The data structures for multiple frames are combined to construct an enhanced data structure for one of the frames, and symbols in that frame are replaced with values determined using the enhanced data structure.

Abstract: A method is disclosed that enables the transmission of a digital message along with a corresponding media information signal, such as audio or video. A telecommunications device that is processing the information signal from its user, such as a speech signal, encodes the information signal by using a model-based compression coder. One such device is a telecommunications endpoint. Then, based on an evaluation of the perceptual significance of each encoded bit, or on some other meaningful characteristic of the signal, the endpoint's processor: (i) determines which encoded bits can be overwritten; and (ii) intersperses the digital message bits throughout the encoded signal in place of the overwritten bits. The endpoint then transmits those digital message bits as part of the encoded information signal. In this way, no additional bits are appended to the packet to be transmitted, thereby addressing the issue of compatibility with existing protocols and firewalls.

Abstract: A coding/decoding system and method are disclosed. Coding, as used herein, refers assigning values to cells. Information to be coded is processed stepwise in information pieces, with bitwise processing (single information bits as information pieces) as a special case. According to an illustrative embodiment, bitwise coding/decoding is disclosed. A predefined structure called a configuration is known to both the coding and decoding systems. The configuration includes a step configuration for each coding step. A step configuration is: 1) a distinction of two subsets of cells, one called inversion cells, the other called non inversion cells; 2) an assignment of at least one cell tuple consisting of at least one inversion cell and one non inversion cell each, where, for these tuples, for any preceding step configuration the tuple cells are either all inversion cells or all non inversion cells. For coding, in each step, its inversion cells are XORed with the information bit.

Abstract: A method of generating a codebook for a multiple-input multiple-output (MIMO) system is provided. The codebook generation method includes: assigning a single-polarized preceding matrix to diagonal blocks among a plurality of blocks arranged in a block diagonal format in which a number of diagonal blocks corresponds to a number of polarization directions of transmitting antennas; and assigning a zero matrix to remaining blocks excluding the diagonal blocks.

Abstract: Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

Abstract: An apparatus for generating a DBI signal in a semiconductor memory apparatus includes a data switching detection unit that detects whether or not previous data is consistent with current data and outputs a detection signal according to a detection result, and a DBI detection unit that outputs a DBI signal according to a difference in charge sharing level using the detection signal. Therefore, it is possible to minimize current consumption. Further, since there is no effect due to resistance skew of a transistor, an error in DBI signal generation and an error in data transfer accordingly can be prevented. Therefore, it is possible to improve the reliability of a system to which a semiconductor memory apparatus is applied.

Abstract: A general-purpose processor expands and transmits to a volatile memory compressed program data and compressed parameter data stored in a nonvolatile memory. The DSP processor reads the expanded program data and the expanded parameter data into a program memory and the data memory of the DSP processor, respectively, and then, decodes compressed digital data or encodes expanded digital data.

Abstract: A system and method for encrypting and/or compressing an input data string is disclosed. The input data string is divided into a plurality of blocks of data that each contains a plurality of bits of data. A block code is used to identify the size of each of the blocks of data. The blocks of data are analyzed to determine how frequently different groups of bits of data are present within each block of data. The blocks of data are also analyzed to determine whether certain relationships among the groups of bits of data exist within the blocks of data. After the blocks of data are analyzed, and in response to the analyses, a control code is generated for each block of data through the use of a control code index. After the control code for each block of data is generated, a position code is also generated for each block of data in response to the control code for the corresponding block of data.

Abstract: A method and system for transmitting binary-coded data use partitioning of data words in a plurality of data nibbles. The data nibbles are coded using modified a 1-bit hot coding format that transforms a data nibble in a data segment including a plurality of bit groups. A change in a digital state at a bit position in a more significant bit group is maintained at that bit position in less significant bit groups, and information is transmitted in a form of a transition between digital states. The data segments are transmitted in phases each including one bit group from each data segment. At a receiving terminal, the bit groups are converted back in the binary-coded data words. In one application, the invention is used to reduce power consumption during data transmissions to and from an integrated circuit device.

Abstract: A method of converting m-bit information words to a run-length constrained modulated signal includes converting the information words into n-bit code words. The available code words are distributed over at least one group (G1) of a first type and at least one group (G2) of a second type. The selection of a code word belonging to the group of the first or second type establishes a coding state of the first type (S1) or one of a number r of coding states (S2, S3) of the second type, depending on the current information word. For each information word, a subset of code words is available, this subset having at least one disjunct code word for each of the r coding states. The selection from the subset of the code word to be delivered is based the coding state, on dynamically verifying the run-length constraint for the sequence of code words, and on an additional criterion, like the low frequency content of the modulated signal.

Abstract: N binary signals are transmitted through a bus of m leads, where m<n, at the rhythm of a train of clock pulses by encoding a first signal on a second signal. The encoding provides for the information associated with the first signal to be included in the second signal within a predetermined time interval of the clock period preceding each reading clock pulse. In this way one obtains a reduction of the switching activity on the bus and therefore a reduction of the energy consumption.

Abstract: We describe a voltage level coding system and method. The voltage level coding system includes a level encoder having an input to receive data segments coded using a first code and an output to supply second data codes indicating one of 2N plus at least one additional voltage level to which each data segment is assigned. A converter converts the second data codes into such voltage levels. A controller output supplies the voltage levels. A method for coding digital data includes determining a first data transition, generating a code that includes at least one additional level that minimizes data skew in the first data transition, and coding the first data transition with the additional level in the code.

Abstract: A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.

Abstract: In the case of a method and a device for transmitting data units by way of a transmission medium that comprises at least three adjacent transmission lines, first of all a plurality of codes is supplied. Each code has a number of code sections that corresponds to the number of transmission lines of the transmission medium. Each code section has on an associated transmission line a predetermined signal value, the sum of the signal values for each transmitted code being substantially constant. For each data unit to be transmitted, a code is selected from the plurality of codes, and the selected code is supplied for transmission by way of the transmission medium. The data units and the codes to be transmitted can be supplied in accordance with a predetermined clock pulse, a new code being selected at each new clock pulse, based on the preceding code and the new data unit.

Abstract: A data encoding apparatus extracts valid data to be encoded from received data and encodes the data, and realigns the encoded data in units of a predetermined data width and outputs the data having each unit of the predetermined data width. A data decoding apparatus extracts valid data to be decoded from received data and realigns the decoded data in units of a predetermined data width and outputs the data having each unit of the predetermined data width.

Abstract: Method and system for representing a strong of alpha characters, numeral characters and/or delimiters that allows uniform searching procedures, whether or not numerals and/or delimiters are present in the string. Numerical sub strings, containing only numerals and delimiters, are re characterized in binary format and are separated from, and later recombined with, sub strings containing only alpha characters and delimiters, to provide a modified searchable string in binary format Floating point numbers are easily handled in this approach. Delimiters may be any subset of ASCII characters, as distinguished from numerals and from alpha characters. A numeral character, to be transmitted as a sequence of bits, is optimized by expression in a base (power of 2) requiring the smallest bit count.

Abstract: A computer implemented method of encoding and decoding a data file. The method of encoding includes assigning a context to the data file; and encoding the data file using an encoding method associated with the context. The method of decoding includes reading a context assigned to a data file; and decoding the data file using a decoding method associated with the context. More efficient use of limited encoding representations result.

Abstract: According to some embodiments, a bit stuffing method is provided for fax and other data communication.

Abstract: An encoding and decoding apparatus is provided. In a coding process, a relation between a matching length and a matching-length code is dynamically changed in order to independently switch the matching length that can be expressed by the matching-length code from one value to another. By using a slide window in a data buffer as a dictionary, a character-string searching section searches for a state of matching a character sub-string in input data. A matching-length extension table is used for storing relations between matching lengths and matching-length codes as relations dependent on an internal state stored in an internal-state holding section. A matching-length coding section refers to the matching-length extension table in order to dynamically determine a relation between a matching length and a matching-length code as a relation dependent on an internal state.

Abstract: An improved manifold array (ManArray) architecture addresses the problem of configurable application-spacific instruction set optimization and instruction memory reduction using an instruction abbreviation process thereby further optimizing the general ManArray architecture for application to high-volume and portablke battery-powered type of products. In the ManArray abbreviation process a standard 32-bit ManArray instruction is reduced to a smaller length instruction format, such as 14-bits. An application is first programmed using the full ManArray instruction set using the native 32-bit instructions. After the application program is completed and verified, an instruction-abbreviation tool analyzes the 32-bit application program and generates the abbreviated program using the abbreviated instructions. This instruction abbreviation process allows different program-reduction optimizations tailored for each application program. This process develops an optimized instruction set for the intended application.