Abstract: A method for decoding encoded data. The method includes receiving data encoded by replacing each of a plurality of characters with bit strings. The method also includes recording, on the basis of definition information, at least one of the characters as corresponding to each of the bit lengths, and generating decode information based on the number of characters, wherein the decode information includes bit string information for sorting the bit strings in a bit length order that is a predetermined order associated with bit lengths. The method also includes, in response to receiving a particular bit length, generating character information in which the characters are sorted in the bit length order by inserting a character corresponding to the particular bit length into a position corresponding to the particular bit length in an array in which at least one of the bit lengths.

Abstract: In a data encoding process: data is encoded by using unit bit series obtained from an encoding bit series; the encoding bit series is searched for a first bit series identical to a portion of the encoded data; the portion is substituted with a second bit series which includes a leading code indicating a leading position of a substitution range and position information indicating the position of the first bit series in the encoding bit series. In a data decoding process: the position information is detected from the substitution range in received data after the leading code is detected in the data; a substitution bit series is extracted from the position in the encoding bit series indicated by the position information; and the data in the substitution range is substituted with the substitution bit series so as to restore the encoded data.

Abstract: An encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on output nodes. The encoder selects a current codeword from a group of codewords in a codespace which does not overlap the other group of codewords, i.e., codewords in a given group of codewords are not included in any other group of codewords in the codespace. This property allows a receiver of the codewords to be simplified. In particular, a mathematical operation performed on symbols in the current codeword uniquely specifies the corresponding group of codewords. This allows a decoder to decode the current codeword using comparisons of symbols received on a subset of all possible combinations of node pairs.

Abstract: A method for decoding a message is disclosed. The method is used for an electronic system for displaying messages. The method comprises the following steps: a processing module decoding an un-decoded string of a message received from a message transferring terminal, acquiring a first word group and saving the first word group to a word group handling buffer, and recording a repetition value of the first word group; the processing module decoding an un-decoded string of a message received from the message transferring terminal, acquiring a second word group from the un-decoded string, and saving the second word group to a word group decoding buffer; the processing module comparing the first word group and the second word group to determine whether the first word group and the second word group are the same; and if yes, increasing the repetition value of the first word group.

Abstract: Multiple files a served using a server coupled to a data network. A plurality of files is determined, wherein a file includes an integer number of blocks, and wherein each block includes at least one input symbol. For each file, an indication of at least one channel on which to serve the file is determined, and, for each file, a rate at which to serve the file is determined. Also, a schedule for processing the blocks is determined, and output symbols for the blocks are generated according to the schedule. The output symbols are transmitted on the corresponding at least one channel, wherein the files are concurrently served at their corresponding rates.

Abstract: For context based compression techniques, for example Context Based YK compression, a method and system for grouping contexts from a given context model together to create a new context model that has fewer contexts, but retains acceptable compression gains compared to the context model with more contexts is provided. According to an exemplary embodiment a set of files that are correlated to the file to be compressed (hereafter called training files) are read to determine, for an initial context model, the empirical statistics of contexts and symbols. In some embodiments, this includes determining the estimated joint and conditional probabilities of the various contexts and symbols (or blocks of symbols). The initial context model is then reduced to a desired number of contexts, for example, by applying a grouping function g to the original set of contexts to obtain a new and smaller set of contexts.

Abstract: In one embodiment, a method of converting an uncompressed bitstream into a compressed bitstream for a programmable logic device (PLD) is disclosed. The method includes embedding a first data frame from the uncompressed bitstream into the compressed bitstream, wherein the first data frame comprises a first data set; embedding a first instruction into the compressed bitstream to load the first data frame into a first row of configuration memory of the PLD at an address associated with the first data frame; identifying a second data frame in the uncompressed bitstream, wherein the second data frame comprises the first data set; and embedding a second instruction into the compressed bitstream to load the first data frame into a second row of the configuration memory at an address associated with the second data frame.

Abstract: A display device with reduced power consumption has pixels coupled with data lines and arranged in a matrix, a signal controller processing input image signals and outputting output image signals, and a data driver applying data voltages, corresponding to output image signals, to the data lines. When all the input image signals have either a first or second value, the output image signals have the first value. The signal controller generates a polarity signal for determining data voltage polarity, and when all the input image signals have either a first or second value, data voltages corresponding to the input image signals have a polarity equivalent to a polarity of previously applied data voltages. The signal controller generates a control signal for controlling the data driver's clock synchronization circuit, and the control signal halts the clock synchronization circuit when an operating frequency is lower than a predetermined value.

Abstract: An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.

Abstract: A bit stream is received and each bit corresponding to the bit stream is over-sampled to generate a first set of data samples. Each data sample from the first set of data samples is compared with a corresponding immediate previous data sample to generate a second set of data samples. The second set of data samples is compared with bit masks, and accordingly, some of the data samples in the first set of data samples are identified for replacement. Further, a substitute data sample is selected from the first set of data samples based on a predefined criterion and some of the data samples in the first set of data samples are replaced with the substitute data sample.

Abstract: The present encoding method encodes binary data as sequences of code points occupying the Private Use Area of the Unicode Basic Multilingual Plane. The encoded data can be contained within a stream of UTF-8, UTF-16 or UTF-32 code units and subsequently decoded to yield the original binary data. This method requires minimal processing for both encoding and decoding operations, and yields a 75% storage efficiency limit. Each datum encoding sequence includes type and encoding length information, enhancing parse and search operation performance. The type system includes elements for creating complex structured data-text sequences, and a mechanism for application defined extensions.

Abstract: A serializer device is used for generation, from a parallel digital signal, of a clock signal or a serial binary data signal having a pre-determined amount of jitter. A binary number having consecutive groups of ones and zeroes, when serialized by the serializer device, produces a clock signal. By varying the number of ones and zeroes on the binary number, a pre-determined amount of jitter can be generated. Use of sigma-delta modulation in combination with a phase-locked loop circuitry allows one to obtain a smoothly varying jitter of the output signal.

Abstract: A character data set is compressed with a compression algorithm module of a computer system to generate one or more streams of encoded values. The compression module is configured to compress the character data set with an entropy encoder to generate one or more streams of encoded values with UTF-8 or UTF-16. A code points mapper assigns the encoded values to code points in a Unicode format. A UTF encoder encodes the streams of assigned encoded values.

Abstract: In a data encoding process: data is encoded by using unit bit series obtained from an encoding bit series; the encoding bit series is searched for a first bit series identical to a portion of the encoded data; the portion is substituted with a second bit series which includes a leading code indicating a leading position of a substitution range and position information indicating the position of the first bit series in the encoding bit series. In a data decoding process: the position information is detected from the substitution range in received data after the leading code is detected in the data; a substitution bit series is extracted from the position in the encoding bit series indicated by the position information; and the data in the substitution range is substituted with the substitution bit series so as to restore the encoded data.

Abstract: Provided is an information processing apparatus including a distributor that distributes input data in units of M bits and generates N M-bit bit sequences, an encoder that converts each of the N bit sequences distributed by the distributor into a binary symbol sequence of K symbols and generates N binary symbol sequences, a signal generator that generates N transmission signals Sj synchronized with a specific symbol clock and having, as an amplitude value, each symbol value included in the N binary symbol sequences, a signal delay unit that delays, with regard to j, the transmission signals Sj generated by the signal generator by a (j?1)/N-symbol period and generates delay signals Rj, a signal addition unit that adds the delay signals Rj generated by the signal delay unit and generates an added signal, and a signal transmitter that transmits the added signal generated by the signal addition unit.

Abstract: An encoder/decoder architecture including an arithmetic encoder that encodes the MSB portions of a Factorial Pulse Coder output, and that encodes an output of a first-level source encoder, e.g., MDCT. Sub-parts (e.g., frequency bands) of portions (e.g., frames) of the signal are sorted in increasing order based on a measure related to signal energy (e.g., signal energy itself). In a system that overlays Arithmetic Encoding on Factorial Pulse coding, the result is bits re-allocated to bands with higher signal energy content, yielding higher signal quality and higher bit utilization efficiency.

Abstract: A method and system allows for fast compression and decompressing of data using existing repetitive interleaved patterns within scientific data (floating point, integer, and image). An advantage of the method and system is that it is so fast that it can be used to save time due to a lower amount of data transferred/stored in scenarios like network transfer, disk or memory storage, cache storage or any other real-time applications where time plays a crucial role.

Abstract: Various techniques are provided to compress and decompress configuration data for use with programmable logic devices (PLDs). In one example, a method includes embedding a first data frame comprising a data set from an uncompressed bitstream into a compressed bitstream. The method also includes embedding a first instruction to instruct a PLD to load the first data frame into a data shift register, embedding a second instruction to instruct the PLD to load a first address associated with the first data frame into an address shift register, and embedding a third instruction to instruct the PLD to load the first data frame from the data shift register into a first row of a configuration memory corresponding to the first address. The method further includes identifying a second data frame comprising the data set in the uncompressed bitstream, and embedding fourth and fifth instructions in place of the second data frame.

Abstract: Class-D amplifiers have evolved from using binary pulse-width modulation (PWM) modulators to three-level PWM modulators. Three-level PWM drivers for audio applications offer the benefits of eliminating costly elements at the output of an audio system. However, they also introduce increased common-mode interference. Three-level PWM generates three states, but one state has two interchangeable representations which can be scrambled in order to shape the common-mode output spectrum.

Abstract: A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.

Abstract: A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals.

Abstract: A system and method for increasing transmission distance and/or transmission data rates using tedons and an encoding scheme to reduce the number of ones in a data signal is described. For example, the method for increasing transmission distance and transmission data rate of a fiber optical communications link using tedons includes the steps of encoding a data signal to be transmitted using an encoding scheme that reduces a number of ones in the data signal, transmitting the encoded data signal over the fiber optical communications link, receiving the encoded data signal and decoding the encoded data signal.

Abstract: A data encoding method is provided. The data has several bytes, and each byte has n bits. The data encoding method includes the following steps. First, a specific value is defined. Next, the data is divided into one or several data blocks each having m bytes, wherein m?2n?2. Following that, a replacing value, not appearing in the m bytes of the data block, is obtained from each data block respectively, wherein the replacing value is not equal to the specific value. Then, the values of the bytes being the specific value are replaced to the replacing value in the m bytes of each data bock respectively. Afterwards, a starting byte is allocated at the start of each data block, and the replacing value is stored to the starting byte so as to obtain the data block being encoded respectively. Each data block being encoded has m+1 bytes.

Abstract: A method for converting data received in either a Level A or Level B SMPTE 425M compliant format into either a Level B or a Level A compliant format, respectively, includes receiving and processing data in one of a Level A or a Level B SMPTE 425M compliant format. Inputting the received Level A formatted data into a storage device and reading out Level B formatted data at an output of the storage device, or inputting Level B formatted data into the storage device and reading out Level A formatted data at an output of the storage device. Back-end circuitry further processes the Level A formatted data when Level B formatted data is received or further processes the Level B formatted data when Level A formatted data is received. The storage device is operated as a line multiplexer to convert data in a Level B format to data in a Level A format and is operated as a line demultiplexer to convert data in a Level A format to data in a Level B format.

Abstract: The present invention provides coding/decoding a digital signal, in particular using a transform with overlap employing weighting windows. In the invention, two consecutive and equal-size blocks of samples of the signal may be weighted by respective different successive windows. These two windows may be chosen independently of each other according to a criterion specific to the characteristics of the signal (entropy, data rate/distortion, etc.) that are determined for each of the two blocks.

Abstract: A method of processing an encoded data stream comprises determining one or more data strings of interest; wherein the data string comprises a predetermined sequence of characters; encoding (3) the or each data string using the same encoding that was used to encode to the data stream; and searching (4) for the encoded data string in the encoded data stream.

Abstract: Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.

Abstract: A transmitter using a method of block code-based group modulation includes a grouping unit, a generating unit, and a mapping unit. The grouping unit generates symbols by grouping a data bit stream into N-bit groups, and the generating unit generates a codeword set composed of codewords corresponding to combinations of arrangements of pulses that are generated by a result of grouping to a predetermined number. Next, the mapping unit block-maps a codeword selected from the codeword set to groups constituting the symbols.

Abstract: In an apparatus and method of transforming a block of data elements, the order of the data elements is transformed. The data elements are stored in an initial order in respective ones of first and second memory elements, each first memory element corresponding to a respective second memory element. The contents of all respective pairs of the first and second memory elements are compared. The data elements in the second memory elements are shifted to different ones of the second memory elements after each comparison while maintaining the initial order of the data elements. The shifts and comparisons are repeated until every data element has been compared with every other data element. The results of the comparisons are combined after each comparison to provide a result that can be used to order the data elements to a final order.

Abstract: Methods or sub-component method step/s necessary for lossless data compressions of input binary (or adaptable for even N-ary) data file, or for compression/representation of sequential list of positive integers (or offsetted to all be positive integers >0, which may be a sequential list of variable length binary base positive integer digit numbers or even N-ary base positive integer digit numbers) are described, providing many magnitudes orders improvements over existing state-of-art best available methods such as Rice-Coulomb encodings/RunLength based/LZW encodings . . . etc. The methods or sub-component method step/s further makes possible or forms the basis/sub-component method step/s for ‘infinite data compressions’ algorithms to be adapted designed implemented.

Abstract: A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the “balance” of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used.

Abstract: Coding efficiently in non-power-of-two ranges. Coding is performed in an N-bit system, where certain codes are represented with N bits and other codes are represented with (N+1) bits. An example is where the other codes may have an N-bit representation used to represent multiple values, with the additional bit being disambiguation information provided to distinguish the codes having multiple values. Thus, N bits are used to represent most codes, and an extra bit is used to represent other codes. The number of bits per element used for representing a sequence is, on average, close to a theoretical minimum for N-bits.

Abstract: The invention relates to a method for converting a voltage identification code includes the steps as follows. A special binary code range is obtained, and N special voltage identification codes corresponding to a special command are converted to N special binary codes under a converting relation, and the N special binary codes are used as the special binary code range. A first voltage identification code is converted to a corresponding first binary code under the converting relation. In addition, the first binary code and a first preset value are used to compute to obtain a second binary code, and the second binary code is not in the special binary code range.

Abstract: A data encoding method is provided. The data has several bytes, and each byte has n bits. The data encoding method includes the following steps. First, a specific value is defined. Next, the data is divided into one or several data blocks each having m bytes, wherein m?2n?2. Following that, a replacing value, not appearing in the m bytes of the data block, is obtained from each data block respectively, wherein the replacing value is not equal to the specific value. Then, the values of the bytes being the specific value are replaced to the replacing value in the m bytes of each data bock respectively. Afterwards, a starting byte is allocated at the start of each data block, and the replacing value is stored to the starting byte so as to obtain the data block being encoded respectively. Each data block being encoded has m+1 bytes.

Abstract: An image encoding and decoding scheme operable according two different modes depending on properties of the processed image is disclosed. In the encoding, an image is decomposed into image blocks (600) comprising image elements (610). The blocks (600) are compressed into block representations (700A, 700B) according to one of two compression modes. A block representation (700A; 700B) comprises two codewords (720A, 730A; 720B, 730B) representing properties of the image elements (610) in the block (600) and a sequence (740A; 740B) of image element associated indices indicative of one of the codewords (720B, 730B) or a property representation generated based on a codeword (730A). The block representation (700A; 700B) also includes a mode index representing the mode, according to which the block representation (700A; 700B) was compressed. This mode index can be provided before, during or after generation of the codewords (720A, 730A; 720B, 730B) and index sequence (740A; 740B).

Abstract: Provided is a code conversion device that is capable of converting codes even if an input code sequence is invalid, and is able to reduce the amount of processing. When a first code sequence is input, the code conversion device generates a decoded signal by decoding the codes of normal frames of the first code sequence at Step S1, stores and holds the decoded signal at Step S2, generates a signal corresponding to an invalid frame by interpolation with the decoded signal that is stored and held, at Step S3. Subsequently, the code conversion device generates codes corresponding to the invalid frame by encoding the generated signal at Step S4, and makes the normal frames of the first code sequence without conversion be the frames of the second code sequence while making the generated codes be the frame of the second code sequence, in place of the codes of the invalid frame, at Step S5.

Abstract: The invention provides a method and system for reducing redundant data blocks. The method includes encoding a first data block having a first length into a bitstream having a second length, transmitting the bitstream to a server device, and reducing redundant data blocks by decoding the first data block from a first plurality of data blocks and the bitstream where each block in the first plurality of data blocks has a length equal to the first length.

Abstract: A system including a serializer/deserializer (SERDES) block including a first SERDES lane, a second SERDES lane, a third SERDES lane, and a fourth SERDES lane; a physical coding sublayer (PCS) block including a layout select tag, a first PCS lane connected to the fourth SERDES lane, a second PCS lane connected to the third SERDES lane, a third PCS lane connected to the second SERDES lane, and a fourth PCS lane connected to the first SERDES lane; and a media access control (MAC) layer block including a first plurality of pins connected to the first PCS lane, a second plurality of pins connected to the second PCS lane, a third plurality of pins connected to the third PCS lane, and a fourth plurality of pins connected to the fourth PCS lane, wherein the PCS block is configured to map the first SERDES lane to the first plurality of pins, the second SERDES lane to the second plurality of pins, the third SERDES lane to the third plurality of pins, and the fourth SERDES lane to the fourth plurality of pins based on

Abstract: A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the “balance” of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used.

Abstract: An apparatus for transmitting data signals includes a logic unit configured to generate an encoded clock signal in response to a clock signal and a first data signal, and a demultiplexer configured to receive the encoded signal, the first data signal, and a second data signal, and to output odd-numbered data signals of the received signals at a first edge of the clock signal and even-numbered data signals of the received signals at a second edge of the clock signal. A data state elimination block is configured to receive the signals and to invert one of the received signals if logic levels of the signals are the same.

Abstract: A computerized system for representing a digital media using both a bit stream and an associated metadata includes a codec configured to encode the digital media to the bit stream. The codec is further configured to generate a metadata representation stream of the bit stream that encapsulates information embedded in the bit stream and at least one type of media-related information. The system also includes a manager configured to assure synchronization between the bit stream and the metadata representation stream during streaming of the bit stream and the metadata representation stream.

Abstract: A method for conversion between a decimal floating-point number and an order-preserving format has been disclosed. The method encodes numbers in the decimal floating-point format into a format which preserves value ordering. This encoding allows for fast and direct string comparison of two values. Such an encoding provides normalized representations for decimal floating-point numbers and supports type-insensitive comparisons. Type-insensitive comparisons are often used in database management systems, where the data type is not specified for values to compare. In addition, the original decimal floating-point format can be recovered from the order-preserving format.

Abstract: A method and system for converting a digital code. A digital signal is encoded to have a digital code having multiple binary bits. Substantially one half of the binary bits of the digital code is inverted to produce a modified digital code to reduce digital noise associated with the digital code.

Abstract: A method for decompressing a stream of a compressed data packet includes determining whether first data of a data-dictionary for a first decompression copy operation is located in a history buffer on a remote memory or a local memory, and when it is determined that the first data is located in the remote memory, stalling the first decompression copy operation, performing a second decompression operation using second data that is located in the history buffer on the local memory and fetching the first data from the remote memory to the history buffer on the local memory. The method further includes performing the first decompression operation using the first data in the history buffer on the local memory.

Abstract: A method and an apparatus for bus encoding and a method and an apparatus for bus decoding are provided. The methods and apparatuses for bus encoding/decoding use a discontinuous pattern table (DPT) to store discontinuous pattern pairs. The tables are kept synchronous in both transmitter and receiver ends. After transmitting the first data in a discontinuous pattern pair, the second data may be transmitted by merely informing the receiver end through a control line instead of transmitting the second data by the bus.

Abstract: A method and system allows for fast compression and decompressing of data using existing repetitive interleaved patterns within scientific data (floating point, integer, and image). An advantage of the method and system is that it is so fast that it can be used to save time due to a lower amount of data transferred/stored in scenarios like network transfer, disk or memory storage, cache storage or any other real-time applications where time plays a crucial role.

Abstract: A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals.

Abstract: Techniques for encoding and decoding non-repeating data objects are described herein. According to one embodiment, an input stream having non-repeating literals is received to be encoded into an output stream having a preamble and a payload, where each of the non-repeating literal is encoded via a unique data value, a lowest value among data values representing the literals to be encoded and a literal count representing a number of literals to be encoded are identified. A bit count representing a number of bits required to encode each of the literals is determined. The lowest value, the literal count, and the bit count are emitted into a preamble of an output stream. For each literal of the input stream, a code value representing a predetermined relationship between the data value associated with each literal and the identified lowest value is emitted to the payload of the output stream.

Abstract: A system and method for increasing transmission distance and/or transmission data rates using tedons and an encoding scheme to reduce the number of ones in a data signal is described. For example, the method for increasing transmission distance and transmission data rate of a fiber optical communications link using tedons includes the steps of encoding a data signal to be transmitted using an encoding scheme that reduces a number of ones in the data signal, transmitting the encoded data signal over the fiber optical communications link, receiving the encoded data signal and decoding the encoded data signal.

Abstract: An apparatus for generating a DBI signal in a semiconductor memory apparatus includes a data switching detection unit that detects whether or not previous data is consistent with current data and outputs a detection signal according to a detection result, and a DBI detection unit that outputs a DBI signal according to a difference in charge sharing level using the detection signal. Therefore, it is possible to minimize current consumption. Further, since there is no effect due to resistance skew of a transistor, an error in DBI signal generation and an error in data transfer accordingly can be prevented. Therefore, it is possible to improve the reliability of a system to which a semiconductor memory apparatus is applied.