Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for machine translation using neural networks. In some implementations, a text in one language is translated into a second language using a neural network model. The model can include an encoder neural network comprising a plurality of bidirectional recurrent neural network layers. The encoding vectors are processed using a multi-headed attention module configured to generate multiple attention context vectors for each encoding vector. A decoder neural network generates a sequence of decoder output vectors using the attention context vectors. The decoder output vectors can represent distributions over various language elements of the second language, allowing a translation of the text into the second language to be determined based on the sequence of decoder output vectors.

Abstract: Provided is a device and method for encoding and decoding to implement maximum transition avoidance coding with minimum overhead. An exemplary device performs encoding and/or decoding, by using sub-block lookup tables representing correlations between some bit values in a data burst and symbols, a combining lookup table selectively interconnecting the sub-block lookup tables based on remaining bit values of the data burst, and a codeword decoding lookup table designating the sub-block lookup tables corresponding to the symbols of each of received codewords.

Abstract: A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.

Abstract: A first physical layer coding data block flow and a second physical layer coding data block flow are received. A first data flow is obtained according to the first physical layer coding data block flow and the second physical layer coding data block flow. Multiple subframe headers are generated. A second data flow is obtained according to the first data flow and the multiple subframe headers. Data blocks in the second data flow are distributed to a first physical medium dependent (PMD) sublayer circuit and to a second PMD sublayer circuit to obtain a first PMD sublayer data flow and a second PMD sublayer data flow.

Abstract: A method of compressing a frame in an image compression and storage system includes mapping an original sample to a mapped sample based on a bit depth of the original sample and a maximum allowed error, to ensure low reconstruction error for a high priority sample value, determining a residue of the mapped sample based on a mapped previous reconstructed sample, applying a modulo addition to the residue to generate a biased residue, quantizing the biased residue based on the maximum allowed error to generate a quantized biased residue, and encoding a value corresponding to the quantized biased residue to generate an encoded value.

Abstract: According to one aspect of the invention, there is provided a signal processing method, wherein a frame is generated in which at least one position of occurrence of a transition in a pulse value is determined from an input bitstream. According to another aspect of the invention, there is provided a signal processing method, wherein a frame including at least one pulse having a pulse width not less than a minimum pulse width is generated from an input bitstream.

Abstract: An apparatus is provided for generating a transmission wave. The apparatus includes a plurality of antennas and a plurality of signal generators. The plurality of antennas has polarization diversity. The plurality of signal generators are each coupled to one of the antennas and configured to generate a continuous twisted wave by driving each of the antennas using independent, coordinated, and distinct sinusoidal waves, and having a twist frequency and a carrier frequency, the twist frequency lower than the carrier frequency. A method is also provided.

Abstract: Systems and methods for dynamically encoding and decoding binary numbers using linear-time algorithms that encode and decode Hamming Distance-Based representations for the binary numbers are described. The binary numbers may correspond with integer values, such as 64-bit, 128-bit, or 256-bit integer values. In some cases, in response to detecting that a binary number is to be stored using a particular type of memory (e.g., a phase change memory), the binary number may first be encoded using a Hamming Distance-Based representation and then the encoded data may be written to the particular type of memory. The binary number may be encoded by generating a binary string or a binary array representing the binary number such that if one bit flips within the binary string or the binary array, the maximum distortion in the number is less than a threshold amount (e.g., less than 256).

Abstract: A referenceless frequency acquisition scheme locks to an unknown data frequency by feedback of sampled data to a digitally controlled oscillator (DCO). A received data signal is converted to deserialized outputs, then by a phase detector to symbol streams of phase updates. Each symbol stream is converted to a lower rate sum, for which absolute values are computed and periodically summed. Absolute value sums are obtained for each frequency over a range of test frequencies to obtain totals, each corresponding to a different test frequency. A critical value is determined from among the totals. The DCO is set to the test frequency corresponding to the critical value as a coarse approximation for the unknown frequency.

Abstract: A device and a method for an improved compacting of compressed and uncompressed data blocks into an output buffer are provided. The device is configured to obtain a set of input data blocks comprising at least one of a compressed data block and an uncompressed data block; compact the compressed data blocks into the output buffer, starting from a first predefined region in the output buffer, such that the compressed data blocks are sequentially compacted; and compact the uncompressed data blocks into the output buffer, starting from a second predefined region in the output buffer, such that the uncompressed data blocks are sequentially compacted.

Abstract: The present invention relates to an encoding apparatus for multi-level signaling, the encoding apparatus including: a candidate pattern generator (1) generating a set of candidate patterns from input data by using symbol-based inversion; a controller (2) generating a cumulated disparity value that is a result of calculating disparity indicating a degree to which transmission data up to previous transmission deviates from DC balance, storing the cumulated disparity value, and determining a transmission control code by using the cumulated disparity value and a set of disparity values that is a result of calculating disparity indicating a degree to which each of the candidate patterns deviates from DC balance; and a data selector (3) selecting one candidate pattern from the set of the candidate patterns as data to be transmitted, according to the determined transmission control code.

Abstract: A data transmitting system includes a transmitter configured to transmit first unit data having a first bit length and second unit data sequentially with the first unit data and having the first bit length and a receiver configured to receive the first unit data and the second unit data. The transmitter is configured to transmit the second unit data to the receiver when a last bit of the first unit data and a first bit of the second unit data have different values and to invert the first bit of the second unit data and transmit the second unit data having the inverted first bit to the receiver when the last bit of the first unit data and the first bit of the second unit data have the same value.

Abstract: Network communication systems may employ coding schemes to provide error checking and/or error correction. Such schemes may include parity or check symbols in a message that may add redundancy, which may be used to check for errors. For example, Ethernet may employ forward error correction (FEC) schemes using Reed-Solomon codes. An increase in the number of parity symbols may increase the power of the error-correcting scheme, but may lead to an increased in latencies. Encoders and decoders that may be configured in a manner to produce variable-length messages while preserving compatibility with network standards are described. Decoders described herein may be able to verify long codewords by checking short codes and integrating the results. Encoders described herein may be able to generate codewords in multiple formats without replicating large segments of the circuitry.

Abstract: This application relates to an encoding method and device, a decoding method and device, and a signal transmission system.

Abstract: According to one embodiment, a magnetic memory includes: a memory area; a first memory unit disposed in the memory area and including h first magnetoresistive effect elements arrayed on a first conductive layer; and a first circuit configured to receive i-bit first data, convert the first data into j-bit (j=h) second data, and write the second data in the first memory unit. The second data includes m first values and (j?m) second values, and m and j have a relationship given by “j/2?1?m?j/2+1”.

Abstract: Systems and methods for dynamically encoding and decoding binary numbers using linear-time algorithms that encode and decode Hamming Distance-Based representations for the binary numbers are described. The binary numbers may correspond with integer values, such as 64-bit, 128-bit, or 256-bit integer values. In some cases, in response to detecting that a binary number is to be stored using a particular type of memory (e.g., a phase change memory), the binary number may first be encoded using a Hamming Distance-Based representation and then the encoded data may be written to the particular type of memory. The binary number may be encoded by generating a binary string or a binary array representing the binary number such that if one bit flips within the binary string or the binary array, the maximum distortion in the number is less than a threshold amount (e.g., less than 256).

Abstract: In accordance with various embodiments, described herein is a system (Data Artificial Intelligence system, Data AI system), for use with a data integration or other computing environment, that leverages machine learning (ML, DataFlow Machine Learning, DFML), for use in managing a flow of data (dataflow, DF), and building complex dataflow software applications (dataflow applications, pipelines). In accordance with an embodiment, the system can provide a service to recommend actions and transformations, on an input data, based on patterns identified from the functional decomposition of a data flow for a software application, including determining possible transformations of the data flow in subsequent applications. Data flows can be decomposed into a model describing transformations of data, predicates, and business rules applied to the data, and attributes used in the data flows.

Abstract: A method of implementing a keyed cryptographic operation using a plurality of basic blocks, includes: generating a balanced encoding function; applying the balanced encoding function to the output of a first basic block; and applying an inverse of the encoding function to the input of a second basic block, wherein the second basic block receives the encoded output of first basic block as an input.

Abstract: Techniques for header encoding include encoding a plurality of bits using a forward error correction code, generating an FEC codeword comprising a plurality of encoded bits, and concatenating a first copy of the FEC codeword with a second copy of the FEC codeword, wherein the concatenating comprises cyclically shifting by two bits the second concatenated copy of the FEC codeword relative to the first concatenated copy of the FEC codeword, wherein the encoded bits of the first and second copies of the FEC codewords are modulated on at least one OFDM symbol. techniques for header decoding include receiving a plurality of encoded bits comprising at least two concatenated copies of an FEC codeword, decoding a first copy of the FEC codeword to generate a first plurality of decoded bits, and decoding a second copy of the FEC codeword to generate a second plurality of decoded bits.

Abstract: A front end for a radar system and method of operation are described. A timing circuit controls operation of a transmitter circuit and a receiver circuit and outputs a valid data signal indicating whether the receiver circuit will be receiving a reflected radar signal. A converter converts a received radar signal and outputs digital data. A serialising circuit receives the digital data and supplies a serial data stream including the digital data for a data processing device. The valid data signal is also communicated to the converter to cause the converter to output a bit pattern corresponding to a code word when the valid data signals indicates that the receiver circuit will not be receiving the reflected radar signal and to output a bit pattern corresponding to a data word including radar data when the valid data signals indicates that the receiver circuit will be receiving the reflected radar signal.

Abstract: A method of detecting faults in a register bank is disclosed. The register bank includes at least one chain of registers. The method comprises sequentially shifting parameters stored in each register of the chain to an output node of the chain and inverting each parameter and feeding each parameter back to an input node of that chain, and sequentially shifting the inverted parameters through the chain until all the non-inverted parameters have been output at the output node. A first checksum of the parameters output at the output node is calculated. The inverted parameters in each register of the chain are sequentially shifted to the output node of the chain. A second checksum of the inverted parameters output at the output node is calculated, and the first and second checksums are compared.

Abstract: A circuit includes a splitter to extract L bits from each of a plurality of N-bit transmissions on a data bus, a decoder to generate output data comprising N-L bits of each N-bit transmission, and a delay circuit to apply the L bits for a previous transmission to control the inversion of a current transmission at the decoder.

Abstract: Certain aspects of the disclosure are directed to a method for communicating data from a transmitting circuit to a receiving circuit over a noisy channel. The method can be performed by logic circuitry, and can include encoding data, for transmission over the noisy channel. The data can be encoded, as a shaped-coded modulation signal by shaping the signal based on an amplitude selection algorithm that leads to a symmetrical input and by constructing a trellis having a bounded-energy sequence of amplitude values selected by computing and storing a plurality of channel-related energy constraints based on use of a nonlinear-estimation process, and therein providing an index for the bounded-energy sequence of amplitudes. The method can also include receiving over the noisy channel, the shaped-coded modulation signal, and decoding the data from the shaped-coded modulation signal by using the index to reconstruct the bounded-energy sequence of amplitudes.

Abstract: A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.

Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

Abstract: A first frequency accumulator (7a) operates using an output signal of a variable frequency divider (3) as a clock. A second frequency accumulator (7b) operates using a reference signal from a reference signal source (1) as a clock. A comparison operating circuit (11) compares the output values of the first frequency accumulator (7a) and the second frequency accumulator (7b), and calculates a parameter so that a result of the comparison falls within a set value. A digital-analog converter (9) outputs a signal to be added to an output of a loop filter (6) depending on the parameter output from the comparison operating circuit (11).

Abstract: A communication device receives a physical layer (PHY) data unit that includes i) a first orthogonal frequency division multiplexing (OFDM) symbol corresponding to a legacy signal field of a PHY preamble, and ii) a second OFDM symbol that immediately follows the first OFDM symbol. The communication device determines a first bit sequence corresponding to the first OFDM symbol and a second bit sequence corresponding to the second OFDM symbol. The communication device unscrambles the second bit sequence to obtain an unscrambled second bit sequence, and determines whether the unscrambled second bit sequence matches the first bit sequence. If the unscrambled second bit sequence matches the first bit sequence, the communication device decodes the PHY data unit according to a first communication protocol, and if the unscrambled second bit sequence does not match the first bit sequence, decodes the PHY data unit according to a second communication protocol.

Abstract: The invention relates to method and apparatus for improving the performance of communication systems using Run Length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.

Abstract: A method for transmitting data advantageously reduces cross-talk in high-speed data transmission. The method comprises receiving an input data word, encoding the input data word into a code word, and driving the code word on to an interconnect for transmission. The code word is generating using a balanced coding scheme, and the interconnect is a single-ended, twisted-wire on-chip fly-over interconnect. A receiver circuit decodes the code word to generate an output data word.

Abstract: A time-based decision feedback equalizer (TB-DFE) circuit may include a voltage-to-time converter configured to convert a communication signal into a time-based signal. A timing of when an edge of the time-based signal occurs is indicative of a voltage level of the communication signal. The circuit may include a plurality of delay circuits arranged to process the time-based signal in series to generate a delay data signal. The delay circuits may adjust the timing of when the edge of the time-based signal occurs, and a corresponding time delay introduced by each of the delay circuits may be based on a respective weighting factor applied to one or more samples of an output digital signal previously generated by the TB-DFE circuit. A phase detector may compare a timing of an edge of the delay data signal with a reference clock signal and generate the output digital signal based on the comparison.

Abstract: A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.

Abstract: A data transmission system for a display device, the data transmission system comprising: an encoder having at least one translation table, encoding m bits of a data into n bits of a data on the basis of the translation table; a parallel-to-serial converter; a clock recovery circuit for recovering a clock from the data encoded and serialized; a serial-to-parallel converter for decoding the n bits of the encoded data to the m bits of the data; and an output driver for outputting a gray scale voltage, wherein an amplitude of the gray scale voltage is determined according to a value of the m bit of the data, and, wherein in the translation table, a larger the amplitude of the gray scale voltage of a bit pattern in 2 m pieces of bit patterns of the m bits of the data, a larger the data change index of the bit pattern.

Abstract: A transmission resource in a time domain subframe is divided into a plurality of equal duration resource elements in a time and frequency domain, the plurality of resource elements are segregated into a plurality of resource regions, information to be transmitted is modulated to generate a sequence of modulation symbols at a transmitter, the sequence of modulation symbols is mapped into the plurality of resource elements in the plurality of resource regions, and the modulation symbols are transmitted via a plurality of antennas using the respective corresponding resource elements to a receiver. The mapping of the modulation symbols in at least one resource region is independent of a certain control channel information that is carried in the time domain subframe, and the mapping of the modulation symbols in at least another resource region is dependent upon that certain control channel information.

Abstract: A method for decoding an orthogonal frequency division multiplex (OFDM) data unit is described. OFDM symbols of the OFDM data unit are received that include a first OFDM symbol that corresponds to a legacy signal field followed by a second OFDM symbol that corresponds to a candidate signal field. It is determined whether the candidate signal field corresponds to a repetition of the legacy signal field. At least some of the OFDM symbols of the OFDM data unit are decoded according to a first communication protocol indicated by the determination of whether the candidate signal field corresponds to the repetition of the legacy signal field.

Abstract: The present invention relates to a method and encoding device for encoding a sequence of m-bit pattern words and outputting as a bit-stream a frame comprising corresponding n-bit symbols as well as a predetermined comma symbol, wherein m<n, wherein occurrences of false commas in the output bitstream are avoided. The output bitstream may further be optimized based on CID count and DC balance.

Abstract: A system and method for line coding of data. A serial transmitter includes a forward error correction encoding circuit followed by a bit conditioning circuit. The bit conditioning circuit counts the lengths of runs of consecutive identical digits and, when the count reaches a threshold, flips a bit. A serial receiver receives the data from the serial transmitter. The serial receiver includes a forward error correction decoding circuit, which re-flips bits flipped by the bit conditioning circuit of the serial transmitter.

Abstract: In certain aspects, a device may include a memory and a controller coupled to the memory. The controller may be configured to process data to form codewords and to send the codewords to the memory to be stored at locations of the memory. The controller may encode and tag the incoming data (from the host) to minimize the charge that is required to be stored in the non-volatile memory.

Abstract: An example method for forming a data-bearing medium in accordance with aspects of the present disclosure includes setting variables associated with the data-bearing medium, the variables comprising a bit length of a codeword, identifying a phase-invariant codeword based on the variables, and arranging rows of the data-bearing medium with the phase-invariant codewords.

Abstract: Data is compressed based on non-identical similarity between a first data set and a second data set. A representation of the differences is used to represent one of the data sets. For example, a probabilistically unique value may be generated as a new block label. Probabilistic comparison of the new block label with a plurality of training labels associated with training blocks produces a plurality of training labels that are potentially similar to the new block label. The Hamming distance between each potentially similar training label and the new block label is determined to select the training label with the smallest calculated Hamming distance from the new block label. A bitmap of differences between the new block and the training block associated with the selected training label is compressed and stored as a compressed representation of the new block.

Abstract: A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.

Abstract: Technology is described herein for encoding and decoding numbers. In one aspect, floating point numbers are represented as binary strings. The binary strings may be encoded in a manner such that if one bit flips, the average and maximum distortion in the number that is represented by the binary string is relatively small. In one aspect, 2^n binary strings are ordered across an interval [a, b) in accordance with their Hamming weights. Numbers in the interval may be uniformly quantized into one of 2^n sub-intervals. For example, floating point numbers in the interval [a, b) may be uniformly quantized into 2^n sub-intervals. These 2^n sub-intervals may be mapped to the 2^n binary strings. Thus, the number may be assigned to one of the 2^n binary strings. Doing so may reduce the distortion in the number in the event that there is a bit flip in the assigned binary string.

Abstract: A method implemented by a transmitter, comprising encoding digital in-phase and quadrature-phase (IQ) data associated with a plurality of analog signals according to a first multi-level modulation format to produce a modulated IQ signal, encoding control information associated with the plurality of analog signals according to a second multi-level modulation format that is different from the first multi-level modulation format to produce a modulated control signal, aggregating the modulated IQ signal and the modulated control signal via time-division multiplexing (TDM) to produce an aggregated TDM signal, and transmitting the aggregated TDM signal over a communication channel.

Abstract: A display device includes an encoder having at least one translation table, and encoding m (m is a natural number) bits of a data to n (n is a natural number and n>m) bits of a data on a basis of the at least one translation table; a clock recovery circuit configured to recover a clock from the data encoded by the encoder; a decoder configured to decode the n bits of the encoded data to the m bits of the data in accordance with the clock recovered by the clock recovery circuit; an output driver configured to output a voltage in accordance with the data decoded by the decoder; and a display element having a pixel applied with the voltage.

Abstract: The invention provides methods of encoding content for distribution over a network and methods for decoding encoded content which has been distributed over the network. In a first example in which the content is divided into a plurality of segments and each segment comprising a plurality of blocks of data, the method comprises selecting a segment from the plurality of segments and selecting at least two blocks of the selected segment from a store of blocks. A new encoded block is created from a linear combination of the selected blocks.

Abstract: Signal processing methods, signal processing device(s), signal processing system(s) and non-transitory information storage means are provided herein for shaping the spectrum of an input bitstream. In at least one embodiment, a signal processing method includes performing a plurality of line coding steps on respective parts of an input bitstream to obtain a plurality of respective line-coded signals, and multiplexing the plurality of line-coded signals to obtain a spectrum-shaped output signal. Embodiments provide a modulation scheme that makes it possible to shape the spectrum of a bitstream to be transmitted in order to match a channel transfer function of a communication medium.

Abstract: A system may include a first device, a second device, a third device, and a serial link between the second device and the third device. The first device may be configured to deliver to the second device an information stream having a transmission fault tolerance associated with a transmission by the second device to the third device over the serial link. A related method may include, during the transmission over the serial link, phases for synchronization between the second and third devices, and during each synchronization phase, the first device may continue to deliver the information stream to the second device.

Abstract: A storage controller includes a control unit and an interface. The control unit, when write data input as data to be written onto a magnetic disk includes a bit string of a first pattern, inverts one or more bits of the bit string. The write data includes a redundancy bit string used for data error correction. The interface outputs write data including bit inverted by the control unit.

Abstract: Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision.

Abstract: Circuits that are matched to balanced codes may recover transmitted information in a noise resilient and power efficient manner. Circuit components for processing a balanced code may include one or more of: matched amplification of the signals representing the balanced code, matched equalization and/or filtering on the signals representing the balanced code, matched non-linear filtering on the signaling representing the balanced code to detect the presence of particular symbols and matched latching of the signals representing the balanced code. Such matched circuits and circuit components may be achieved at least in part by incorporating suitable common circuit nodes and/or a single energy source into circuit topologies.

Abstract: A method of detecting a data bit depth and an interface device for a display device using the same are disclosed. The method includes confirming a physical connection between a transmitting terminal and a receiving terminal and then transmitting a clock data recovery (CDR) training pattern signal from the transmitting terminal to the receiving terminal, outputting clocks from a CDR circuit of the receiving terminal using the CDR training pattern signal, receiving an alignment training pattern signal subsequent to the CDR training pattern signal from the transmitting terminal to the receiving terminal, and counting bits of pixel data included in the alignment training pattern signal or the clocks and determining a data bit depth of input data based on a count result, in the interface receiving terminal.