Abstract: An improved transmission protocol is used to transmit a signal between two components of an electronic device. The improved transmission protocol is configured to reduce the number of simultaneous channel transitions that occur when multiple signal channels are transmitted in parallel. Reducing the number of simultaneous channel transitions is beneficial because a signal that is subject to skew, distortion, or electromagnetic interference during transmission may have a shorter settling time when fewer channels undergo a transition simultaneously. When the protocol is used to transmit a signal from a controller to an optical pickup unit in an optical data storage system, the reduced settling times allow for a higher data transmission rate.

Abstract: The present invention provides a convolutional line coding method, including: constructing a sequence set, where the length of each sequence in the sequence set is n bits; selecting a balanced sequence in the sequence set, and obtaining source data of n?1 bits corresponding to the balanced sequence; performing Hamming distance detection for an unbalanced sequence in the sequence set to obtain source data of n?1 bits corresponding to the unbalanced sequence; sorting the balanced sequence and the unbalanced sequence according to an operation difference value, and generating a code table, where the source data of n?1 bits correspond to the sequence of n bits, and the code table is designed for line coding; and at time of encoding the source data of n?1 bits, obtaining a coding result of n bits according to a mapping relation in the code table.

Abstract: A method for encoding data to be placed into a weight constrained memory array includes designating a set of crosspoints within a crossbar memory array as indicator crosspoints and a set of crosspoints within the memory array as data crosspoints, the set of indicator crosspoints selected so that a net number of times that each data crosspoint has been flipped can be determined from a subset of the set of indicator crosspoints, placing an input stream of data into a matrix corresponding to crosspoints within the memory array, bits of the input stream being placed into matrix elements that correspond to data crosspoints of the memory array, setting each matrix element corresponding to indicator crosspoints to a value corresponding to a fixed resistive state, and flipping each bit corresponding to a conductor of the memory array until no conductors within the memory array violate a weight constraint.

Abstract: An encoder comprises a first and a second input, and a first and a second output, and the encoder comprises a selection block suitable for selecting a more significant bit and a less significant bit. The encoder comprises a switching block suitable for connecting the first input to the first output, and the second input to the second output, the switching block being suitable for being switched in order to connect the first input to the second output and the second input to the first output, when the selection block has selected a less significant bit and a more significant bit. A decoder, a storage medium and an electronic system is also disclosed.

Abstract: Provided is an encoding apparatus including an encoding unit that generates encoded data formed from a sequence of base-k data in which m pieces (m<n) of base-k symbols are combined, by converting input binary data in units of n bits based on a specific conversion rule that associates n-bit binary data and the base-k data. In case a DC balance of the base-k data obtained after conversion has a polarity, the encoding unit controls a polarity of a symbol included in the base-k data obtained after conversion such that the polarity of the DC balance of the base-k data obtained after conversion is different from a polarity of a DC balance of a sequence of base-k data previous to the base-k data obtained after conversion.

Abstract: A coding apparatus includes a transform table in which with regard to data words of m bits and code words of n bits where n and m are both integers and also n>m is established, 2m pieces of code words selected to have a tendency that the number of symbols “1” is small among the 2n pieces of code words of n bits are associated with the 2m pieces of data words of m bits and a coding unit that encodes input data words of m bits on the basis of the transform table.

Abstract: An encoding apparatus that converts m-bit data words into n-bit code words, where m and n are both integers and satisfy an expression 2n?2m×2, includes a first conversion table in which 2m m-bit data words are associated with 2m n-bit code words selected from 2n n-bit code words, a second conversion table in which the 2m m-bit data words are associated with 2m n-bit code words that have been selected from the 2n n-bit code words and that do not overlap with the 2m n-bit code words in the first conversion table, and an encoder configured to select and output an n-bit code word with which an m-bit data word that has been input is associated in the first conversion table or an n-bit code word with which the m-bit data word that has been input is associated in the second conversion table, the selected and output n-bit code word having a smaller number of symbols “1”.

Abstract: This application relates to decoding signals that carry clock and data information. In particular, it relates to construction a time-varying histogram of inter-arrival times between pulse edges and using the histogram to identify whether a pulse edge encodes a single length interval, a double length interval or some longer length interval. Further details and embodiments of the technology disclosed are provided in the drawings, detailed description and claims.

Abstract: A method and system for ciphering interface with list processing is described. Various aspects of a system for ciphering interface with list processing may include a cipher module that enables deciphering and/or bit stuffing, in hardware, of a potion of one of a plurality of data blocks starting at any bit location that is subsequent to a first bit of the one of the plurality of data blocks. One of the plurality of data blocks may comprise at least one data word. A modulus of a number representing the bit location with respect to a number of bits in the one of the data words may be a number greater than 0. The cipher module may enable selection of any bit location based on and index and/or an offset. The cipher module may enable selection of deciphering and/or bit stuffing based on configured information.

Abstract: Embodiments of an encoder and a decoder are described. The encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on two corresponding sets of output nodes, a first set and a second set. The encoder selects a current codeword such that it differs from the immediately preceding codeword by a fixed number of zero-to-one transitions on the first set of nodes and a fixed number of one-to-zero transitions on the second set of nodes. A decoder receives and decodes the codewords by comparing symbols on node pairs for which the symbols expressed in the prior code word were alike and decoding the results of those comparisons.

Abstract: A data demodulator includes: a conversion means for converting an RLL code obtained by converting data in which information bits including specific bits are inserted at fixed intervals which is included in an input signal in accordance with a modulation table having variable-length conversion rules into data in accordance with a demodulation table corresponding to the modulation table; a determination means for determining control segments for performing calculation intended by the information bits from the converted data; a calculation means for executing calculation intended by the specific bit inserted in the control segment different from a calculation target with respect to the data of the control segment as the calculation target; and a correction output means for selecting one of first data converted by the conversion means and second data obtained by converting the RLL code of the input signal corrected based on the calculation result in accordance with the demodulation table and outputting the data.

Abstract: An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.

Abstract: Provided is an encoding apparatus including an encoding unit that converts, based on a first conversion rule group according to which a total value for a base-K symbol sequence is X and a second conversion rule group according to which the total value for the base-K symbol sequence is ?X among conversion rule groups for converting an L-bit bit sequence into the base-K symbol sequence (K>2) of N/2 symbol, an M-bit (M?2*L) bit sequence into the base-K symbol sequence of N symbols. When converting the M-bit bit sequence into the base-K symbol sequence of N symbols, the encoding unit converts a first-half N/2 symbol based on the first conversion rule group and converts a second-half N/2 symbol based on the second conversion rule group.

Abstract: M-bit data are encoded into n-bit data such that the encoded n-bit data has a sufficient number of encoded data patterns enough to encode the number (2m) of data patterns in the m-bit data but that the n-bit data has Hamming Weights (HWs) with minimum (smallest possible) variation. Specifically, encoder logic is configured to receive 2m of m-bit data patterns and encode the 2m of m-bit data patterns to n-bit encoded data patterns, n being greater than m and me being a positive integer greater than one. The encoder logic is configured to map the 2m m-bit data patterns to a subset of 2m of the n-bit encoded data patterns, and the n-bit data patterns in said subset has a minimum (smallest possible) range of Hamming Weight variation while the number of the n-bit data patterns in said subset is not less than 2m.

Abstract: Provided is an information processing apparatus including a distributor that distributes input data in units of M bits and generates N M-bit bit sequences, an encoder that converts each of the N bit sequences distributed by the distributor into a binary symbol sequence of K symbols and generates N binary symbol sequences, a signal generator that generates N transmission signals Sj synchronized with a specific symbol clock and having, as an amplitude value, each symbol value included in the N binary symbol sequences, a signal delay unit that delays, with regard to j, the transmission signals Sj generated by the signal generator by a (j?1)/N-symbol period and generates delay signals Rj, a signal addition unit that adds the delay signals Rj generated by the signal delay unit and generates an added signal, and a signal transmitter that transmits the added signal generated by the signal addition unit.

Abstract: An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending on the information. Accordingly, an information receiving apparatus comprises an interface comprising an input for a data word and an output for an information, wherein the interface derives the information depending on whether the data word is a valid data word or an invalid data word.

Abstract: A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable.

Abstract: Method and system are disclosed for expanding a reference number range without altering existing data storage length. Such reference numbers may include employee numbers, social security numbers, customer account numbers, and the like. The method/system takes advantage of the way decimal numbers are stored by computers to allow text to be used in numeric reference numbers. In one implementation, letters A-Z are used for the leftmost position, increasing the domain count of reference numbers from 10 to 36 for that position. A reference number expansion utility is then used to convert the additional reference numbers to and from the existing data storage format.

Abstract: An encoder encodes data into parallel codewords. Each codeword is expressed as a set of logic 0s and a set of logic 1s on two sets of output nodes. The encoder selects a current codeword which differs from the immediately preceding codeword by a fixed number of zero-to-one transitions on the first set of nodes and a fixed number of one-to-zero transitions on the second set of nodes. The current codeword is selected such that the first and second sets of nodes are different than additional nodes that contain transitions between the immediately preceding codeword and a bi-preceding codeword, and that logic values on additional nodes are unchanged between immediately preceding codeword and current codeword. A decoder decodes the codewords by comparing symbols on node pairs other than those for which transitions were expressed in the preceding code word, and decoding the results of those comparisons.

Abstract: An encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on output nodes. The encoder selects a current codeword from a group of codewords in a codespace which does not overlap the other group of codewords, i.e., codewords in a given group of codewords are not included in any other group of codewords in the codespace. This property allows a receiver of the codewords to be simplified. In particular, a mathematical operation performed on symbols in the current codeword uniquely specifies the corresponding group of codewords. This allows a decoder to decode the current codeword using comparisons of symbols received on a subset of all possible combinations of node pairs.

Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

Abstract: Embodiments provide for a method for eliminating pathological sequences in a serial bit stream. Parallel data words having a first bit length are received. The received data words may be analyzed for a pathological sequence. If a pathological sequence is present in a data word, the data word containing the pathological sequence may be segmented into data segments having bit lengths less than a pathological sequence. The data word may be reformatted by generating reformatted data words having a second bit length. The reformatted data words may contain at least one of the data segments and the second bit length is greater than the first bit length. The reformatting may be performed by adding framing bits to the segments to form the reformatted data words. The reformatted data words are transmitted in place of the data word containing the pathological sequence.

Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

Abstract: An encoding method and an encoder for encoding data transmitted in a manner of bursts via a parallel bus and a decoding method and a decoder. The encoding method includes organizing data of the bursts into matrixes, determining for each of the matrixes whether a transform mode capable of decreasing the bus transition number exists, determining that the matrix needs to be transformed, determining a transform mode for transforming the matrix, and replacing the initial matrix with the transformed matrix. Then, forming a new matrix to be transmitted from matrixes which do not need to be transformed and matrixes which have been transformed. Thereafter, first generating a transform information word indicating transform states of the respective matrixes and then attaching the transform information word to the matrix to be transmitted to form an encoded matrix for actual transmission.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: A modulation apparatus includes: a modulation section that modulates, in accordance with a correlation table where a data sequence with a predetermined number of bits is associated with a code sequence with a predetermined number of bits, the data sequence into the code sequence to allow a predetermined demodulation section to demodulate the code sequence into the data sequence in accordance with the correlation table, wherein the code sequence is, on NRZI method, a MSN code sequence where a null point of a frequency spectrum on a recording channel or communication channel of the code sequence is matched with a null point of a frequency spectrum of a PR equalized signal including the code sequence and a minimum run length is limited to be greater or equal to one.

Abstract: An encoding device for converting m-bit data words into n-bit (both n and m are integers and 2n?2m×2) code words includes a first encoding table in which 2m code words selected from the 2n n-bit code words correspond to 2m m-bit data words, a second encoding table in which 2m code words, which do not overlap with the code words in the first encoding table, of the 2n n-bit code words correspond to 2m m-bit data words, and an encoding unit which selects and outputs a code word, in which an absolute value of a code string DSV is smaller, from code words corresponding to the input m-bit data words in the first encoding table and code words corresponding to the input m-bit data words in the second encoding table.

Abstract: Systems and methods are provided for encoding and decoding constrained codewords using an enumerative coding graph. The constrained codewords may contain run-length and DC level limits. The enumerative coding graph contains a series of states and each state has multiple branches that lead to other states. Each state in the enumerative coding graph is associated with at least two bits of an enumerative codeword. Configuring the structure of the graph and cardinalities associated with each state allows the encoder to generate a code that conforms to defined constraints.

Abstract: A high-rate constrained code is provided to encode/decode channel data. A transformer translates binary channel data into an arbitrary alphabet size. The transformer selects an indicator word and makes forbidden prefix substitutions in the data to be transformed. A finite-state encoder imposes some user-defined constraint on the transformed data before the data is transferred to the channel. The high-rate constrained coding technique may be used to produce high-rate DC-limited and run-length-limited codes. The high-rate code can be used in tandem with error-correcting codes.

Abstract: A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the “balance” of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used.

Abstract: A storage device includes a signal processor that receives an input signal that includes a direct current (DC) voltage offset. An encoder receives the input signal from the signal processor and selectively inverts portions of the input signal based on at least one of an average DC value and a weighted DC value of the input signal.

Abstract: Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.

Abstract: An encoding apparatus that converts input digital data and an input clock into three-bit six-state transition encode outputs and outputs them is disclosed. The encoding apparatus has a first state transition control section, second state transition control section, and an output selection section. The first state transition control section changes a state of first data at a positive edge of the input clock. The second state transition control section changes a state of second data at a negative edge of the input clock. The output selection section alternately selects the state of the first state transition control section and the second state transition control section.

Abstract: A semiconductor device may include a coding lookup table unit including a plurality of coding lookup tables each of which is selected by a respectively selection signal, and a selection unit configured to receive one of N-bit parallel data and extract respective encoded data corresponding to the selection signal and to which the N-bit parallel data is mapped from the coding lookup table unit, and encoded data and extract respective N-bit parallel data corresponding to the selection signal and to which the encoded data is mapped from the coding lookup table unit, wherein N is 2 or an integer greater than 2, and wherein the coding lookup tables respectively store a plurality of coded data patterns that respectively correspond to patterns of the N-bit parallel data and are random temporally and spatially.

Abstract: Disclosed herein is a data identification method for identifying, from within a readout signal from a recording medium on or in which user data of k bits are recorded using a recording modulation code wherein m bits from among n bits which compose one codeword have a value of “1” while the remaining n-m bits have another value of “0”, the data, n and m being integers including, a first step of delimiting the readout signal in a unit of a codeword and adding, with regard to one of the n-bit codewords obtained by the delimiting, an amplitude of the readout signal of the bits of “1” to 2k different codewords which may possibly be recorded and setting results of the addition as evaluation values, and a second step of finding a maximum value among the 2k evaluation values and outputting the maximum value as an evaluation result.

Abstract: DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

Abstract: A data communication device or system includes a preamble unit and a data interface. The preamble unit generates or detects a first preamble having a first length for a first data line, and generates or detects a second preamble having a second length for a second data line. The first length is different from the second length, and data on the first and second data lines form parallel data. The data interface communicates a first data with the first preamble via the first data line and communicates a second data with the second preamble via the second data line. The respective length and/or respective pattern of each preamble are adjustable and/or programmable.

Abstract: An apparatus for enhancing packet communication is disclosed. In one embodiment, the apparatus includes an encoder configured to convert input data to a binary coded base system of an augmented code employing a base of an original code used for coding the input data, wherein the augmented code employs more symbols for coding than the original code, the encoder including: (1) an adder configured to add the input data to a multiplication product to generate a base sum that is binary-coded in the augmented code, (2) a multiplier configured to multiply an accumulated value by a base of the original code to provide the multiplication product that is binary-coded in the augmented code, and (3) an accumulator configured to employ the base sum to provide an accumulated value as an output for the encoder, wherein the accumulated value is binary-coded in the augmented code to represent the input data.

Abstract: There are provided a method and apparatus for embedding a second level code into a first level code of an optical disc by data modulation rule variation. The apparatus includes a multi-level, varying rule based modulator (199) for modulating the first level code to obtain a channel bit stream representative of the first level code and having the second level code embedded therein. The multi-level, varying rule based modulator modulates the first level code using modulation rules respectively having different statistical properties of pit-land length distributions that preserve a readability of the first level code and that are distinguishable at readout of the optical disc. The different statistical properties represent binary or multilevel data of the second level code.

Abstract: In one embodiment, an integrated circuit comprises circuitry for performing bus inversion. The circuitry is operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes each of which the integrated circuit is capable of performing. The circuitry is also operable to process data input to and output from the integrated circuit based on the bus inversion scheme for which the integrated circuit is configured.

Abstract: Methods of encoding data to and decoding data from flash memory devices are provided. User data having an unknown ratio of 1's to 0's is received. The user data is utilized in generating transformed data that has a predictable ratio of 1's to 0's. The transformed data is stored to flash memory. The transformed data is illustratively generate by either applying an “exclusive or” function to the user data or by converting the user data into a number having a greater number of bits.

Abstract: To reduce the complexity of the encoding/decoding of pulse positions and/or pulse magnitudes associated with complex combinatorial computations, a method and structure for encoding and decoding of pulse position and/or pulse magnitudes requires fewer computations of these combinatorial functions. Adaptive switching between coding or encoding is performed in accordance with the estimated density of the plurality of occupied positions.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo-random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo-random data streams. An encoder RLL-modulates the plurality of types of pseudo-random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals.

Abstract: A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be located in any position of the unformatted block. The block encoder inserts data characters into a first set of slots of the encoded data block. The block encoder encodes K characters to produce corresponding encoded K characters. Each encoded K character includes a link field, a position field and a recoded value field. The encoded K characters are inserted into a second set of slots of the encoded data block. A synchronization header is attached to the encoded data block to distinguish control blocks from pure data blocks. The header and encoded data block are subsequently scrambled in preparation for transmission.

Abstract: Systems and methods are provided for encoding and decoding constrained codewords using an enumerative coding graph. The constrained codewords may contain run-length and DC level limits. The enumerative coding graph contains a series of states and each state has multiple branches that lead to other states. Each state in the enumerative coding graph is associated with at least two bits of an enumerative codeword. Configuring the structure of the graph and cardinalities associated with each state allows the encoder to generate a code that conforms to defined constraints.

Abstract: A method for encoding data packets includes providing an encoding scheme for coding source data units into encoded data units; establishing a first look-ahead table for the source data units; providing a data packet including a first source data unit and a second source data unit; encoding the first source data unit to generate a first encoded data unit; indexing the first look-ahead table using the first source data unit to determine a balancing capability of the first encoded data unit for balancing a running disparity; and encoding the second source data unit to generate a second encoded data unit using the balancing capability of the first encoded data unit.

Abstract: A coder is fed with pre-coded data such that the absolute value of the RDS of the code words as produced by the coder is limited. This is achieved by ensuring that in a group of 2 code words the RDS of the first code word is compensated by the RDS of the second conde word. The RDS at the end of the second code word is then zero and the excursions of the RDS from the start of the first code word until the end of the second code word are limited because there are only a limited number of bits that can contribute to an increase of the absolute value of the RDS. This principle can easily be applied to the 17PP coder.

Abstract: A system and method for increasing transmission distance and/or transmission data rates using tedons and an encoding scheme to reduce the number of ones in a data signal is described. For example, the method for increasing transmission distance and transmission data rate of a fiber optical communications link using tedons includes the steps of encoding a data signal to be transmitted using an encoding scheme that reduces a number of ones in the data signal, transmitting the encoded data signal over the fiber optical communications link, receiving the encoded data signal and decoding the encoded data signal.

Abstract: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.