Abstract: Methods and apparatus intelligently switching between line coding schemes based on context. In one exemplary embodiment, an High Definition Multimedia Interface (HDMI) system is configured to transmit control and video data according to an 8B/10B line coding protocol, and data island data according to TERC4 (TMDS (Transition Minimized Differential Signaling) Error Reduction Coding 4-bit). Various elements of the disclosed HDMI devices are configured to determine when a context switch occurs, and thereafter seamlessly transition between the appropriate line code protocol.

Abstract: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level enumerative encoder operable to encode the data set before it is written to the storage medium as encoded data, wherein the enumerative encoder applies an enumeration using a plurality of level-dependent bases, and a decoder operable to decode the data set after it is read from the storage medium.

Abstract: In general, techniques are described that insert one or more bits into a digital bit stream to maintain an overall transition density in the digital bit stream. Maintaining the overall transition density facilitates the generation of a recovered clock by a phase-locked loop (PLL) circuit of a receiver. For example, when a data transition ratio for a portion of the digital bit stream is less than a desired data transition ratio, the techniques insert additional bits to increase the overall transition density of the digital bit stream.

Abstract: This disclosure generally relates to encoding, transmission, and decoding of digital video, and more particularly to methods and systems for minimizing decoding delay in distributed video coding (DVC). In one embodiment, a video decoding method is disclosed, comprising: obtaining side information; obtaining a syndrome bit chunk corresponding to a non-key-frame bit-plane; performing, via one or more processors, at least one non-key-frame bit-plane channel decoding iteration using the side information and the syndrome bit chunk; generating a decoded bit-plane via performing the at least one non-key-frame bit-plane channel decoding iteration; determining a bit error rate measure for the decoded bit-plane; determining, based on the bit error rate measure, a number of additional syndrome bit chunks to request; and providing a request for the additional syndrome bit chunks.

Abstract: Circuits that are matched to balanced codes may recover transmitted information in a noise resilient and power efficient manner. Circuit components for processing a balanced code may include one or more of: matched amplification of the signals representing the balanced code, matched equalization and/or filtering on the signals representing the balanced code, matched non-linear filtering on the signaling representing the balanced code to detect the presence of particular symbols and matched latching of the signals representing the balanced code. Such matched circuits and circuit components may be achieved at least in part by incorporating suitable common circuit nodes and/or a single energy source into circuit topologies.

Abstract: Multi-level encoded data transfer is disclosed. 2n bits may be encoded in a data signal each half clock cycle. For example, four bits may be transferred each clock cycle. Prior to data transfer, each data line may have two bits ready to be encoded. The two bits may be encoded to one of four different data states. The clock may be divided into four intervals for each half clock cycle, with each interval corresponding to one of the four data states. The two bits may be encoded into the data signal based on the interval that corresponds to the data state. As one example, the data signal could transition during the interval that corresponds to the data state for the two bits. This encoding may be repeated for two other bits for the other half of the clock cycle. Thus, QDR or some other data rate may be achieved.

Abstract: A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.

Abstract: The invention is directed to a multi-bit digital signal isolation system including a plurality of micro-transformers, each having a primary winding and a secondary winding, a transmitter circuit receiving a multi-bit signal and transmitting an encoded logic signal across the plurality of micro-transformers corresponding to the multi-bit signal, the primary winding of each micro-transformer receiving a signal corresponding to one of at least three possible states, and a receiver circuit receiving the encoded logic signal from the secondary windings of the plurality of transformers, decoding the encoded logic signal and reconstructing the received multi-bit signal based upon the decoded signal.

Abstract: A method of line coding is disclosed that limits error propagation in a decision feedback equalizer (DFE) of a receiving device. A communications device receives a set of bits to be transmitted over a channel and divides the set of bits into a plurality of blocks based, at least in part, on a line coding scheme. The device then encodes each of the blocks of bits into a corresponding block of symbols based on the line coding scheme. Specifically, the line coding scheme has a non-uniform coding efficiency, wherein a first bit or a last bit of each block of bits is mapped to a single data symbol. For some embodiments, the line coding scheme may be a ternary line coding scheme that maps a block of 3k+1 bits to a corresponding block of 2k+1 symbols, where k is an integer greater than 1.

Abstract: It is an objective of the present invention to provide a technique, when using fixed-length run-length limit codes based on enumeration, that generates fixed-length channel bit words satisfying maximum run-length limitation using a simple configuration. A channel bit word processor according to the present invention includes an avoidance list that describes a difference between a user bit word satisfying a maximum run-length limitation of run-length limit code and a user bit word not satisfying the maximum run-length limitation. The channel bit word processor, if a user bit word does not satisfy the maximum run-length limitation, generates a channel bit word using a user bit word after the difference is added.

Abstract: An array f(n) is received for n=1, . . . , N where N is a length of a codeword. An array g(n) is received for n=1, . . . , N where N is a length of a codeword. Input data is encoded to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n).

Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

Abstract: An error control encoding system produces a codeword from a data word, where the resulting codeword includes the data word and three or more parity segments produced using the data word. The system includes a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, where each of the two or more first data segments includes a respective sequential portion of the data word. The system includes a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, where each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or more first data segments.

Abstract: System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.

Abstract: A multilevel amplitude modulation device for generating, from digital data, a multilevel amplitude modulation signal having four or more signal levels and outputting the generated signal, including: an average level calculator that selects one of a plurality of preliminarily prepared different candidates for a code word building method such that average level of a symbol array, obtained by adding a symbol for a code word of digital data to be transmitted to one or more already outputted symbols included in a multilevel amplitude modulation signal already outputted, is most approximate to voltage center of the four or more signal levels, and outputs a selection signal indicating the selected method; a signal converter that forms a codeword of the digital data in accordance with the method indicated by the selection signal; and a multilevel modulator that generates a multilevel amplitude modulation signal using the codeword and outputs the generated signal.

Abstract: An image coding apparatus provides a run-length encoding unit RLE1 that subjects quantized coefficients obtained by quantizing frequency components of an image signal to a variable length coding process by using a run value Run that indicates the number of successive zero coefficients and a level value Lev that indicates a value of a non-zero coefficient following the zero coefficients. The run-length encoding unit RLE1 includes a reordering unit Lreodr for reordering level values Lev; a variable length coder LVLC for coding reordered level values ROLev by using a code table selected according to the value of a quantization parameter QP; a reordering unit Rreodr for reordering run values Run from high frequency component of the quantized coefficients to low frequency component; and a variable length coder RVLC for coding reordered run values RORun by using a code table selected according to the number of already-processed run values.

Abstract: A method and apparatus for symbol-space based compression of patterns are provided. The method comprises receiving an input sequence, the input sequence being of a first length and comprising a plurality of symbols; extracting all common patterns within the input sequence, wherein a common pattern includes at least two symbols; generating an output sequence responsive of the extraction of all common patterns, wherein the output sequence has a second length that is shorter than the first length; and storing in a memory the output sequence as a data layer, wherein the output sequence is provided as a new input sequence for a subsequent generation of a data layer.

Abstract: An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The digital flag generator circuit includes a first digital stage including a first plurality of binary logic circuits. Each of the binary logic circuits is configured to receive a subset of the data word.

Abstract: A mechanism is provided for dynamically adjusting DC offset at the time of deviation from DC balance ½ (DC level) in a data pattern including long-period consecutive bits generating DC offset in a section of data. A receiver circuit unit of an LSI having a serializer/deserializer arrangement for performing high-speed serial transmission includes an offset adjusting circuit. The offset adjusting circuit calculates DC balance in an arbitrary section of data by averaging received serial data. Based on comparison between a DC level and the DC balance obtained by averaging the received data, offset is shifted toward the H side when the DC balance exists on the H side from the DC level, and shifted toward the L side when the DC balance exists on the L side.

Abstract: A plurality of random bit sequences is generated. Each of the random bit sequences is different and is based at least in part on an input bit sequence. A plurality of metrics corresponding to the plurality of random bit sequences is generated. The plurality of metrics is associated with one or more transition run lengths. One of the random bit sequences is selected based at least in part on the metrics. An output bit sequence is generated that includes the selected random bit sequence and an index associated with demodulating the selected random bit sequence.

Abstract: Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.

Abstract: Embodiments of the present invention generally relate to binary block transmission codes for high-speed network transmissions. More specifically, embodiments of the present invention relate to bounded-disparity run-length-limited forward error correction codes and methods of constructing and utilizing same. In one embodiment, a method for generating binary block bounded-disparity run-length-limited forward error correction transmission codes comprises selecting an existing base code, deriving a sub-code from the existing base code, having properties indicated by disparity bound, run-length limit and minimum distance, ascertaining a plurality of codewords and control characters from within the sub-code, encoding Messages to be transmitted with at least one codeword from the plurality of codewords, transmitting codewords from a transmitter to a receiver, and decoding the codewords into Messages.

Abstract: A minimum energy coding method and apparatus that includes obtaining groups of bits from a bitstream and finding a mapping rule between the groups of bits and codewords that is chosen to maintain a DC balance. For example, the bitstream may be a bitstream corresponding to a biosignal.

Abstract: A data transmission/reception system includes a data transmission circuit and a data reception circuit. The data transmission circuit includes a pattern detection unit configured to detect a pattern of data to be loaded on inner lines among a plurality of transmission lines and generate an inversion signal, and a transmission unit configured to transmit data to the plurality of transmission lines and the inversion signal to an inversion line, and invert some of the data to be loaded on the inner lines in response to the inversion signal. The data reception circuit is configured to invert the data inverted by the transmission unit among the data transferred to the plurality of transmission lines, in response to the inversion signal.

Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

Abstract: Systems and methods for communicating digital data associated with amplitudes and phases of a virtual periodic waveform having a designated period between components connected by n conductors include, in one embodiment, circuitry that converts a first amplitude and a first phase to a first corresponding voltage or current and applies the first corresponding voltage or current to a first one of the plurality of conductors, and converts the first amplitude and the first phase to (n?1) corresponding voltages or currents based on amplitudes of the periodic waveform phase shifted by about m*(360/n) relative to the first phase where m is indexed from one to (n?1) and applies each corresponding voltage or current to an associated conductor of the plurality of conductors. The systems and methods are particularly suited for reducing the number of conductors to obtain a desired I/O data rate/throughput for integrated circuit chips and wired networks.

Abstract: Methods and apparatuses for providing multi-level encoded signals are disclosed. An apparatus may include an encoding circuit and a multi-level encoder. The encoding circuit may be configured to receive data and provide encoded data based, at least in part on the data. The multi-level encoder may be coupled to the encoding circuit and configured to receive the encoded data. The multi-level encoder may be further configured to provide the encoded data to a bus as multi-level signal responsive, at least in part, to receipt of the encoded data.

Abstract: System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.

Abstract: An embodiment may include circuitry to generate and/or receive, at least in part, a signal that may include at least one waveform. The at least one waveform may include at least one portion followed by at least one other portion. The at least one portion may include a plurality of levels to be compared to data encoding levels to determine whether the plurality of levels satisfy ratios determined based at least in part upon the plurality of levels and the data encoding levels. The at least one other portion may include maximum and minimum data encoding levels to facilitate emphasis measurement. Many alternatives, variations, and modifications are possible.

Abstract: According to an aspect of the present disclosure, a system for correcting for DC characteristics of a magnetic recording system includes: circuitry implementing at least a portion of a write channel of the magnetic recording system; and circuitry configured to process output data of the write channel circuitry in accordance with a read channel of the magnetic recording system and repeatedly trigger re-writing through the write channel circuitry using different ones of a plurality of available data scramblings until a measured baseline wander exceeds a target threshold.

Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

Abstract: A method and system for eliminating/suppressing long transition runs over a communications channel is disclosed. The method may include providing modulation coding based on a multi-level finite state machine (ML-FSM) having a periodic structure, the periodic structure being defined by a predetermined number of time frames. The ML-FSM may include a plurality of penalty-free edges for connecting nodes in one time frame to nodes at the same level in a subsequent time frame and a plurality of penalty edges for connecting nodes in one time frame to nodes at an upper level in the subsequent time frame. The method may further include utilizing the ML-FSM based modulation coding to facilitate data transmission over the communications channel.

Abstract: A data transfer method multiplexes a data character having a bit width M (M is a natural number greater than or equal to 3) and a control character having a bit width N (N is a natural number greater than or equal to 1), and adds a control character valid signal indicating whether the control character is valid, in order to generate a symbol code having a bit width M+1 or N+3, whichever is greater, and converts the symbol code from parallel data into serial data to be output to a transmission line.

Abstract: A minimum energy coding method and apparatus that includes obtaining groups of bits from a bitstream and finding a mapping rule between the groups of bits and codewords that is chosen to maintain a DC balance. For example, the bitstream may be a bitstream corresponding to a biosignal.

Abstract: An array f(n) is received for n=1, . . . , N where N is a length of a codeword. An array g(n) is received for n=1, . . . , N where N is a length of a codeword. Input data is encoded to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n).

Abstract: A semiconductor device may include a coding lookup table unit including a plurality of coding lookup tables each of which is selected by a respectively selection signal, and a selection unit configured to receive one of N-bit parallel data and extract respective encoded data corresponding to the selection signal and to which the N-bit parallel data is mapped from the coding lookup table unit, and encoded data and extract respective N-bit parallel data corresponding to the selection signal and to which the encoded data is mapped from the coding lookup table unit, wherein N is 2 or an integer greater than 2, and wherein the coding lookup tables respectively store a plurality of coded data patterns that respectively correspond to patterns of the N-bit parallel data and are random temporally and spatially.

Abstract: Systems and methods for encoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word that can be subdivided into portions of eight bits or less to be encoded using code words having one extra bit than the corresponding portion of the data word. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table. In some embodiments, data words may be less than eight bits wide.

Abstract: A prediction error calculation part calculates a prediction error for each input data. A prediction error encoding part generates a prediction error code by encoding the value of the prediction error. A run-length counting part counts the run-length of the prediction error. When the value of the prediction error changes, a run-length encoding part generates a run-length code by encoding the run-length counted. A code connecting part generates a connected code by connecting the run-length code to the prediction error code of a corresponding prediction error. When the value of the prediction error is a particular value, a prediction error checking part selects a connected code for the prediction error, as an output code. When the value of the prediction error is a different value, the prediction error checking part selects a prediction error code for the prediction error, as an output code. A code output part outputs the output code selected.

Abstract: Systems and methods for encoding/decoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word to be encoded using code words. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table.

Abstract: An image coding apparatus provides a run-length encoding unit RLE1 that subjects quantized coefficients which are obtained by quantizing frequency components of an image signal to a variable length coding process by using a run value Run that indicates the number of successive zero coefficients and a level value Lev that indicates a value of a non-zero coefficient following the zero coefficients. The run-length encoding unit RLE1 includes a reordering unit Lreodr for reordering level values Lev; a variable length coder LVLC for coding reordered level values ROLev by using a code table that is selected according to the value of a quantization parameter QP; a reordering unit Rreodr for reordering run values Run from high frequency component of the quantized coefficients to low frequency component; and a variable length coder RVLC for coding reordered run values RORun by using a code table that is selected according to the number of already-processed run values.

Abstract: A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control.

Abstract: Circuits that are matched to balanced codes may recover transmitted information in a noise resilient and power efficient manner. Circuit components for processing a balanced code may include one or more of: matched amplification of the signals representing the balanced code, matched equalization and/or filtering on the signals representing the balanced code, matched non-linear filtering on the signaling representing the balanced code to detect the presence of particular symbols and matched latching of the signals representing the balanced code. Such matched circuits and circuit components may be achieved at least in part by incorporating suitable common circuit nodes and/or a single energy source into circuit topologies.

Abstract: A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.

Abstract: Methods of encoding data to and decoding data from flash memory devices are provided. User data having an unknown ratio of 1's to 0's is received. The user data is utilized in generating transformed data that has a predictable ratio of 1's to 0's. The transformed data is stored to flash memory. The transformed data is illustratively generate by either applying an “exclusive or” function to the user data or by converting the user data into a number having a greater number of bits.

Abstract: A method comprising receiving a syntax element to be encoded as a code word of a set of code words, determining a mapping between the syntax element and the code word on the basis of a hierarchy level in a tree structure, using the mapping to obtain the code word, and updating the mapping is disclosed.

Abstract: A frame formed of a plurality of code words encoded with an encoding mode in which two different types of code words are assigned one-to-one to two smallest quantization intervals is checked to determine whether it contains just the two types of code words assigned to the two smallest quantization intervals, and lossless encoding is applied to the frame containing just the two types of code words. A code obtained by this lossless encoding is decoded with a decoding method corresponding to the lossless encoding.

Abstract: A data-processing device includes a plurality of data generation units, a plurality of bit change number calculation units, a bit change number comparison unit, a first data selection unit, and a bit-coupling unit. The data generation unit arranges input data to generate first conversion data based on each prescribed arranging method. The bit change number calculation unit compares values of respective bits in the first conversion data output at the n-th time and the (n+1)-th time by the corresponding data generation unit, and calculates a bit number based on the comparison result as a bit change number. The bit change number comparison unit compares values of the respective bit change numbers, selects the data generation unit, and outputs selection information. The first data selection unit outputs any one first conversion data selected based on the selection information as selection data. Then, the bit-coupling unit couples the selection information.

Abstract: One embodiment of the present invention provides a system that facilitates multiplexing low-speed Ethernet channels onto a high-speed channel. During operation, the system receives a number of low-speed Ethernet channels. Next, the system derives N bit streams from the number of low-speed Ethernet channels, and feeds each bit stream to an input of a serializer, which is conventionally used to serialize bits from a single channel. Each input of the serializer comprises one bit of an N-bit-wide parallel input bus, and the data rate of the serializer output matches the data rate of the high-speed channel. The system then transmits the output of the serializer onto the high-speed channel.

Abstract: The present invention provides a method and apparatus for compressing or decompressing data in Fiber Channel (FC) services. In the solution of the present invention, when compressing FC data, a K code indicator bit and an ERR code indicator bit are compressed into a K/ERR code indicator bit, and 8b codes and the K/ERR code indicator bit are compressed into 9b codes; when decompressing FC data, the 9b code is decompressed into 8b codes and a K/ERR code indicator bit, and the K/ERR code indicator bit is decompressed into a K code indicator bit and an ERR code indicator bit. The solution provided by the present invention overcomes the disadvantages that in conventional art, when processing FC service, the K code indicator bit and the ERR code indicator bit must be retained, and the K code and the ERR code are processed separately, which lead to a high bandwidth utilization ratio and a complex processing procedure.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.