Abstract: This invention relates to a digital modulation method and apparatus used for recording an audio or video signal, computer data, and etc on a recording medium such as an optical or magneto-optical disc. Data words of m bits are translated into code words of n bits in accordance with a conversion table. The code words satisfy a (d, k) constraint in which at least d “0”s and not more than k “0”s occur between consecutive “1”s. The n-bit code words alternate with p-bit merging words which are selected such that between the leading “1” in the code word following the merging word and the trailing “1” in the merging word are at least d “0”s, and further that between the trailing “1” in the code word preceding the merging word and the leading “1” in the merging word are at least d “0”s.

Abstract: A data modulation method resistant to channel distortion and a method of correcting error in data coded by the modulation method. The data modulation method uses a run length limited (RLL) modulation code applied to write data to an optical storage medium, the RLL modulation code being expressed as RLL (d, k, m, n, s) with s=2 or greater, where d is minimum run length, k is maximum run length, m is a data bit length before modulation, n is a codeword bit length after modulation, and s is a space length between codewords. Further, the data modulation method provides run lengths expressed as in+1=in+s (n=1, 2, . . . ), where i1=d.

Abstract: A data-decoding apparatus having bit-detecting section 4. In the apparatus, an RF signal is reproduced from a recording medium and converted to digital data. If the RF signal has a level (amplitude) equal to a comparator level, the bit-detecting section 4 outputs channel-bit data having logic level “0” or “1” in accordance with whether the sum of the amplitudes of the two RF signals respectively preceding and following that RF signal is higher or lower than the comparator level.

Abstract: A method for encoding data to meet a maximum run length limitation is disclosed. In one embodiment, the method comprises the steps of: (1) providing user data that includes a plurality of bits, wherein said bits have a value of 1 or 0; (2) performing an ECC computation on said plurality of user data bits to add ECC symbols in the form of a plurality of ECC bits; (3) randomizing the plurality of user data bits and said plurality of ECC bits; (4) analyzing said randomized user data bits and ECC bits to determine whether a number of consecutive bits have a common value; and, (5) inverting the value of a bit, when the number of consecutive bits having a common value exceeds the maximum run length limitation. Subsequently, representations of each of the randomized user bits and ECC bits, including any inverted bits, are stored onto a disk surface as magnetic-polarity transitions.

Abstract: A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.

Abstract: Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.

Abstract: Methods of encoding and decoding, as well as an encoding system and a digital communications system are provided for encoding data words into code words and decoding code words into data words. The data words are encoded according to a run-length-limited (RLL) code of “k” constraint, the encoding producing u-bit non-zero code words. The “k” constraint can be increased to a higher value by extending the u-bit non-zero code words to generate q-bit non-zero code words.

Abstract: A method for converting an analogue signal representing a runlength limited binary signal with runs of length of at least N into a binary output signal. The analogue signal is sampled and an intermediary binary signal is generated based on the sample analogue signal. Those binary sequences within the intermediary binary signal having a length greater than 2N−1 are identified. The sequences having a set of successive samples having the same binary value, and which borders on samples having an opposite binary value. For each such binary sequence, an analogue sequence is selected in the sampled analogue input signal which corresponds to the identified binary sequence. Then it is determined if there are a plurality of significant local extrema within the selected analogue sequence, and if they are found, the identified binary sequence is partitioned into a corresponding plurality of smaller runs, comprising at least one run of length N.

Abstract: A cost-effective high-throughput enumerative encoder is disclosed for encoding m-bit input datawords in an input data stream into n-bit output codewords in an encoded output data stream for use in a communication channel. The enumerative encoder comprises an input buffer for storing a plurality of bits in the input data stream, and a plurality of segmented compare tables for encoding the bits stored in the input buffer into the encoded output data stream, wherein each segmented compare table represents a segment of a full compare table of an enumerative trellis. A cost-effective high-throughput enumerative decoder is also disclosed for decoding n-bit input codewords in a received data stream into m-bit output datawords in a decoded data stream for use in a communication channel.

Abstract: An LZW compressor implementation architecture utilizes a plurality of limited length character tables corresponding to the respective characters of the alphabet. A string is stored by storing the code associated with the string in the character table corresponding to the extension character of the string at a character table location corresponding to the code of the string prefix. A character table is created when the character corresponding thereto is first encountered in the input. The input data character stream is searched by comparing the input stream to the stored strings to determine longest matches therewith. The codes associated with the longest matched strings are outputted so as to provide an output stream of compressed codes. The respective lengths of the character tables are limited in accordance with the frequency of occurrence of the characters of the alphabet.

Abstract: Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.

Abstract: To convert a 12-bit data word into an 18-bit code word, the 12-bit data word is divided into the 8 high-order bits and the 4 low-order bits. The 8 high-order bits are converted into 12 bits and the 4 low-order bits are converted into 6 bits, thereby creating an 18-bit code. This enables conversion using small-scale conversion tables.

Abstract: The invention pertains to a method for converting an analogue signal representing a runlength limited binary signal with runs having a length of at least N into a binary output signal comprising the following steps: a) sampling the analogue signal, b) generating an intermediary binary signal on the basis of the sampled analogue signal, c) identifying binary sequences within the intermediary binary signal having a length greater than 2N−1, the sequences comprising a set of successive samples having the same binary value, and which set borders on samples having an opposite binary value and for each such binary sequence, d) selecting an analogue sequence in the sampled analogue input signal which corresponds to the identified binary sequence, e) searching for the existence of a plurality of significant local extrema within the selected analogue sequence, f) if such a plurality of significant local extrema is found partitioning the identified binary sequence into a corresponding plurality of smaller runs, c

Abstract: In a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal the bitstream of the source signal is divided into n-bit source words. The device comprises converting means adapted to convert a block of p consecutive n-bit source words into a corresponding block of p consecutive m-bit channel words, such that the conversion for at least most of the n-bit source words is parity preserving and/or parity inverting, where m>n≧1. The converting means comprise memory means which contain for each n-bit source word a number of m-bit channel words, arranged in coding states, and a corresponding state number, indicating the state for a next m-bit channel word. After each block of source words q dc-control sourcebits are added, which are converted into r dc-control channelbits, independent of the conversion of a following source word.

Abstract: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.

Abstract: The present invention pertains to a distance-enhancing coding method that can be applied to digital recording and digital communications. It improves the time-varying maximum transition run method used in a conventional distance-enhancing coding to avoid main error events ±(1,−1) from happening. Under the premise of maintaining a code gain of 1.8 dB, the code rate can be increased from ¾ to ⅘. The invention also provides a method of using an enumeration algorithm and an exhaustive method to search for block codes for distance-enhancing coding, which can find required codes by following specific steps.

Abstract: Frequency spectrums are determined for all possible codes given a predetermined number of bits in a code. A subset of these codes is formed based on spectral properties of codes in a desired frequency band. This subset of code is then used to encode data prior to transmission over a high-speed data bus to reduce undesirable emissions on targeted frequency bands.

Abstract: A system for encoding and decoding information of a codeblock from a memory buffer that includes a context modeler that receives from the memory buffer the codeblock and divides the codeblock into a plurality of codesegments or decodes a codeblock worth of information from received compressed data. The codesegments includes a plurality of bits. The context modeler processes each of the codesegments individually by determining whether any of the bits need special coding information or decoding. The context modeler outputs coded bits associated with the bits that are coded with the special coding information and context information associated with the coded bits or outputs a codeblock worth of information to the memory buffer. An arithmetic coder receives the context information and coded bits and compresses the coded bits or receives compressed data and decompresses the compressed data to produce context information and coded bits.

Abstract: A digital data modulating method wherein the last unit of a block consisting of predetermined units is received and a block is obtained which does not infringe A k-constraint in AN RLL code having (d, k) constraints on the basis of a modulation data table of a predetermined unit. A source code word to be modulated to a code word can be quickly and accurately determined while satisfying the (d, k) constraint of the RLL code between the blocks having a predetermined size.

Abstract: An information carrier includes runlength limited marks in a track. The runlengths of the marks represent main channel bits and variations of a further parameter of the marks representing secondary channel bits. Not all marks have the variations, only marks of at least a predetermined runlength have the variations.

Abstract: A run-length based decoder for decoding compressed image data while allowing error to be contained with the length of a code word. The decoder includes: (a) a shifter for outputing Q+1 number of N-bit data streams; (b) Q+1 code comparators to respectively receive the data streams from the shifter; (c) a code type arbitrator which includes a multiplexer to receive output signals from the Q+1 number of code comparators, and output the data stream received from the code word comparator which also outputs the verification signal; (d) a shift number generator connected to the code arbitrator to receive the N-bit data stream from the code arbitrator and generate a new_shift_number to the shifter according to the number of bits associated with the code word pattern of the N-bit data stream; and (e) a code interpreter which is also connected to the code arbitrator to receive to decode the N-bit data stream into pixels.

Abstract: A method and apparatus to encode data is provided. The method includes the steps of: i) dividing the data into a plurality of blocks, with each block having a plurality of bits, wherein the plurality of blocks includes a first subset of blocks and a second subset of blocks; ii) encoding data in the first subset; arranging a codeword to include the encoded data of the first subset and the second subset; iii) scanning a plurality of segments in the codeword for at least one predetermined sequence; and iv) encoding a scanned segment when the predetermined sequence is found in the segment. A method and apparatus to decode data is also provided according to the present invention.

Abstract: A sampled amplitude read channel is disclosed for writing data to and reading data from a disk storage medium. A first channel encoder encodes a first j-k bits of a j-bit data block to generate first encoded data, and an ECC encoder encodes the first encoded data and a remaining k-bits of the data block to generate ECC redundancy symbols comprising a plurality of bits. A second channel encoder encodes the remaining k-bits of the data block and the ECC redundancy symbols to generate second encoded data. The first encoded data and the second encoded data are then output as channel data written to the disk storage medium.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: A method of coding parallel data for transmission while maintaining baud rate includes the steps of providing a plurality of uncoded data blocks having a predetermined baud rate, demultiplexing the data blocks to sequentially distribute the data blocks to encoders, encoding the data blocks at the predetermined baud rate, and serializing the coded data blocks for serially transmitting data at the predetermined baud rate. A system for coding parallel data for serial transmission while maintaining baud rate is included wherein the predetermined baud rate is maintained by providing an adequate number transmission links rather than increasing baud rate.

Abstract: A DSV control bit determining/inserting unit inserts DSV control bits into an input data string and outputs the string including the DSV control bits to a modulation unit which converts the string with basic data length of 2 bits into variable length code with basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit. The conversion table includes substitution codes for limiting the number of consecutive appearances of a minimum run and substitution codes for keeping a run length limit. The conversion table enforces a conversion rule: the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 equals the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.

Abstract: There is disclosed a modulation method in which a four bits unit of a plurality of continuous input data words is encoded into a six bits unit of a plurality of continuous output code words by referring to a plurality of coding tables including output code words corresponding to input data words, and coding table designation information in which an coding table for use in encoding the next input data word is designated. Further, in particular, two redundant bits are inserted into each predetermined number of data words of the plurality of continuous output code words. Even with such redundant bits, a DSV control is possible, k satisfies 9 in a (1, k) RLL rule, and a repetition frequency of a minimum run is limited.

Abstract: A signal processing apparatus capable of reducing burst error generation, and a highly reliable data recording/reproducing apparatus using this signal processing apparatus. This signal processing apparatus has a simple error detection/correction circuit provided just before a modulated code demodulator, thereby correcting error of a pattern easy to occur in a maximum likelihood decoder. The simple error detection/correction circuit is an error detection/correction circuit using a linear error correction code, for example, an error correction code (CRCC) formed of a cyclic code. Thus the number of burst errors after the modulated code demodulator can be decreased.

Abstract: A method and apparatus for generating multiple selectable contexts is described. In one embodiment, the method comprises generating two contexts, one of the two contexts for when the current bit being decoded is a zero bit and the other of the two context for when the current bit being decoded is a one bit indicating that a coefficient has become significant, selecting one of the two context to use to decode a bit subsequent to the current bit, wherein selecting the one context is based on the current bit once decoded, and decoding the bit subsequent to the current bit using the one context.

Abstract: A coding table portion includes six coding tables each storing a code word and status information indicating a coding table for use in modulating a next input data word in order to obtain a next code word which satisfies a predetermined run length restriction rule even if the next code word is coupled directly with the preceding code word, corresponding to each input data word. In the coding table portion, the code words and status informations allocated corresponding to input data words of a number set up preliminarily in succession from the highest appearance frequency to a lower one in one or more coding tables of the plural coding tables are replaced with code words having smaller RDSs and status informations allocated corresponding to other input data words in the same coding table. Consequently, the input data word is modulated using the six coding tables.

Abstract: A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.

Abstract: A method and apparatus for recording and reproducing information to and from an optical disk. If the size of a shortest mark is made small, a signal amplitude lowers and errors are likely to occur. In order to overcome this problem, when data of asymmetric codes is written, the length of a write mark is compensated so that the shortest mark and gap have the same length.

Abstract: A circuit and method for protecting the minimum run length in RLL code is disclosed. The circuit comprises three state processors, each having a plurality of registers, including a decision bit, an invalid bit, metric bits and path bit array, and changing state at the zero crossing point (Turning) of an RF signal, before the zero crossing point (Before) and after the zero crossing point (After). A metric computing unit is used to calculate the metrics at the points of turning, before and after corresponding to the EFM (Eight-Fourteen Modulation) signal. A timing unit is used to generate control signals to the state processors and metric computing unit according to the EFM signal. Then the protecting circuit comprises a computing unit to control the decision bit, the invalid bit, the metric bits and path bit array and generates correct output signals according to the control signals and the metrics.

Abstract: A method for modulating digital data and apparatus therefor is capable of determining digital data stream coded by Run Length Limited (hereinafter as RLL) swiftly and precisely so as to record data in a record medium. To achieve the method and apparatus, the digital data modulating method includes the steps of comparing a preset critical value and DSV of a certain digital data stream, computing the penalty of the digital data stream by multiplying the number of the time that the DSV of the digital data stream is larger than the critical value by a preset weight value of the critical value and comparing the penalty of the digital data and a penalty of another digital data stream and determining a digital data stream with a smaller penalty for the digital data stream.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. Two redundant bits are added to every prescribed number of the successive generated output code words for digital-sum-variation control. The generated output code words and the added redundant bits are sequentially connected into a redundant-bit-added output-code-word sequence which follows predetermined run length limiting rules (1, k)RLL, where “k” denotes a predetermined natural number equal to 9.

Abstract: Methods of encoding and decoding as well as an encoder and decoder are provided for encoding data words into codewords and decoding codewords into data words. The data words are encoded by mapping each data word into a number of data segments. Each data segment is then encoded to form a codeword segment that has the same number of bits as the data word segment. The codeword segments are concatenated to form the codeword. The codewords are decoded by decoding individual codeword segments into data word segments that are the same size as the codeword segments. The data word segments are then mapped into the data word, which has fewer bits than the total number of bits across all data word segments.

Abstract: A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than l and N is an integer that is greater than M. Two codes are described for the encoding and decoding processes: a rate (2/6) code and a rate (2/8) code. In general, block encoding and block decoding maps between M servo data bits and N coded symbol bits. Such block encoding with a rate (M/N) code may be employed in a magnetic recording system for encoding servo data that is written to a servo data sector on a magnetic recording medium. Encoded servo data is read from the magnetic medium and block decoded. A forced maximum-likelihood, partial-response (PRML) detector is used to detect the N coded symbol bits from channel samples read from the magnetic medium. Block encoding provides greater coding gain for a detector when the characteristics of the block code are used to improve performance of the PRML detector that is used to detect the N coded symbol bits.

Abstract: The invention relates to an information carrier comprising runlength limited marks in a track. The runlengths of the marks represent main channel bits and variations of a further parameter of the marks representing secondary channel bits. Not all marks have said variations, only marks of at least a predetermined runlength have said variations.

Abstract: The present invention describes a system and method for encoding a sequence of 64 bit digital data words into a sequence of 65 bit codewords having constraints of (d=0, G=11/I=10) for recording upon a magnetic medium within a magnetic recording channel are disclosed. The method for encoding a sequence of 64 bit digital data words into a sequence of codewords having 65 bits, comprising the steps of dividing each 64-bit digital data word into 8-bit bytes, encoding two 8-bit bytes to form a 17-bit word, forming five 11-bit intermediate blocks from the 8-bit bytes, encoding the five 11-bit intermediate blocks, and concatenating the five encoded 11-bit intermediate blocks and uncoded and unconstrained bits from the 64 bit digital data word to form a 65 bit codeword. A corresponding decoding method is also described. A byte shuffler may be used in the processing.

Abstract: Coding a data stream comprising: channel coding (11) respective partitions of a given part of the data stream with different error protection rates to obtain a coded data stream (WS1), and including (20, 14) length information (lf) concerning respective lengths of the respective partitions in the coded data stream (WS1).

Abstract: A method of converting a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal. This stream of databits of the information signal is divided into n-bit information words. These information words are converted into m1-bit channel words in accordance with a channel code C1, or m2-bit channel words in accordance with a channel code C2, where m1, m2, and n are intergers such that m2>m1≧n. The m2-bit channel word is chosen from of at least two m2-bit channel words, at least two of which have opposite parities. The concatenated m1-bit channel words and the m2-bit channel words comply with a runlength constraint of the constrained binary channel signal. The constrained binary channel signal may be recorded on a record carrier.

Abstract: A digital data modulating method wherein the last unit of a block consisting of predetermined units is received and a block is obtained which does not infringe the k-constraint in the RLL code having the (d, k) constraints on the basis of a modulation data table of a predetermined unit. The source code word to be modulated to a code word can be quickly and accurately determined while satisfying the (d, k) constraint of the RLL code between the blocks having a predetermined size.

Abstract: In this invention a thirty three bit word is encoded from a thirty two bit word to conform to RLL coding constraints. A parity bit is added to the coded word after coding is complete. With the parity bit inserted the code satisfies a minimum Hamming weight of nine and no more than eleven consecutive zeros and no more than eleven consecutive zeros in both the odd and even interleaves. A table of “bad” eight bit sequences is used to compare the odd and even interleaves of the right and left halves of the input word that is being encoded. If a “bad” sequence is found, its position in the table points to a second table containing a four bit replacement code that is inserted into the coded output word. Flag bits in the output coded word are set to indicate the violation of the coding constraints and provide a means by which a decoder can be used to reverse the process and obtain the original input word.

Abstract: In some embodiments, the invention involves a circuit including a first set of conductors to carry a current bit set and last bit set circuitry to hold and provide a last bit set. The circuit also includes drivers coupled to interconnect conductors to provide signals from the drivers to the interconnect conductors and an encoder to receive the last bit set and the current bit set and determine whether to provide the current bit set or an encoded version of the current bit set to the drivers.

Abstract: A data modulating/demodulating method and apparatus for an optical recording medium that is capable of keeping a digital sum value at a minimum value. In the method, a source data is converted into a coded data by a first conversion table in which the coded data corresponding to the source data is registered. The coded data is converted into a first channel data suitable for the optical recording medium. A second conversion table is registered with a coded data for suppressing a DC component in correspondence with a specific source data such that a digital sum value of the first channel data becomes a minimum value. The specific source data is converted into the coded data for a direct current restraint by the second decoding table and then converted into a second channel data. A digital sum value for the first and second channel data is calculated to select a coded data in which the digital sum value becomes a minimum value from the first and second conversion tables.

Abstract: A method of modulating and a method of demodulating for a run length limited (RLL) code having an improved direct current (DC) suppression capability. Received data is modulated using a DC suppression control code group which is separate from a data modulation conversion code group. The DC suppression control code group maximizes use of the characteristics of codewords in conversion code groups, such as, the sign of parameter CSV representing the DC value within a codeword and the characteristics of parameter INV predicting the DSV transition direction of the next codeword, while relaxing the redundant codeword generation condition or the condition of usable codewords compared with the data modulation conversion code group. Therefore, the number of codewords increases, so that the probability of DC suppression control further increases.

Abstract: A method encodes an input data block with a block encoder. The block encoder is capable of processing consecutive coding blocks whose size has an upper limit which is smaller than the size of the input data block. The method comprises: determining the length of the input data block before encoding any of its data with the block encoder; dividing the input data block to a plurality of segments wherein all segments are of substantially equal size and no segment is larger than the upper limit; and processing each segment with the block encoder. If the last segment is shorter than the remaining segments, fill bits can be added to the last segment such that its length equals that of the remaining segments.

Abstract: A communication system is provided for interconnecting a network of digital systems. Each node of the communication system may include a transceiver and an encoder/decoder. The encoder codes an incoming data stream and forwards the encoded data stream across a communication link based on a DC-adaptive encoding mechanism. The encoded data stream is substantially free of a DC value that would skew the detector components at the receiver end of the communication link. Moreover, the encoded signal is forwarded at no greater than the incoming bitstream. Encoding occurs dependent on a digital sum value of the preceding clock cycle (DSVn−1) for the encoded bitstream and the logic values for the incoming bitstream during the current clock cycle n as well as the subsequent clock cycle n+1. Encoding according to normal encoding or multiple-ones encoding is dependent on those values.

Abstract: A system and method are provided for encoding from decimal to binary and back again. The coding is based on representing 3 decimal digits as 10 binary bits and is a development of the Chen-Ho algorithm. This provides a storage efficiency of >99%, yet still allows decimal arithmetic to be readily performed. The decimal input is typically first converted to binary coded decimal (4 bits per decimal digit), before compression to 10 bits. Adopting the encoding of the present invention, if the leading (most significant) decimal digit is zero, then the first three bits of the binary output are zero; and if the first two decimal digits are zero, then the first six bits of the binary output are zero. Accordingly, the same coding can be flexibly used to code 2 decimal digits to 7 binary bits, and 1 decimal digit to 4 binary bits. This makes it particularly suitable for standard computer architectures which are based on a power of two (16-bit, 32-bit, 64-bit, etc), and therefore not directly divisible by 7 or by 10.

Abstract: A method for designing a computer program for finding a low-complexity coder for constrained block codes for application to timing recovery or error control in data recording systems. The method includes (1) decomposing an input set of candidate codewords into simple subsets of codewords, (2) providing, for each simple subset of codewords, a respective subset of datawords, and (3) filling in certain coordinates in the datawords by values of certain coordinates in the codewords.