Abstract: An encoder for enabling selection of output bits that reduce run-length includes classification circuitry, a disparity control circuit, encoding circuitry, and a run-length control circuit. The classification circuitry is configured to receive data in a first bitwidth. An output of the classification circuitry is in communication with the disparity control circuit. The encoding circuitry is configured to encode the data received in the first bitwidth into a second bitwidth. The run-length control circuit is included in the encoding circuit and is selectively triggered in one coding scheme when a contiguous portion of the data of the first bitwidth is of a particular sequence, e.g., all logic ones, to generate a control signal. The run-length control circuit receives as additional inputs outputs of a portion of the encoding circuitry and a disparity signal from the current encoding cycle. The control signal, when generated, reduces run-length of the second bitwidth.

Abstract: On the transmitter side, an enhancement layer is hierarchized by expanding a coefficient of orthogonal transformation to a plurality of bit planes or designating a coefficient position in a block. Then, only a coefficient in a position designated by coefficient position information is encoded and streaming distribution is performed. On the receiver side, the coefficient block is restored using the coefficient position information.

Abstract: A method of decoding an encoded bitstream. The method includes performing a table lookup. Addresses into the table are generated using selected numbers of bits drawn from the bitstream in response to values stored in the table entries. A table entry may contain an index offset and a number of bits to extract from the bitstream. Alternatively, the table entry may contain the decode result. The value of a result tag in the entry signals which of the alternatives is contained in the entry. The table is recursively accessed until a portion of the bitstream is decoded. Any remaining portion of the bitstream is decoded similarly. An initial index into the table is determined from a number of bits of the bitstream corresponding to the length of the smallest code word in the codetable used to encode the bitstream.

Abstract: A data conversion apparatus of this invention has a storage unit configured to store a conversion table to convert m-bit data into n-bit data, and a conversion unit configured to convert the m-bit data into the n-bit data by using the conversion table stored in the storage unit. The conversion table contains a plurality of bit conversion codes to convert the m-bit data into the n-bit data. The bit conversion code is a code which converts the m-bit data into the n-bit data that allows the minimum number d of consecutive “0” bits between “1” bits.

Abstract: A serial data transmission system in which a transmitter encodes data in accordance with a TMDS-like encoding algorithm and transmits the TMDS-like encoded data over a serial link to a receiver. The encoded data are transmitted as a run length limited (“RLL”) code word sequence, including transition-minimized code words. In some embodiments, the RLL code word sequence includes only Min words, including both DC balancing Min words and DC unbalancing Min words. In other embodiments, the RLL code word sequence includes both transition-maximized code words and transition-minimized code words. Other aspects of the invention are circuitry and methods for TMDS-like encoding of data for transmission as an RLL code word sequence.

Abstract: A digital-to-analog converter having a differential signal path, and a current parking circuit that is independent of the signal path, thereby avoiding a source of imbalance that caused output anomalies in conventional digital-to-analog circuitry. In one embodiment of the invention, a pair of diodes in the current parking circuit are connected through their own independent load resistors to a voltage source. In another embodiment, a single diode is used instead of the pair of diodes, and in a third embodiment the current parking circuit comprises a single load resistor connected to the voltage source, and no diodes at all.

Abstract: A data dependent scrambler (DDS) for a communications channel that transmits a user data sequence having a plurality of symbols includes a scrambler that generates a scrambled user data sequence that is based on the user data sequence and a seed. A first encoder selectively interleaves adjacent symbols in the scrambled user data sequence if an all-zero symbol is produced by bit interleaving. The first encoder identifies a pivot bit that is adjacent to the all-zero symbol if interleaving is performed and replaces the all-zero symbol with an all-one symbol if the pivot bit is zero.

Abstract: There is disclosed a synchronous signal generating method, recording apparatus, transmitting apparatus, recording medium and transmission medium in which a plurality of coding tables is used to convert an input data word of p-bits to a code word of q-bits (q>p), and a code word string obtained by directly coupling the code words is recorded and reproduced in a recording medium such as an optical disk and magnetic disk, or transmitted via a transmitting portion. A synchronous frame consists of a synchronous signal and the cord word string satisfying restriction on minimum run length and maximum run length.

Abstract: Circuitry for detecting excessive runs of similar bits of data in a data stream is provided. The data stream is typically received as serial data operating in a serial clock domain. Run-length detection circuitry checks the received data for run-length violations while operating in a slower parallel clock domain, as opposed to the faster serial clock domain. An advantage of operating run-length detection circuitry in the parallel domain is that longer length run-length violations can be searched for in the received data, as compared to run-length detectors that operate in the serial domain. Another advantage offered by the circuitry is that the run-length violation signal can be provided to utilization circuitry asynchronously. This enables utilization circuitry to quickly capture the signal despite differences in clock domains (i.e., the clock domain of the detection circuitry and the clock domain of the utilization circuitry).

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1(b2)(b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

Abstract: A method and apparatus for modulating data modulates data having a length of m-bits to a variable length code having a basic code length of n-bits. A SYNC but insertion section adds a sync signal to a train of codes, after a minimum run. The sync signal has a pattern that breaks a maximum run.

Abstract: A transmission code which packs six bits of data and four control vectors into an eight-hit format is presented. A direct current (DC)-balanced 6B/8B transmission code is produced from an input data stream that includes one or more six-bit source vectors. A given coded vector is created in accordance with an eight binary digit coded vector set. The given coded vector has eight binary digits and the given coded vector corresponds to a given six-bit source vector. Each coded vector in the eight binary digit coded vector set is balanced. The given coded vector is output.

Abstract: A method of encoding digital information in a system is provided. The method includes receiving a sequence of user-bits and calculating a running digital sum (RDS) of the system. Also, a code word is generated based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range. In one embodiment, the sequence of user bits is 19 bits and the code word is 20 bits.

Abstract: An adapter configured to automatically detect and compensate for differential signal inversion is herein disclosed. In one embodiment, the adapter is part of a computer network having differential conductor pairs conveying differential signals between network devices. The network devices include adapters coupled to transmit and receive signals via the differential conductor pairs. The adapter preferably includes a lane receiver, a decoder, and a synchronization circuit. The lane receiver is configured to receive a single differential signal and to convert the differential signal into a sequence of code symbols. The decoder decodes the code symbols to produce a sequence of received symbols. The synchronization circuit examines the sequence of received symbols to determine if it is incorrect due to inversion of the differential signal, and if so, it causes the lane receiver to correct for the differential signal inversion.

Abstract: In a code modulating method and a code modulating apparatus, a run length has an encoding rate of ? which is equal to that of (1, 7) modulation, and indicates the number of “0” bits between adjacent ones of “1” bits in the channel bit train. A data bit train is converted into the channel bit train so that the run length has a minimum value 1 and a maximum value 10. Further, upon converting any data bit train, the channel bit train does not include a pattern “1010101010101” in which the run length 1 is continuously repeated six times or more. The channel bit train has a DSV (Digital Sum Value) control bit which selects the “0” bit or “1” bit in accordance with a DSV. The channel bit train obtained by using random data for the data bit train is NRZI converted into a signal. A frequency component of the signal is reduced from a maximum value of the frequency component by 20 dB or less as a power density at a frequency of {fraction (1/10,000)} or less of a channel clock frequency.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1 (b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

Abstract: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.

Abstract: Methods of encoding and decoding, as well as an encoding system and a digital communications system are provided for encoding data words into code words and decoding code words into data words. The data words are encoded according to a run-length-limited (RLL) code of “k” constraint, the encoding producing u-bit non-zero code words. The “k” constraint can be increased to a higher value by extending the u-bit non-zero code words to generate q-bit non-zero code words.

Abstract: An ultra-wideband pulse modulation apparatus, system and method is provided. The pulse modulation method increases the available bandwidth in an ultra-wideband, or impulse radio communications system. One embodiment of the present invention comprises a pulsed modulation system and method that employs a set of different pulse transmission, or emission rates to represent different groups of binary digits. The modulation and pulse transmission method of the present invention enables the simultaneous coexistence of the ultra-wideband pulses with conventional carrier-wave signals. The present invention may be used in wireless and wired communication networks such as CATV networks.

Abstract: A method and apparatus of converting a series of data words into modulated signals generates for each data words, a number of intermediate sequences by combining mutually different digital words with a data word, scrambles the intermediate sequences to form alternative sequences, translates each alternataive sequence into a (d,k) constrained sequences, measures for each (d,k) constrained sequences, not only an inclusion rate of an undesired sub-sequence but also a running DSV (Digital Sum Value), and selects one (d,k) constrained sequence having a small inclusion rate for recording on an optical or magneto-optical recording medium among the (d,k) constrained sequences having maximum value of running DSV, smaller than a preset limit. Accordingly, efficient DSV control can be achieved for even relatively-long sequences.

Abstract: A method and an apparatus for providing digital quality transmission of audio and non-audio information using low cost components and arrangement. The present invention provides for the transmission of the audio and non-audio transmission by first converting the data to conform to the CD standard format and conditioning the converted signal to thereby generate a conditioned EFM signal. The conditioned EFM signal is used to frequency modulate a carrier. By converting the audio and non-audio information to conform to the CD standard format, the present method provides a low cost means of transmitting the data with error detection and correction. Another aspect of the present invention relates to embedding the non-audio information in the SUBCODE block of the data frame according to the CD standard. The non-audio information may be unrelated to the audio information, and the audio and non-audio information may be transmitted to separate devices.

Abstract: The present invention relates to method and apparatus of converting a series of data words into modulated signals. This method divides a data word, which a sync signal is to be added in front or rear of when it is written in a recording medium, into two or more word segments, generates for each word segment a number of intermediate sequences by combining mutually different digital words with that word segment, scrambles these intermediate sequences to form alternative sequences, translates each alternative sequence into a (d, k) constrained sequence, checks how many undesired sub-sequences are contained in each (d, k) constrained sequence, and selects one (d, k) constrained sequence for recording on an optical or magneto-optical recording medium among the (d, k) constrained sequences not having the undesired sub-sequence. Applying this method to a modulating device, DSV control can be conducted by much simpler hardware.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (y1, y2, y3). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity inverting (table I) (FIG. 1). The relations hold that m>n≧1, p≧1, and that p is an odd integer that can vary. Preferably, m=n+1.

Abstract: An 8B/10B encoder/decoder including logic gates. The 8B/10B encoder including logic gates including a 5B/6B encoding block to compute 6 bit output data, in which the number of ‘0’s and the number of ‘1’s are balanced, from 5 bit input data; a 3B/4B encoding block to compute 4 bit output data, in which the number of ‘0’s and the number of ‘1’s are balanced, from 3 bit input data; and a disparity computation block to create and output a disparity in response to outputs and clocks of the 5B/6B encoding block and the 3B/4B encoding block. Thus, an 8B/10B encoder/decoder including logic gates uses a two-group logic combination method with emphasis on speed rather than size. The minimum number of stages for data processing at logic gate level guarantees more stable and fast operation.

Abstract: A set of processes are disclosed for compressing and decompressing bitmapped picture files that are to be stored for later display within a control for an HVAC system. The compression process includes an examination of the first bitmapped pixel in a given bitmapped file followed by a counting of the number of consecutive pixels having the same state as the first pixel. The process continues with analyses of successive numbers of pixels of first one state and then another state and generating a numerical representations as to each number of so counted pixels until the last pixel of the bitmapped picture file data is analyzed. The resulting compressed file is stored in a memory within a control for an HVAC system so that the file can thereafter be read when the file is to be displayed.

Abstract: Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream.

Abstract: A run length limited code recording/reproduction apparatus according to an aspect of this invention includes a generation unit for generating a plurality of different code sequences which have recording densities that gradually become higher, and a recording unit for recording the plurality of different code sequences generated by the generation unit on a plurality of successive subfields in a test data field of an information storage medium.

Abstract: The invention relates to a modulation code system, including an encoder and a decoder and two corresponding modulation code methods. More specifically, the encoder 100 serves for transforming an original signal s into an encoded signal c satisfying predefined second constraints. Such encoder signals are, for example, transmitted via a channel 300 or stored on a recording medium. After receipt or restoration, said encoded signal c is decoded by a decoder 200 in order to regenerate the original signal s again. It is the object of the present invention to improve the known modulation code systems and methods in such a way that their embodiment requires less hardware. This object is solved in that the encoder 100 comprises a series connection of a modulation code encoder 110 and of a transformer encoder 120 allowing an N-time integration of the output signal of said modulation code encoder 110.

Abstract: A digital signal modulation method selects a modulation strategy to modulate current M sets of data by determining variations in a digital sum value (DSV) corresponding to the modulated data modulated according to a first modulation strategy from M sets of data ahead of the current M sets of data.

Abstract: For encoding a current data word to be encoded, a most suitable redundant signal for the current data word to be encoded is generated by referring to a next data word to be encoded, that is, using a look-ahead decision method. The current data word to be encoded is encoded by using this redundant signal. A low-frequency component of the encoded data is effectively suppressed without decreasing encoding efficiency, by using both a regular substitution code and a stochastic substitution code, and a look-ahead determination algorithm for changing the length of words of a data segment, based on stochastic occurrence of a substitution word.

Abstract: Disclosed is a method of compressing data contained in variable length or universal variable length code words to be carried in a digital bitstream. The method includes formatting a first set of code words for data and then constructing a second set of code words containing code words from the first set as well as concatenations of code words from the first set. Code words from the second set are to carry data in compressed form in the digital bitstream. One way in which the concatenation is accomplished includes selecting a code word from said first set of code words and applying it as a prefix to itself and to all of the other words in the first set, thereby constructing the second set. The code word selected from the first set for application as a prefix may be the shortest code word of the first set.

Abstract: The present invention relates to a method for compensating asymmetry in a reproduction signal DRSO from an optical recording medium, and to an apparatus for reading from and/or writing to optical recording media using such method. It is an object of the invention to propose a method for compensating an offset in an asymmetric reproduction signal DRSO capable of compensating the offset even if the amplitude of the shortest run-length components is smaller than the asymmetry of the reproduction signal DRSO. This object is achieved by a method for compensating an offset in an asymmetric reproduction signal, whereby an offset compensation signal OFS is subtracted from the reproduction signal DRSO, the offset compensation signal OFS being generated by an offset compensator 11, comprising the steps of: detecting a binary data signal NRZ from the asymmetric reproduction signal DRSO; and using the binary data signal NRZ for obtaining the offset compensation signal OFS.

Abstract: A data conversion apparatus of this invention has a storage unit configured to store a conversion table to convert m-bit data into n-bit data, and a conversion unit configured to convert the m-bit data into the n-bit data by using the conversion table stored in the storage unit. The conversion table contains a plurality of bit conversion codes to convert the m-bit data into the n-bit data. The bit conversion code is a code which converts the m-bit data into the n-bit data that allows the minimum number d of consecutive “0” bits between “1” bits.

Abstract: Data modulating/demodulating method and system and apparatus using the same. The modulation method with smaller modulation table, compared to the conventional modulation table, is used to modulate the source data to the channel bits to be recorded to an external storage apparatus, such as optical disc. The demodulation method with smaller demodulation table, compared to the conventional demodulation table, is used to demodulate the bit data stream recorded on a storage apparatus, such as optical disc, to the original source data.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1(b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords.

Abstract: The invention relates to a method and device for adding or extracting a secondary information signal to/from a runlength-limited code sequence. A polarity of a runlength at a first predetermined position of the runlength-limited code sequence is detected and a parameter reflecting the degree of freedom that is present in the runlength-limited channel code, e.g. the selection of a merging bit pattern in the CD-standard, is set on the basis of the detected polarity so as to obtain a predetermined polarity of a runlength at a subsequent second predetermined position of the runlength-limited code sequence. The predetermined polarity then corresponds to a binary value of the secondary information. Thus, a side-channel with a small capacity is provided, which is positioned very close to the physical channel such that the secondary information is hard to be detected from the EFM bit stream. Therefore, the side-channel can be used as a hidden channel for copy protection purposes.

Abstract: An encoding and decoding method of record medium having the concept of type and set is disclosed. The disclosed not only satisfy the DK-Constraint, the coding rate and DC-free control are better through the auxiliary conditions of type dependency and digital sum value. The available storage space of the record medium consequently increases. In the decoding procedures, the accuracy and efficiency are better through the auxiliary conditions of type dependency and forbidden type set. Thus, the decoding error consequently decreases.

Abstract: An EFM/EFM+ encoding system is adapted to modulate a source symbol sequence into a modulated bit sequence that is further converted to a channel bit sequence, which is to be recorded on a recording medium and which has a cumulative Digital Sum Value (DSV), through NRZI conversion. An apparatus for performing DSV protection in the EFM/EFM+ encoding system includes a DSV calculation unit for calculating the DSV associated with the EFM/EFM+ modulated bit sequence, and a decision unit for adjusting at least a bit in the modulated bit sequence according to the result calculated by the DSV calculation unit such that the channel bit sequence from the NRZI conversion of the adjusted modulated bit sequence accumulates a relatively small DSV. A method of using the EFM/EFM+ encoding system to inhibit disc copying is also disclosed.

Abstract: A method and apparatus of converting a series of data words into modulated signals generates for each data word, a number of intermediate sequences by combining mutually different digital words with that data word, scrambles the intermediate sequences to form alternative sequences, translates each alternative sequence into a (d,k) constrained sequence, measures for each (d,k) constrained sequence, not only an inclusion rate of undesired sub-sequence but also a running DSV (Digital Sum Value), and selects one (d,k) constrained sequence having small inclusion rate for recording on an optical or magneto-optical recording medium among the (d,k) constrained sequences having maximum value of running DSV. smaller than a preset limit. Accordingly, efficient DSV control can be achieved for even relatively-long sequences.

Abstract: Aspects of the invention relate to providing a secondary communication channel overlaid on a primary communication channel, using an enhanced encoding method, to effectively expand the utilized information capacity of the primary communication channel. Aspects of the invention may include encoding a portion of at least a first word of one or more packets in a datastream. A running disparity of the encoded word may be reversed. Hence, if an encoded running disparity of an encoded word is RD positive RD(+), then the running disparity is reversed to RD negative RD(−). Similarly, if an encoded running disparity is RD negative RD(−), then the running disparity is reversed to RD positive RD(+). The word may be a data word, control word or an idle word corresponding to a data packet, a control packet and an idle packet, respectively.

Abstract: Clock information related to a reference clock is distributed from a master network node to a slave network node in an asynchronous packet-based network by embedding the clock information into an additional bit stream and multiplexing the additional bit stream with a primary data stream using an out-of-band channel. Multiplexing the additional bit stream with the primary bit stream using an out-of-band channel may involve selecting yB codes of an xB/yB encoded bit stream to represent bits of the additional bit stream or to balance the running disparity of the xB/yB encoded bit stream. The clock information that is embedded into the additional bit stream is used to generate a clock that is synchronized with a reference clock. In an embodiment, the clock information represents the time difference between a transmitted frame of the additional bit stream and a next edge of the reference clock.

Abstract: This invention relates to a digital modulation method and apparatus used for recording an audio or video signal, computer data, and etc on a recording medium such as an optical or magneto-optical disc. Data words of m bits are translated into code words of n bits in accordance with a conversion table. The code words satisfy a (d, k) constraint in which at least d “0”s and not more than k “0”s occur between consecutive “1”s. The n-bit code words alternate with p-bit merging words which are selected such that between the leading “1” in the code word following the merging word and the trailing “1” in the merging word are at least d “0”s, and further that between the trailing “1” in the code word preceding the merging word and the leading “1” in the merging word are at least d “0”s.

Abstract: Managing a primary bit stream involves converting a qB/rB encoded bit stream to an xB/yB encoded bit stream and multiplexing an additional bit stream with the xB/yB encoded bit stream at a transmission side of a link. The additional bit stream is then demultiplexed from the xB/yB encoded bit stream and the xB/yB encoded bit stream is converted back to the qB/rB encoded bit stream at the receiver side of the link. The qB/rB encoded bit stream is converted to and from the xB/yB encoded bit stream so that the additional bit stream can be multiplexed with the qB/rB encoded bit stream using multiplexing/demultiplexing systems that are compatible with the xB/yB multiplexing system. In an application, a 4B/5B encoded bit stream is converted to an 8B/10B encoded bit stream and an additional bit stream is multiplexed with the 10B code-words of the 8B/10B encoded bit stream using code-word manipulation.

Abstract: An input bit stream is encoded into a stream of output code words according to variable-length encoding rules using a variable constraint length. The output-code-word stream observes prescribed run length limiting rules RLL(d, k). Every m-bit piece of the input bit stream is encoded into an n-bit output code word by referring to predetermined M encoding tables following the variable-length encoding rules. CDS (code word digital sum) values are calculated which correspond to respective n-bit output code words. DSV (digital sum variation) control bits are generated in response to the calculated CDS values. The generated DSV control bits are periodically inserted into the input bit stream at intervals each corresponding to a prescribed number of successive bits. The input bit stream is subjected to variable-length encoding while DSV control is implemented in response to the inserted DSV control bits.

Abstract: During decoding and encoding, the starting disparity of a current block is computed by using a disparity at some previous reference point and disparity characteristics of bytes from the reference point to a current block boundary. The characteristics of the bytes are whether the bytes are unbalanced coded vectors and whether the number of unbalanced vectors is even or odd. Alternately, the characteristics of the bytes are whether the bytes are balanced and how many balanced coded vectors exist. New classifications are created for encoding and decoding 3B/4B and 5B/6B transmission codes. Separate functions are created that address specifically disparity aspects. A dispartiy violation at the front of a byte is detected during decoding by comparing a required front-end disparity of the byte with the actual running disparity by assuming the actual running disparity is equivalent to an exit disparity of the next preceding byte that is disparity dependent.

Abstract: A coding system that in a first embodiment is capable of encoding 16-bit input words into even parity 17-bit codewords, wherein the codewords have at least 7 ones, wherein the codewords has an 8-bit first half and a 9-bit second half, wherein the first half has at least 3 or more ones, and wherein the second half comprises at least 3 or more ones. The first half and second half of the codewords each have odd-coordinate bits and even-coordinate bits, at least one odd-coordinate bit of each half has a value of one, and at least one even-coordinate bit of each half has a value of one. In a second embodiment, the coding system is capable of encoding 16-bit input words into even parity 17-bit codewords, wherein the codewords have at least 7 ones, wherein the codewords have an 11-bit first half and a 6-bit second half, wherein the first half comprises at least 3 or more ones, and wherein the second half has at least 2 or more ones.

Abstract: A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than 1 and N is an integer that is greater than M. Two codes are described for the encoding and decoding processes: a rate (2/6) code and a rate (2/8) code. In general, block encoding and block decoding maps between M servo data bits and N coded symbol bits. Such block encoding with a rate (M/N) code may be employed in a magnetic recording system for encoding servo data that is written to a servo data sector on a magnetic recording medium. Encoded servo data is read from the magnetic medium and block decoded. A forced maximum-likelihood, partial-response (PRML) detector is used to detect the N coded symbol bits from channel samples read from the magnetic medium. Block encoding provides greater coding gain for a detector when the characteristics of the block code are used to improve performance of the PRML detector that is used to detect the N coded symbol bits.

Abstract: Disclosed is a method for satisfying both high reliability and low error rate when in recording and reproducing information by making the average run length of the RLL code for recording a crystal state shorter than that for recording an amorphous state on a recording film, although the consistence of both high reliability and low error rate has been difficult in the case of conventional optical disks.

Abstract: A method for run-length encoding two or more data values, the method comprising: loading the data values into storage by forming a first data string, the data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values; generating a second data string having a data sub-string corresponding to each data sub-string of the first data string, all the bits of each of the data sub-strings of the second data string having a first predetermined value if all the bits of the corresponding data sub-string of the first data string have a second predetermined value and having a third predetermined value if any of the bits of the corresponding data sub-string of the first data string has other than the second predetermined value; starting from a predetermined end of the second data string, counting the number of consecutive bits of the second data spring having the first predetermined value; and dividing the said number by the number of bits in each data sub-strin

Abstract: A recording medium for a computer contains sectors, each of which represents a section of data that has originally been supplied by a user. As the user data is sent to the recording medium from the memory of the computer, an adjust bit determining circuit determines the adjust bit for a block of the write data. The adjust bit-value is such that the sum of the DC levels for the write data at a given point is equal to zero or approaches zero. The user data is converted using RLL(1,7) codes and PWM is performed to derive the write data. The circuit includes an encoder for receiving the user data two bits at a time. The encoder outputs DSV values for the 2-bit user data. A first circuit group for accumulating the DSV values from the encoder is used acquire block DSV values of data belonging to the plurality of blocks of the data section. A second circuit group accumulates these block DSV values computed by the first circuit group and calculates a temporary sector DSV value.