Abstract: A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.

Abstract: A codeword for use in a communication channel is provided. A first segment of the codeword includes a plurality of bits having a running digital sum (RDS) and a second segment includes a plurality of bits based on the RDS of the first segment.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1(b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

Abstract: A method and apparatus are provided for encoding and decoding digital information. A sequence of data words is received, wherein each data word has a running digital sum (RDS). The sequence of data words is encoded into a sequence of corresponding code words, which has a current RDS. For each data word a binary symbol is added to the data word and the data word is selectively complemented as a function of the RDS of the data word and the current RDS of the sequence of code words to form the corresponding code word.

Abstract: A system and method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium, includes encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, each set of P symbols being selected to reduce full-swing transitions and to perform DC balancing between successive digital signal transmissions. The system and method further includes transmitting the sets of P symbols over the single transmission medium. Clock data recovery and comma insertions may additionally be provided in alternate configurations.

Abstract: A method of generating an 8B/10B-like code bit sequence that is similar to an 8B/10B code may include: generating a parallel pseudo random bit sequence having N bits wherein N is an integer and N?2; and transforming the parallel pseudo random bit sequence into a parallel first bit sequence that is similar to an 8B/10B code, a number Q of consecutive “0”s or “1”s of the first bit sequence being Q?M1, wherein Q and M1 are integers and M<N. Devices related to such a method are also provided.

Abstract: An encoding method of recording media is used to speed up the encoding procedure in a recording media. Different conditions of states and paths set in advance during the encoding procedure to simply the actual operation loading for possible paths in the look-ahead calculation, thereby achieving fast encoding. Using the method, the operation of the look-ahead calculation of an exponential growth is greatly reduced to a linear growth.

Abstract: Non-uniform modulation encoding techniques are provided to prevent data from containing bit patterns that are prone to errors during read back. Modulation encoding is performed on a data stream to remove error prone bit patterns. Unconstrained data, such as error check parity, that is inserted into the modulated data stream may contain error prone bit patterns. Stricter modulation constraints are enforced on bits that are next to the unconstrained data, than on the remaining bits. By enforcing stricter modulation constraints on these bits, an entire data bit stream can have a desired modulation constraint.

Abstract: Provided are a rate 13/15 MTR code encoding/decoding method and apparatus. The encoding method includes: generating a predetermined rate-13/15 MTR code in which 13-bit data corresponds to 15-bit data; outputting input 13-bit data as a 15-bit codeword according to the rate-13/15 MTR code; checking whether codewords satisfy a predetermined constraint condition by connecting the 15-bit codeword and a subsequent 15-bit codeword; and converting specific bits of the codewords if the codewords violate the constraint condition and not converting the codewords if the codewords do not violate the constraint condition. The rate-13/15 MTR (j=2, k=8) code includes: 8192 codewords obtained to prevent the number of consecutive transitions from becoming 3 at code boundaries in a modulation coding process. Data can be reliably reproduced with high write density, and a large amount of data can be stored in and reproduced from a magnetic recording information storage medium.

Abstract: A data-demodulating method for demodulating a variable-length code (d, k; m, n; r) having a basic code length of n bits to data having a basic data length of m bits. A train of codes is received, and a sync signal having a pattern that breaks a maximum run is detected. The pattern is repeated twice continuously and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in a termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.

Abstract: A method of modulating data having a basic data length of m bits, to a variable-length code (d, k; m, n; r) having a basic code length of n bits. A sync signal is added to a received train of codes after a minimum run. The sync signal has a pattern that is repeated twice continuously. The minimum run is repeated no more than six times; and the sync signal exhibits seven types of sync signal IDs, with any adjacent two bits of a sync signal ID being spaced apart by a distance of 2.

Abstract: Apparatus for modulating data having a basic data length of m bits, to a variable-length code (d, k; m, n; r) having a basic code length of n bits. A sync signal is added to a received train of codes after a minimum run. The sync signal has a pattern that is repeated twice continuously. The minimum run is repeated no more than six times; and the sync signal exhibits seven types of sync signal IDs, with any adjacent two bits of a sync signal ID being spaced apart by a distance of 2.

Abstract: A data-demodulating apparatus for demodulating a variable-length code (d, k; m, n; r) having a basic code length of n bits to data having a basic data length of m bits. A train of codes is received, and a sync signal having a pattern that breaks a maximum run is detected. The pattern is repeated twice continuously and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in a termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.

Abstract: A method and device for adding or extracting a secondary information signal to/from a runlength-limited code sequence, includes detecting a polarity of a runlength at a first predetermined position of the runlength-limited code sequence and setting a parameter reflecting the degree of freedom that is present in the runlength-limited channel code, e.g., the selection of a merging bit pattern in the CD-standard, on the basis of the detected polarity so as to obtain a predetermined polarity of a runlength at a subsequent second predetermined position of the runlength-limited code sequence. The predetermined polarity then corresponds to a binary value of the secondary information. Thus, a side-channel with a small capacity is provided, which is positioned very close to the physical channel such that the secondary information is hard to be detected from the EFM bit stream. Therefore, the side-channel can be used as a hidden channel for copy protection purposes.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: Output data of a multiplexer 11 is EFM-modulated by an EFM modulator 12. In the EFM modulation, merging bits that satisfy run length limit conditions Tmin=3 and Tmax=11 are selected. Among them, merging bits that converge DSV are selected. A run length controlling portion 13 detects a particular data pattern that causes DSV to increase as large as a data read error takes place and controls the EFM modulator 12 so that the run length limit conditions of the EFM are loosened. As a result, an increase of DSV is suppressed. Data is reproduced from a data recording medium on which the data has been recorded in such a manner and the reproduced data is decoded. The decoded data is re-encoded so as to record it to another recoding medium. When the data pattern is re-encoded, DSV increases. As a result, data cannot be correctly reproduced from the other recording medium. Consequently, a copying operation can be prevented.

Abstract: In the coding device and method, m-bit information words are converted into n-bit code words such that the coding rate m/n is greater than 2/3. The n-bit code words are divided into a first type and a second type, and into coding states of a first kind and a second kind such that an m-bit information word is converted into an n-bit code word of the first or second kind if the previous m-bit information word was converted into an n-bit code word of the first type and is converted into an n-bit code word of the first kind if the previous m-bit information word was converted into an n-bit code word of the second type. In one embodiment, n-bit code words of the first type end in zero, n-bit code words of the second type end in one, n-bit code words of the first kind start with zero, and n-bit code words of the second kind start with zero or one.

Abstract: A fast look-ahead path modulation apparatus, used in a recording medium modulation apparatus, reduces computation time during its look-ahead path modulation procedure. It is based on different selection criteria of predetermined states, paths and characteristics of modulation. Accordingly, the apparatus drastically reduces the amount of computation in a regular look-ahead path modulation apparatus. It also reduces hardware costs of the recording medium modulation apparatus and increases efficiency.

Abstract: A technique for constructing a dictionary word list for use in a data compressor is provided by determining a set of words that are included in the dictionary word list and sorting each subset of words having a common starting character by lengths of the words. Partitions are formed and identified based on the common starting character and word length, with each partition being stored in memory and indexed.

Abstract: An EFM data decoding method and apparatus thereof for optical disk system is provided. According to the method, a 14-bit data complying with the EFM modulation criteria but failing to correspond to a 8-bit data based on an EFM decoding table is transformed successfully by looking up an expanded EFM decoding table. The expanded EFM decoding table includes probable 8-bit data corresponding to the erroneous data complying with the EFM modulation criteria. Reliability of data reading is thus enhanced in the present invention.

Abstract: A method and system of lossless compression of integer data using a novel backward-adaptive technique. The adaptive Run-Length and Golomb/Rice (RLGR) encoder and decoder (codec) and method switches between a Golomb/Rice (G/R) encoder mode only and using the G/R encoder combined with a Run-Length encoder. The backward-adaptive technique includes novel adaptation rules that adjust the encoder parameters after each encoded symbol. An encoder mode parameter and a G/R parameter are adapted. The encoding mode parameter controls whether the adaptive RLGR encoder and method uses Run-Length encoding and, if so, it is used. The G/R parameter is used in both modes to encode every input value (in the G/R only mode) or to encode the number or value after an incomplete run of zeros (in the RLGR mode). The adaptive RLGR codec and method also includes a decoder that can be precisely implemented based on the inverse of the encoder rules.

Abstract: The DVD recording method is intended to increase the number of cycles allowed for recording on the disk an enormous number of times. This method comprises generating two data streams by using a plurality of code mapping variants prepared for coding input data, quasi-randomly selecting one of the plurality of code mapping variants, if absolute DSVs of the two streams are substantially equal, and converting into recording code sequences. This method prevents deterioration of the disk particularly in the management area and increases the number of cycles allowed for rewriting.

Abstract: A rate 7/8 MTR code encoding/decoding method and apparatus. The encoding method includes: generating a rate-7/8 MTR code for inputting 7-bit data and outputting a predetermined 8-bit codeword; checking whether codewords satisfy a predetermined constraint condition by connecting the 8-bit codeword and a subsequent 8-bit codeword; and if the codewords do not violate the constraint condition, not converting the codewords. The decoding method includes: checking whether the codewords satisfy a predetermined MTR constraint condition by connecting a current 8-bit codeword c(k) and a subsequent 8-bit codeword c(k+1); if the codewords violate the constraint condition, converting the codewords, and if the codewords do not violate the constraint condition, not converting the codewords; and decoding each converted 8-bit codeword into 7-bit data using a predetermined MTR code.

Abstract: A method and apparatus are provided for encoding successive data words into respective code words. Each data word is mapped into data segments that are constrained to a first number of bit patterns, which is less than a second number of bit patterns that satisfy a first constraint. The data segments are encoded into intermediate code word segments selected from a first set of the bit patterns that satisfy the first constraint, wherein at least some of the bit patterns in the first set violate a second constraint. The intermediate code word segments are encoded into respective code word segments by encoding the intermediate code word segments that violate the second constraint with code word segments selected from a second, different set of the bit patterns that satisfy the first constraint and the second constraint.

Abstract: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx<My (and particularly where Nx<My, but Nx>My?M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

Abstract: A system and a method for synchronizing running disparity values in a first computer and a data demapping device are provided. The method includes generating a plurality of data characters and a synchronization control character. The method further includes iteratively determining a first running disparity value based on each character of the plurality of data characters and the synchronization control character. The method further includes encapsulating a first plurality of data characters and the synchronization control character from a computer into at least one GFP data block and transmitting the GFP data block to data demapping device. The method further includes decoding the GFP data block to obtain the plurality of data characters and the synchronization control character and iteratively determining a second running disparity value based on each character of the plurality of data characters and the synchronization control character.

Abstract: A data converter (1) capable of reducing a size of the total implementation in a device is a processing apparatus that performs secret converting processing predetermined to input data with 64 bits, the data converter including a finite field polynomial cubing unit (10), data integrating units (11a) to (11d), (12) and (13), a first converter (14), a second converter (15), a data splitting unit (16), and a data integrating unit (17). The finite field polynomial cubing unit (10) performs cubing, on the 32 bits data, in the polynomial residue class ring with a value in the finite field GF (28) as a coefficient and respectively outputs data with 32 bits.

Abstract: An encoding system for encoding digital data for transmission through a communication channel is described, which includes a DCF encoder and a parity encoder operatively coupled to the DCF encoder. The DCF encoder is adapted to receive a first data sequence, and to generate a first DCF code word and a new running digital sum as functions of the first data sequence and a pre-existing running digital sum, wherein the new running digital sum is limited to a maximum absolute value. The parity encoder is operatively coupled to the DCF encoder, and adapted to receive the first DCF code word from the DCF encoder, and to generate a first interleaved parity code word as a function of the first DCF code word, and to provide the first interleaved parity code word to a channel.

Abstract: A method and system of lossless compression of integer data using a novel backward-adaptive technique. The adaptive Run-Length and Golomb/Rice (RLGR) encoder and decoder (codec) and method switches between a Golomb/Rice (G/R) encoder mode only and using the G/R encoder combined with a Run-Length encoder. The backward-adaptive technique includes novel adaptation rules that adjust the encoder parameters after each encoded symbol. An encoder mode parameter and a G/R parameter are adapted. The encoding mode parameter controls whether the adaptive RLGR encoder and method uses Run-Length encoding and, if so, it is used. The G/R parameter is used in both modes to encode every input value (in the G/R only mode) or to encode the number or value after an incomplete run of zeros (in the RLGR mode). The adaptive RLGR codec and method also includes a decoder that can be precisely implemented based on the inverse of the encoder rules.

Abstract: Provided is a method, system, and program for storing input groups of uncoded binary data on a storage medium. A plurality of uncoded data blocks in a data stream are received. An encoded data stream is obtained from concatenating successive encoded blocks such that the encoded data stream includes a predetermined bit pattern comprising a plurality of bits. The bit pattern always occurs within a first number of bits and two occurrences of a “1” or “0” occur within a second number of bits. The encoded data blocks are stored on the storage medium.

Abstract: The present invention relates to a method for coding a data stream, in which the digital sum value of the coded data stream should be close to zero and two alternative code words can be used for the coding at least for some of the possible data values. It is the object of the invention to propose a method for coding a data stream which provides for simple coding of the data stream while at the same time ensuring a digital sum value close to zero. According to the invention, the object is achieved by a method in which the digital sum value of the coded data stream is determined, this value is compared with a first or a second boundary value in dependence on the polarity of the coded data stream and a received data value is coded by a first or a second code word belonging to the respective boundary value in dependence on the result of the comparison.

Abstract: It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1–7. The comparators 1–7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1–OUT7 in the preceding conversion to generate the first and second setting signals CONT1A etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

Abstract: A data-modulating apparatus for modulating data having a basic data length of m bits, to a variable-length code(d, k; m, n: r) having a basic code length of n bits. A sync signal is added to a recieved train of codes after a minimum run, the sync signal having a pattern that breaks a maximum run. The pattern is repeated twice continuously, and the minimum run is repeated no more than six times. The first bit of the sync signal is “1” when the train of modulated codes that immediately precedes the sync signal is included in the termination table used to terminate, at a desired position, a code when less than a predetermined number of variable length codes are available.

Abstract: A method and associated decoder, system, device and storage means for decoding codewords of variable length from a bit stream, in which minimum and maximum lengths are defined for the codewords, wherein the bit stream is processed in parts, each part being subjected to a search for codewords, and where found codewords are decoded. At least partly overlapping fields are extracted from the bit stream part in such a way that the starting point of at least two fields is a possible starting point of a codeword in that part. In at least one field, the end of the codeword is searched, and the data related to the codeword is determined on the basis of the end point of the codeword. Data relating to at least one codeword is used to determine the occurrence of the codeword intended to be decoded in a field, and the found codeword is decoded.

Abstract: During decoding and encoding, the starting disparity of a current block is computed by using a disparity at some previous reference point and disparity characteristics of bytes from the reference point to a current block boundary. The characteristics of the bytes are whether the bytes are unbalanced coded vectors and whether the number of unbalanced vectors is even or odd. Alternately, the characteristics of the bytes are whether the bytes are balanced and how many balanced coded vectors exist. New classifications are created for encoding and decoding 3B/4B and 5B/6B transmission codes. Separate functions are created that address specifically disparity aspects. A dispartiy violation at the front of a byte is detected during decoding by comparing a required front-end disparity of the byte with the actual running disparity by assuming the actual running disparity is equivalent to an exit disparity of the next preceding byte that is disparity dependent.

Abstract: A disk apparatus has a reading unit which reads reflection light from a disk and outputting a read signal, an identifying unit which identifies whether the read signal has been modified in accordance with a first modulation rule or has been modulated in accordance with a second modulation rule and outputs an identification signal, an equalizing unit which applies a waveform equalizing process to the read signal, and a decoding unit which carries out likelihood decoding of the waveform equalized read signal according to the modulation rule indicated by the identification signal from the identifying unit, and outputs a reproduction signal.

Abstract: In the coding device and method, m-bit information words are converted into n-bit code words such that the coding rate m/n is greater than 2/3. The n-bit code words are divided into a first type and a second type, and into coding states of a first kind and a second kind such that an m-bit information word is converted into an n-bit code word of the first or second kind if the previous m-bit information word was converted into an n-bit code word of the first type and is converted into an n-bit code word of the first kind if the previous m-bit information word was converted into an n-bit code word of the second type. In one embodiment, n-bit code words of the first type end in zero, n-bit code words of the second type end in one, n-bit code words of the first kind start with zero, and n-bit code words of the second kind start with zero or one.

Abstract: There is disclosed a recording method for performing a DSV control while recording a recording signal generated by inserting a synchronous signal for decoding reproduction data into every predetermined number of code words in a code word string satisfying a predetermined run length restriction rule and to be outputted into a recording medium, when a plurality of coding tables are used to convert an input data word of p-bits to a code word of q-bits (q>p), and the code word string obtained by directly coupling the code words is recorded and reproduced in a recording medium such as an optical disk and magnetic disk, or transmitted via a transmitting portion, wherein the p-bits are 8 bits, the q-bits are 15 bits, and the predetermined run length restriction rule stipulates that a minimum run length of the signal obtained by NRZI-converting the code word excluding the synchronous signal is 3T, and a maximum run length is any one of 11T, 12T, 13T, and 14T.

Abstract: A method and apparatus are provided for encoding digital information. A sequence of successive data words are encoded into a sequence of successive code words according to a code, such that a running digital sum (RDS) of the sequence of successive code words is bounded and is constrained to predetermined, non-adjacent values at boundaries between the code words.

Abstract: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx<My (and particularly where Nx<My, but Nx>My?M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

Abstract: The present invention relates to a modulation apparatus and method and a DSV-control-bit generating method for suppressing an increase in circuit size of the modulation apparatus. When an input data stream is supplied to a DSV control bit determination unit 31, the DSV control bit determination unit 31 determines a DSV control bit to be inserted into the input data stream. Upon supplying the input data stream to the DSV control bit determination unit 31, the input data stream is simultaneously supplied to a delay processor 32. The input data stream is delayed for a predetermined delay time and supplied to a determined-DSV-control-bit insertion unit 33. The determined-DSV-control-bit insertion unit 33 inserts the DSV control bit determined by the DSV control bit determination unit 31 into a predetermined position of the input data stream supplied by the delay means and supplies the input data stream containing the DSV control bit to a modulator 34.

Abstract: A method of compressing a color image is provided. The color image comprises color data for a plurality of pixels. The method includes the step of obtaining red, green and blue pixel values of an object of interest in the image. A calculation is made of the complement of the red, green and blue values of the object of interest. Transformation coefficients are calculated which transform the complements of red, green and blue values of the object of interest into representations in a transformation color space. The transformation coefficients are applied to all the pixels in the image to thereby obtain a transformed data set representing the image having components along three mutually orthogonal axes (A, B and C herein) in a three-dimensional transformed color space. The transformed data set is scaled in accordance with the color quantization used in the system; e.g., the A, B and C values are between 0 and 255 for an 8 bit quantization. A compression algorithm, e.g.

Abstract: A method and apparatus of converting a series of data words into modulated signals generates for each data words, a number of intermediate sequences by combining mutually different digital words with a data word, scrambles the intermediate sequences to form alternative sequences, translates each alternataive sequence into a (d,k) constrained sequences, measures for each (d,k) constrained sequences, not only an inclusion rate of an undesired sub-sequence but also a running DSV (Digital Sum Value), and selects one (d,k) constrained sequence having a small inclusion rate for recording on an optical or magneto-optical recording medium among the (d,k) constrained sequences having maximum value of running DSV, smaller than a preset limit. Accordingly, efficient DSV control can be achieved for even relatively-long sequences.

Abstract: A system and method of forming RLL coded data streams with separator blocks has an RLL encoder and a channel encoder. The input code word is divided into data portions and a separator portion. The data portions are inserted into an output codeword without encoding. Each data portion is separated from a next data portion by a space. The separator portion is encoded into non-zero separator sub-matrices, which are stuffed into the spaces between the data portions. The separator portions and the data portions may be separately permuted without exceeding a maximum number of consecutive zeros.

Abstract: A pointer-based modulation coding method and apparatus are presented. The pointer-based modulation coding operates to produce, from an unconstrained data stream of data blocks to be delivered to a data channel, a constrained data stream which satisfies a code constraint of the data channel. The pointer-based modulation coding replaces code constraint violating bit sequences occurring in each data block with values that form a linked list in such data block.

Abstract: A method of and an apparatus for modulating data to be resistant to channel distortion. A space extending encoder performs a first code transformation to extend a run length of digitized data to a predetermined length and outputs the space-extended data. A multiplexer multiplexes the space-extended data and data transformed by a predetermined second code transformation. A format converter converts the multiplexed data into a predetermined format which is suitable for writing to a recording medium. The apparatus and method enable recorded data to be resistant to channel distortion, enable the data to be recorded with increased recording density, and enable the data written to the recording medium to be reproduced with improved reliability.

Abstract: A technique for improving the quality of digital signals in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted at more than two signal levels on a single transmission medium. The method may comprise encoding digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is formed to reduce full-swing transitions between successive digital signal transmissions.

Abstract: A method and apparatus reduces a DC level of an input word. The input word is divided into a plurality of components that include n symbols. The n symbols of the components are summed for each component. The component is encoded into a substitute component if a sum for the component exceeds a threshold. The components having a sum that does exceed the threshold are combined with at least one substitute component into an output word. An output word template is selected based on a number of substitute components and on a position that the substitute components originally occupied in the input word. The substitute components are inserted in the output word template. The components that have a sum that does not exceed the threshold are inserted in the output word template. Address and indicator symbols are inserted in the output word.