Abstract: The present invention pertains to a modulation apparatus and method in which the modulation apparatus is realized with a simple circuit structure and is easily applicable to other systems. A pattern conversion unit 32 converts data having a basic data length of 2 bits supplied from a DSV control bit determination and insertion unit 31 into a variable-length code having a basic code length of 3 bits in accordance with a conversion table. A minimum-run-length limitation code detection unit 33 detects, from a data sequence containing a DSV control bit, the position of minimum runs consecutive from a channel bit string converted by the pattern conversion unit 32. A consecutive-minimum-run replacement unit 34 replaces a predetermined portion of the channel bit string supplied from the pattern conversion unit 32 for a predetermined pattern based on the position information supplied from the minimum-run-length limitation code detection unit 33, and limits the minimum run length to a predetermined number or less.

Abstract: An encoded-bit-string generating unit generates a bit string encoded by scrambling an input bit string. A direct-current-component evaluating unit selects a bit string having a predetermined width in the bit string generated by the encoded-bit-string generating unit, while shifting bits one by one, and evaluates the direct-current component in the selected bit string. A bit-string extracting unit extracts a bit string with suppressed direct-current component, based on a result of an evaluation by the direct-current-component evaluating unit.

Abstract: A method and system of lossless compression of integer data using a novel backward-adaptive technique. The adaptive Run-Length and Golomb/Rice (RLGR) encoder and decoder (codec) and method switches between a Golomb/Rice (G/R) encoder mode only and using the G/R encoder combined with a Run-Length encoder. The backward-adaptive technique includes novel adaptation rules that adjust the encoder parameters after each encoded symbol. An encoder mode parameter and a G/R parameter are adapted. The encoding mode parameter controls whether the adaptive RLGR encoder and method uses Run-Length encoding and, if so, it is used. The G/R parameter is used in both modes to encode every input value (in the G/R only mode) or to encode the number or value after an incomplete run of zeros (in the RLGR mode). The adaptive RLGR codec and method also includes a decoder that can be precisely implemented based on the inverse of the encoder rules.

Abstract: Embodiments of the invention a signal processing method capable of realizing low decoding error ratio by using a simple configuration free from unnecessary redundant bits. In one embodiment, user data (512 bytes+additional data) input to an input terminal is RLL-encoded by a RLL encoder 1. The data from the RLL encoder—1 is entered into a symbol error correction encoder where 9-bit symbol encoding is done. Its RS code portion is RLL-encoded by a RLL encoder—2. Signal read from a magnetic disk is entered into a RLL decoder—2 where the RS code portion is RLL-decoded. The signal from the RLL decoder—2 is then entered into a symbol error correction decoder where random read/write errors, burst errors attributable to defects and other errors are corrected to produce a (user data+RLL) signal. This data is output to an output terminal after being decoded by a RLL decoder—1.

Abstract: A system of downconverting an intermediate frequency (IF) phase or frequency modulated signal to a digital baseband includes an N bit shift register circuit that receives a binary input as a 1-bit input sample data stream of an IF signal. A decimation circuit includes a memory and receives data from the N bit shift register circuit and stores N 1-bit binary samples as address bits and performs decimation, downconversion and filtering by accessing memory values at a predetermined rate.

Abstract: An error correction compensating ones or zeros string suppression system and method for use in a digital transmission system is herein disclosed. In digital transmission systems utilizing error control coding (ECC)/forward error correction (FEC) to reduce the number of bit errors in a bit stream, long strings of ones and zeros are easily suppressed by detecting a prohibited length of ones or zeros, and flipping a bit in the string of ones or zeros. This method and system removes the violation of the ones or zeros bit string requirement by flipping a bit in the string, while the receiving side utilizes the error correction capability of the ECC/FEC to correct the inverted bit.

Abstract: An apparatus for data recovery includes a multi-level comparison unit, a detection logic unit, and a data composer. The multi-level comparison unit compares an input signal with M different reference signal levels to generate M digital data, the number M being greater than or equal to 2. The detection logic unit is coupled to the multi-level comparison unit, and performs logic operations upon specified lengths over the M digital data obtained from the multi-level comparison unit. The data composer is coupled to the multi-level comparison unit and the detection logic unit. The data composer generates recovered data conforming with a run length encoding constraint based on the M digital data obtained from the multi-level comparison unit and the result obtained from the detection logic unit.

Abstract: At the preceding stage of a first one of two APP decoders that constitute a turbo decoder, there is provided a logarithmic-likelihood computing circuit that creates and outputs logarithmic likelihoods L(y?i|yi) of a reproduced signal y?i which is soft information. The first APP decoder has an APP decoding function of receiving logarithmic likelihoods L(y?i|yi) of the reproduced signal yi as well as a priori information as to code data c?i, updating the code data c?i and producing outputs of a posteriori probabilities according to trellis diagram information that satisfy constraints concerning an RLL modulation. Turbo decoding becomes compatible with the RLL demodulation, and a turbo decoding with high error-correcting capability is usable in reproducing channel data ai recorded onto a recording medium, which allows a recording density of the recording medium to be increased.

Abstract: A method for encoding a bit stream to meet a minimum bit transition requirement includes providing uncoded bits, determining whether the uncoded bits meet the minimum bit transition requirement, and replacing selected bits in the uncoded bits with replacement bits that meet the minimum bit transition requirement if the uncoded bits do not meet the minimum bit transition requirement, thereby encoding the uncoded bits into encoded bits that meet the minimum bit transition requirement.

Abstract: A signal includes a runlength limited (RLL) encoded binary d,k channel bitstream, parameter d defining a minimum number and k defining a maximum number of zeroes between any two ones of the bitstream, or vice versa. The signal further includes a number of sections of respectively N successive RLL channel bits, called RLL rows, each RLL row representing a row parity-check code-word, in which a row-based parity-check constraint for the RLL row has been realized. K sections of respectively N successive channel bits, called column parity-check rows, are located at predetermined positions of a group of M RLL rows. The column parity-check rows include column parity-check enabling channel words, each realizing a column-based parity-check constraint for all corresponding segments of at least the M RLL rows of the group that correspond to a specific column parity-check enabling channel word, thereby constituting a column parity-check codeword.

Abstract: The present invention provides a method and system for converting an input code into an output code. The method includes: determining a plurality of input code subsets of the input code; converting the input code subsets into a plurality of output code subsets, respectively; and merging the output code subsets to generate the output code. The system includes a splitter, for determining a plurality of input code subsets of the input code; a mapper, coupled to the splitter, for converting the input code subsets into a plurality of output code subsets, respectively; and a merger, coupled to the mapper, for merging the output code subsets to generate the output code.

Abstract: A high speed serializer-deserializer (SerDes) that passes significantly more data through a channel for a given analog bandwidth and signal-to-noise ratio. This SerDes technique involves converting a plurality of bits to be transferred to positions of edges of a waveform that is transmitted over at least one transmission wire from a source to a destination. The plurality of bits are converted to edges in order to position edges such that more than k inter-edge spacings are possible over a range of spacings between T and kT, where k is a real number greater than 1 and T is the minimum spacing between consecutive edges. An edge position translation scheme that maps patterns in a stream of input bits to a corresponding spacing between a rising edge and a falling edge of the waveform, or between a falling edge and a rising edge of the waveform.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. The generated output code words are sequentially connected into a sequence of the generated output code words which follows predetermined run length limiting rules (1, k)RLL, where “k” denotes a predetermined natural number between 7 and 12.

Abstract: A communications channel includes a buffer that receives symbols of user data including a plurality of M-bit symbols. A seed selector receives the M-bit symbols of the user data, selectively removes symbols of the user data from a seed set, and selects a scrambling seed from symbols remaining in the seed set. A scrambling device that communicates with the seed selector and the data buffer generates scrambled user data using the user data and the selected scrambling seed. A Hamming weight coding device determines a Hamming weight of symbols of the scrambled user data and selectively codes the symbols depending upon the determined Hamming weight.

Abstract: A DVD recording method for recording data onto recording media by using a given coding rule, including: generating two data streams by using a plurality of code mapping variants prepared for coding input data, quasi-randomly selecting one of the plurality of code mapping variants, if absolute DSVs of the two data streams are substantially equal, and converting into recording code sequences, where polarities of said two data streams are inverted with respect to each other; and recording data onto said recording media, based on said recording code sequences.

Abstract: Six record areas for predetermined data that has been encoded and digitally modulated are formed in a data record area on a disc. The record areas have different offset compensation amounts. The offset compensation amounts allow all offset amounts that may take place in an error correction code encoder to be compensated. Thus, regardless of the offset amount generated by the error correction code encoder, encoded and modulated data that has been generated by the conventional EFM modulating system and recorded in one of the record areas securely causes DSV to deviate. Each of the record areas is set to a sufficient length that allows the effect of which DSV deviates to be recognized.

Abstract: When a code word sequence is generated by converting input data words of p bits into code words of q bits and concatenating adjacent ones of the code words with a merge bit sequence of r bits in order to obtain the best DSV value, according to one aspect, the adjacent code words are concatenated with the merge bit sequence of r bits which is selected, free from the restriction of the minimum run-length of (d+1)T and the maximum run-length of (k+1)T based on the run-length limiting rule RLL(d, k) but permitting the minimum run-length of (d+1)T and the maximum run-length of (k+2)T.

Abstract: A method and apparatus for channel coding useful for recording channel and other communications applications. The proposed channel coding method is actualized via structured set partition (SSP) in conjunction with multilevel coding (MLC) and offers performance gains over conventional coding schemes with comparable complexity at the bit-error rate (BER) level as well as the sector failure rate (SFR) level.

Abstract: A method and apparatus for modulating data modulates data having a length of m-bits to a variable length code having a basic code length of n-bits. A SYNC bit inserting section adds a sync signal to a train of codes, after a minimum run. The sync signal has a pattern that breaks a maximum run.

Abstract: In a coding method which does not restrict a run length of “1” while data is recorded/reproduced, there are such a drawback that when an error correction is carried out, a total number of error data to be corrected is increased, and also errors of not-detectable data are increased. While data is coded, a continuous number of “1” contained in a code word is limited, and then an error correction is carried out inside a coding/decoding process operation. Thus, a recording/reproducing apparatus having a small number of decoding errors is available.

Abstract: A method and a device for digital/analog conversion are proposed, whereby for improved use of a “dynamic element matching” algorithm, in particular a “data weighted averaging” algorithm, the number of existing conversion elements is greater than a maximum number of possible input or control codes for the conversion elements (7), that is to say greater than a number of conversion elements, which would actually be necessary for a maximum value of the digital word to be converted in each case.

Abstract: A code sequence is encoded using a code conversion table in which the parity of the code sequence varies until the code states become equal to each other. The code word assignment used in this code conversion table is such that the decoded code word constraint length is 3 blocks and q0?q1 for an arbitrary information sequence is satisfied even if a DC control bit is inserted at any of the first and second bits of an information word. Code states s0 and s1 when information sequences d0 and d1 resulted from insertion of provisional DC control bits 1 and 0 inserted at the top of an information sequence “1, 1, 0, 0, 0, 1, 0” are encoded starting with a state 3 according to a predetermined code conversion table are equal to each other, namely, s0=s1=6, in a third block, and two's complement q0 of a sum of code sequences c0 up to a time when the code states are equal to each other is “0,” while two's complement q1 of a sum of code sequences c1 up to that time is “1”. That is, the condition that q0?q1 is met.

Abstract: An apparatus and method for modulating and demodulating data to transmit or record the data on a recoding medium. Data is modulated and demodulated into a variable-length code. The modulated data comprises a sync signal adding means for adding a sync signal to a train of codes after adding a minimum run. The demodulated data comprises a sync signal detecting means for detecting, from a train of codes, a sync signal having a pattern that breaks a maximum run, after detecting a minimum run. A SYNC bit inserting section adds a sync signal to a train of codes, after adding a minimum run, where the sync signal has a pattern that breaks a maximum run.

Abstract: Methods and apparatuses for performing arithmetic encoding and/or decoding are disclosed. In one embodiment, an arithmetic decoder comprises a sequencer to generate a context identifier for an event of an event sequence, a probability estimator to determine a value for a LPS and a probability estimate for the LPS, and a decoding engine that includes a range register to assign a value to a range for the LPS. The value is based on the probability estimate, a value stored in the range register and the context identifier to a range for the LPS if the context identifier is not equal to an index and the value is not based on the value stored in range register if the context identifier is equal to the index. The decoding engine further determines a value of a binary event based on the value of the range for the LPS and bits from an information sequence.

Abstract: A method and apparatus for communicating data is provided. The data is encoded in accordance with a run length limited (RLL) code. A seed is appended to the RLL encoded data. The seed can be used to alter the error correction code (ECC) parity to meet an RLL constraint.

Abstract: The invention filed involves a method of coding and/or decoding binary data for wireless transmission, particularly for radio transmitted data. A sequence of binary data, introduced at the entry to the coding machine with a class N coder (KOD) comprising a register (REG), a comparator (COMP) and a counter (CITN), where N is a number greater than or equal to 3, is separated into a sequence of binary data of the same value, so that the length of each such sequence is not less than one and not more than N, and so that the binary values of the data introduced at the entry to the coder (KOD) are compared with the value last received and recorded in it, the lengths of the same sequences at this entry are read up to the number N and, after reading to N, a sequence of binary data of a value opposite to the value at the entry to the coder (KOD) is inserted, this inserted data sequence having a length M, where M is a number greater than or equal to one and less than N.

Abstract: The present invention provides a system that compresses and decompresses an image. The system includes a first codec a first stage codec for identifying runs of pixels of a defined value in a data stream of the image data beginning from the left and right margins of a line, such that information regarding the runs is assigned as a header and appended to the data stream. The compression device includes a second stage codec for scanning over remaining data in the data stream and compressing all but the header by utilizing a Huffman encoding scheme to reduce amount of data stored in the data stream, wherein the Huffman encoding scheme interleaves Huffman code values with unencrypted data while maintaining long word boundaries for the unencrypted data. The second codec also performs the operation of decompressing a compressed image.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: A communications channel includes a buffer that receives user data symbols including a plurality of M-bit symbols. A seed selector receives the plurality of M-bit symbols, selectively removes symbols from a seed set based on Hamming distances between at least two of the M-bit symbols, and selects a scrambling seed from remaining symbols in the seed set. A scrambling device that communicates with the seed selector and the data buffer generates scrambled user data based on the user data symbols and the scrambling seed. The communications channel is implemented in a data storage system. The seed selector ensures a minimum Hamming weight of 15 percent in the scrambled user data. The seed selector compares first and second user data symbols in the plurality of M-bit symbols.

Abstract: How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit.

Abstract: In a high-density optical storage system, data words are modulated into code words in a manner of minimizing the fluctuation of the digital sum value (DSV). A cumulative DSV is calculated for each possible value of a DSV control bit. The DSV control bit is determined to minimize the absolute cumulative DSV when detecting at least one subsequent DSV control bit or after a predetermined delay. A corresponding code word is generated according to the determined current DSV control bit.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: A recording and reproducing apparatus includes an RLL encoder that encodes an information bit string to a code bit string and a RLL decoder that decodes the code bit string to the information bit string. The RLL encoder encodes the information bit string to the code bit string of a run-length-limited code at a high encoding rate satisfying a plurality of conditions of constraint regarding a string of successive zeros. The RLL decoder decodes the code bit string encoded by the RLL encoder to the information bit string.

Abstract: Systems and methods for performing encoding and/or decoding can include an input data path that receives multiple input data values having an order (significance) with respect to one another. Each input data value can be applied to multiple compute paths (106-1 to 106-N), each of which can precompute multiple output values based on a different predetermined disparity value. Multiplexers (114-1 to 114-N) can output one precomputed output value according to a disparity value corresponding to a previous input data value in the order.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. The generated output code words are sequentially connected into a sequence of the generated output code words which follows predetermined run length limiting rules (1, k)RLL, where “k” denotes a predetermined natural number between 7 and 12.

Abstract: A method and system of lossless compression of integer data using a novel backward-adaptive technique. The adaptive Run-Length and Golomb/Rice (RLGR) encoder and decoder (codec) and method switches between a Golomb/Rice (G/R) encoder mode only and using the G/R encoder combined with a Run-Length encoder. The backward-adaptive technique includes novel adaptation rules that adjust the encoder parameters after each encoded symbol. An encoder mode parameter and a G/R parameter are adapted. The encoding mode parameter controls whether the adaptive RLGR encoder and method uses Run-Length encoding and, if so, it is used. The G/R parameter is used in both modes to encode every input value (in the G/R only mode) or to encode the number or value after an incomplete run of zeros (in the RLGR mode). The adaptive RLGR codec and method also includes a decoder that can be precisely implemented based on the inverse of the encoder rules.

Abstract: An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

Abstract: Techniques are provided for applying modulation constraints to data streams divided into separate interleaved portions. The even and odd bits in a data stream are separated into two data paths. A first modulation encoder encodes the even bits according to a first constraint. A second modulation encoder encodes the odd bits according to a second constraint. The two encoded data streams are then interleaved to form one data stream. The modulation encoders can encode the two data paths using Fibonacci encoding.

Abstract: A method and system for a feed-forward encoder is described. The method includes evaluating one or more source characters to determine whether each source character will invert or maintain a current running disparity and determining a running disparity for each source character before encoding the source character based on the current running disparity and whether the source character will invert or maintain the current running disparity. The current running disparity along with the associated source character may then be passed to an encoder to encode the source character into a transmission character.

Abstract: The invention relates to a method of converting a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal. This stream of databits of the binary information signal is divided into n-bit information words. These information words are converted into m1-bit channel words, in accordance with a channel code C1, or m2-bit channel words, in accordance with a channel code C2, where m1, m2 and n are integers for which it holds that m2>m1?n. The m2-bit channel word is chosen from of at least two m2-bit channel words, at least two of which have opposite parities, the concatenated m1-bit channel words and the m2-bit channel words complying with a runlength constraint of the binary channel signal.

Abstract: Provided is a method, system, and program for providing synchronization in a binary data stream. A binary data stream is received. A synchronization mark having at least one isolated peak is generated into at least one point in the data stream. An encoded data stream is formed by concatenating the synchronization mark with the received binary data. During decoding, the synchronization mark is detected based on error propagation occurring adjacent to the at least one isolated peak of the synchronization mark.

Abstract: Disclosed are a method and device of converting data words into code words. This method inserts 2p p guided bits before inputting each set of data words, performs a pre-defined operation, and generates 2p data sequences with different guided bits. It chooses q data sequences from the 2p data sequences for coding, performs a run length limited (RLL) coding with a coding rate m/n, and generates q (d, k) constrained code word sequences. Finally, an optimal (d, k) constrained code word sequence is selected from the q (d, k) constrained code word sequences. The device reduces the circuitry of the RLL coding applied guided scrambling without losing the control of direct current and low frequency components.

Abstract: A method and circuit to produce an optimal sampling phase for recovery of a digital signal is achieved. A digital signal is over-sampled by sampling on each phase of a multiple phase clock to generate a sample value per phase. The multiple phase clock may be generated by a DLL. A voted value is determined per phase comprising a majority value of a set of consecutive sample values. Transition phases are sensed. A transition phase is defined as two consecutive voted phases comprising different values. The transition phases are compared to a stored phase state to determine a signal shift direction. The signal shift direction is filtered to generate a state update signal. The stored phase state is updated based on the state update signal. The stored phase state corresponds to an optimal sampling phase for recovery of the digital signal.

Abstract: A state modulation method and an apparatus for inserting state control codes are provided. To overcome the problems of inefficient control on direct current and low frequency component in conventional state modulation techniques, the disclosed method inserts state control codes in a state modulation method to increase the probability for selection. With multi-level characteristics, the inserted state control codes can provide a plurality of sets of different signals for selection during coding. Thereby, the direct current and low frequency components can be well controlled.

Abstract: A DSV control bit determining/inserting unit inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit. This modulation unit converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit. The conversion table used by the modulation unit includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remaineder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.

Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.

Abstract: In a data arrangement of a CD-ROM format, data in which DSV control data cannot be placed due to a restriction on the format is followed by control data of two bytes. Main data in which any data cannot be placed is followed by a special control data sequence of two bytes. As a result, after a data sequence of which it is unknown whether the start bit is plus or minus, the sign of the start bit of a diverging control data sequence preceded by the special control data sequence can be kept constant. Consequently, DSV values can be deviated in one direction.

Abstract: Circuitry for detecting excessive runs of similar bits of data in a data stream is provided. The data stream is typically received as serial data operating in a serial clock domain. Run-length detection circuitry checks the received data for run-length violations while operating in a slower parallel clock domain, as opposed to the faster serial clock domain. An advantage of operating run-length detection circuitry in the parallel domain is that longer length run-length violations can be searched for in the received data, as compared to run-length detectors that operate in the serial domain. Another advantage offered by the circuitry is that the run-length violation signal can be provided to utilization circuitry asynchronously. This enables utilization circuitry to quickly capture the signal despite differences in clock domains (i.e., the clock domain of the detection circuitry and the clock domain of the utilization circuitry).

Abstract: A code conversion method and apparatus is provided for scrambling and modulating data. The method and apparatus includes scrambling an input main data unit based on any of plural types of pseudo-random number sequences, and modulating the scrambled main data unit based on any of plural types of modulation data. An output main data unit is produced from the modulated main data unit, and a calculated value representing a difference between a number of 0 bits and a number of 1 bits included in the output main data unit is obtained. Any of the modulation data is then selected dependent upon the calculated value.