Abstract: The invention relates to a method of converting sampling conversion with a predetermined ratio between an input frequency (Fsin) and an output frequency (Fsout). It comprises an initialization phase (40-44) of selective configuration, according to the conversion ratio, of an under-sampling filter and a band-pass filter, and a real time phase comprising the stages of selective over-sampling (45), over-sampling by a factor of two and selective band-pass filtering (46), over-sampling by a factor of sixty four (47) and polynomial interpolation of the quadratic “B-Spline” type (48). The invention also relates to a device (4) for implementation of the method.

Abstract: A method and apparatus are disclosed for performing sampling rate conversion of an audio signal from a first sampling rate to any of a plurality of higher sampling rates using a single set of low-pass filter coefficients. Sampling rate conversion is accomplished by effectively up-sampling, low-pass filtering, and down-sampling the audio signal to generate interpolated output samples of a second digital audio signal at any of a plurality of sampling rates. The sampling rate conversion process includes storing a fixed set of filter coefficients as a plurality of phased subsets of filter coefficients, applying samples of the audio signal to the phased subsets in a rotational manner to generate filtered samples of the audio signal, and selecting and linear interpolating between certain filtered samples to generate samples of the second digital audio signal.

Abstract: A programmable hardware architecture and design methodology for the implementation of a sample rate conversion engine is presented. The conversion engine supports scalable filter taps and can be tuned to a range of interpolation and decimation requirements. The conversion engine can be used effectively in wideband systems to efficiently extract and process digital sequences with protocol specific sampling rate requirements. The conversion engine can also be used as a hardware accelerator for software defined radios and communication systems that require adaptive sampling rates.

Abstract: According to some embodiments, digital sampling rate conversion is performed using a poly-phase filter and a polynomial interpolator.

Abstract: A system of downconverting an intermediate frequency (IF) phase or frequency modulated signal to a digital baseband includes an N bit shift register circuit that receives a binary input as a 1-bit input sample data stream of an IF signal. A decimation circuit includes a memory and receives data from the N bit shift register circuit and stores N 1-bit binary samples as address bits and performs decimation, downconversion and filtering by accessing memory values at a predetermined rate.

Abstract: Digital filtering and sample rate conversion blocks are combined in order to reduce hardware and/or computational complexity. A novel filter design is used to perform sample rate conversion. The filter may be combined with another digital filter. Two embodiment may be used to achieve this function. In a first embodiment, the filter may be clocked at a first (i.e., input) data rate (i.e., before rate conversion). In a second embodiment, the filter may be clocked at the second (i.e., output) data rate (i.e., after rate conversion). In both cases, the filter's basic structure remains essentially the same, but some extra terms are added to handle the rate conversion. The present application is directed toward a sample-rate conversion filter using the output data rate clock as the filter clock.

Abstract: A system for determining a data converter operating mode includes measurement circuitry which measures a master clock frequency, measures a frequency ratio between a frequency of a data clock signal and the master clock frequency, and measures a selected operating condition of the data converter. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and the selected operating condition, to an operating mode of the data converter. In another embodiment, the measurement circuitry adjusts the measurement of the master clock frequency in response to a measurement of the operating conditions of the data converter. In a further embodiment, user input information varies the measurement of the master clock frequency.

Abstract: A sample rate converter reduces the sampling rate of a signal by a fractional number U/D, where U represents an up-sampling rate and D represents a down-sampling rate. The converter comprises an input for receiving an input data stream at a first rate and an FIR filtering stage. The FIR filtering stage comprises a set of D polyphase filter branches, each branch including a set of filter coefficients which operate on a sample of the input signal. The converter also comprises a commutative switch which selectively connects a sample of the input data stream to one of the polyphase filter branches, the switch being arranged to skip every U?1 filter branches during a cycle through the filter branches. An output outputs an output data stream at a second data rate which is lower than the first data rate.

Abstract: Architectures of multi-stage sample rate converters are disclosed. According to one aspect of the present invention, a received signal with a higher sampling rate is converted to a lower sampling rate. To prevent aliasing in the resultant signal, an anti-aliasing filter is introduced. The passband of the anti-aliasing filter is so adjusted according to the conversation rate of a sample rate converter. To keep the implementation relatively simple, the coefficients of the filter are kept constant. Therefore, the conversation rate of a sample rate converter is constrained in a limited range, thus requiring only a constant anti-aliasing filter. A series of halfband filters are then used to convert the signal to a desired sampling rate.

Abstract: A sample rate converter includes an up-conversion module, a linear interpolator module, and a parameter control module. The up-conversion module is operable to convert a first data rate to a second data rate of a data signal. The linear interpolator module is operable to receive the data signal at the second data rate and to produce therefrom a data signal at a desired rate based on at least one parameter. The parameter control module is operable to produce the at least one parameter based on the desired rate.

Abstract: A digital modulator having a sample rate converter that does not require that the final output sampling rate, FOUT, of the sample rate converter be at least twice as great as the input sampling rate, FIN, of the sample rate converter. The upsampling interpolation filter stages of the sample rate converter of the invention do not require any reference clocks to be provided by the NCO of the sample rate converter. Therefore, the upsampling interpolation filter stages are decoupled from the final output sampling rate, FOUT. The interpolation algorithms may be implemented in software, hardware, or a combination of software and hardware. In addition, the polynomial-based interpolator of the Farrow Structure of the invention is capable of using an even or odd number of basepoints.

Abstract: A compressing device comprises plural stages of delay circuits (1?1 to 4?1) and multiplying/adding circuits (5?1 to 10?1) that performs weighted addition of output data from the delay circuits (1?1 to 4?1) according to the value of a digital basic function and thereby determines thinned-out data from sampling data sequentially inputted. Since the thinned-out data is determined by the compression part using a digital basic function serving as the original of a sampling function of infinite supports defferentiable once or more times over the whole range, a compression ratio of at lease 8 can be achieved only by the simple four operations. Further, since interpolation data is determined by the decompression part by using the same digital basic function, the original data before the compression can be reproduced with substantial fidelity by only the simple four operations.

Abstract: A data conversion processing apparatus provides flexible and multifunctional resampling processing using the general-purpose setting method of direct memory access (DMA) setting. In the data conversion processing apparatus, in response to a CPU setting parameters such as input channel information and output channel information including an address for identifying each channel, the transfer amount, and so forth, for a DMA unit, the DMA unit performs data transfer via an input channel and output channel in accordance with the parameters specified by a CPU. A transfer from a first input section to a resampling section via the DMA unit can be specified, including transfer contents from a memory to a first output section. A transfer from the first input section to the first output section is performed by two DMA transfers.

Abstract: A system and method for efficiently upsampling and filtering a signal is provided. The system includes a controller 216 and an upsampler 202 capable of upsampling a digitized signal. The upsampler 202 converts a digitized signal having a first sampled frequency into a digitized signal having a second sampled frequency by inserting, for example, at least one zero between the samples of the digitized signal. A plurality of filters 205–208 is coupled to the upsampler. These filters, which may be band-pass filters, would be suitable for front end encoding in audio-based applications. The controller 216 adjusts at least one output of the plurality of the filters to zero, either by deactivation or forcing the filter to zero, based upon a predetermined characteristic of the digitized signal. One example of a predetermined characteristic is a maximum frequency of interest.

Abstract: A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).

Abstract: A data communication system comprises a transmission line between first and second integrated circuits. An encoder on the first integrated circuit encodes an input data stream to produce a sequence of codewords, wherein codewords in the sequence are members of a set of codewords representing data in the input data stream, and the members of the set are substantially DC balanced, such as a Manchester encoded symbol set. An integrating circuit on the second integrated circuit integrates codewords by integrating for a first interval with a positive polarity within a particular symbol cell, and integrating for a second interval with a negative polarity within the particular symbol cell, to produce output representing the codewords. A sense circuit produces an output data stream.

Abstract: A method for sampling audio data is provided. In this method, the audio data is received and sampled at a first sampling rate using a first interpolation calculation. Thereafter, the audio data sampled at the first sampling rate is again sampled at a second sampling rate using a second interpolation calculation. After sampling, the second audio data sampled at the second sampling rate is outputted. Circuitries and systems for sampling audio data also are described.

Abstract: A method of determining an internal operating mode of an electronic circuit derives multiple comparison rates from a rate of a master clock input, computes one or more clock ratios of the comparison rates to a rate of a sample rate clock input, and determines whether any of the clock ratios is a valid ratio representing a supported clock configuration. The appropriate internal operating mode is then selected based on the valid ratio. In the illustrative embodiment, a clock autodetect unit uses two trip frequencies to derive at least first and second clock comparison rates. The audio converter can operate in three distinct modes (base, high and quad modes). The base mode is selected when the clock ratio is about 256, the high mode is selected when the clock ratio is about 128, and the quad mode is selected when the clock ratio is about 64. A multiplexer can be used to sequence through the computer clock ratios to ensure that a highest valid ratio is used among a plurality of valid ratios.

Abstract: Devices, systems and methods for restricting use of digital content are provided. Among those embodiments which may be construed as providing a method for restricting use of digital data, a preferred method includes the steps of: enabling a user to receive digital data; and preventing the user from copying the digital data to a digital data recording medium if: (a) copy information corresponding to the digital data indicates that such copying is not to be permitted; or (b) the digital data recording medium is not an authorized digital data recording medium.

Abstract: Apparatus, and a related method, for converting digital signals directly to radio-frequency (RF) analog signals. The apparatus includes a single high-speed delta-sigma modulator and an integrated upsampler that increases the data rate of digital input samples by a selected factor, such as nine times. The delta-sigma modulator is configured to include a feedback multiplier coefficients that are selected to greatly facilitate operation of associated adders. At least one critical adder includes a carry-select adder modification that further speeds up the add operation and ensures that the apparatus operates at desirably high frequencies.

Abstract: Analog baseband processors and methods of processing an analog baseband for use in a multimode communication device are disclosed. The analog baseband processor includes a single (shared) analog-to-digital converter, and at least a first receiver digital front end and a second receiver digital front end. The analog baseband processor may further include a third or more receiver digital front ends. The analog-to-digital converter is time-shared by the receiver digital front ends and (alternately) converts a first mode input signal to a first digital signal based at a first sampling rate and converts a second mode input signal to a second digital signal based at the (same) first sampling rate. The first receiver digital front end converts the first sampling rate of the first digital signal, and the second receiver digital front end converts the first sampling rate of the second digital signal.

Abstract: A low-complexity sampling rate conversion (SRC) method and apparatus for the processing of digital audio signals. A first stage upsamples an input audio signal to generate an upsampled audio signal. For example, the first stage may perform 1:2 upsampling using a halfband filter. A second stage re-samples the upsampled audio signal from the first stage at a target sampling rate. For example, re-sampling may be achieved using linear interpolation.

Abstract: Data throughput rates are increased in an optical fiber communication system without requiring replacement of the existing optical fiber in a link. Channel throughput is increased by upgrading the components and circuitry in the head and terminal of an optical fiber communication system link. Aggregate throughput in a fiber optic link is increased beyond the range of conventional Wavelength Division Multiplexed (WDM) upgrades, while precluding the necessity of replacing existing fiber plants. The increase in system throughput is achieved by using advanced modulation techniques to encode greater amounts of data into the transmitted spectrum of a channel, thereby increasing the spectral efficiency of each channel. This novel method of increasing transmission capacity by upgrading the head and terminal of the system to achieve greater spectral efficiency and hence throughput, alleviates the need to replace existing fiber plants.

Abstract: A sample rate converter for converting a digital input signal having a first sample rate into a digital output signal having a second sample rate, wherein the second sample rate is different from the first sample rate. The sample rate converter includes a digital interpolation filter receiving the input signal and comprising a digital zero-phase filter, and a digital polynom interpolator connected to the interpolation filter and providing the output signal.

Abstract: Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.

Abstract: A method and apparatus for maintaining an ideal frequency ratio between numerically-controlled frequency sources provides a mechanism for maintaining coherence between multiple synchronization references where a known ideal rational relationship between the sources is known. Multiple numerically controlled oscillators (NCOs) generate the multiple synchronization references, which may be clock signals or numeric phase representations and the outputs of the NCOs are compared with a ratiometric frequency comparator that determines whether there is an error in the ratio between the NCO outputs. The frequency of one of the NCOs is then adjusted with a frequency correction factor provided by the ratiometric frequency comparator. The NCO inputs can represent ratios of the synchronization reference frequencies to a fixed reference clock and the NCOs clocked by the fixed reference clock.

Abstract: An audio apparatus for performing digital data processing on voice and audio signals through interrelated data sampling and processing. A predetermined mixing processing in the audio apparatus is performed by a first digital processing circuit on both (a) digital received-voice signals converted into the signals sampling processed at a frequency n×fs by a first sampling frequency conversion circuit, and (b) digital audio signals converted into the signals sampling processed at the frequency n×fs by a third sampling frequency conversion circuit. Another predetermined mixing processing is performed by a second digital processing circuit on both (i) digital audio signals converted into the signals sampling processed at a frequency N×Fs by a second sampling frequency conversion circuit, and (ii) digital voice signals converted into the signals sampling processed at the frequency N×Fs by the third sampling frequency conversion circuit.

Abstract: A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.

Abstract: Method and arrangement for converting the sample rate of a higher sample rate discrete time signal to a lower sample rate discrete time signal or vice versa. A recursive signal processing algorithm with low pass filtering function is used, which entirely takes place at the lower sample rate.

Abstract: Provided is a system and method for converting digital data audio data audio data that has a predetermined input sample rate, into an analog data signal. A system includes a digital to analog converter (DAC) including a digital processing portion configured to receive as an input the digital audio data and timing information, the timing information being representative of a time base of the input sample rate. The digital processing portion is similarly configured to digitally process the digital audio data and the timing information to produce serialized output data. The DAC also includes an analog processing portion configured to convert serialized data to an analog format. The digital processing portion operates in accordance with at least one clock having a corresponding clock rate wherein the corresponding clock rate is unrelated to the input sample rate.

Abstract: A data management method that by encrypting and distributing digital content prevents copyright infringement, and that prevents authorization information for decrypting the encrypted digital content from being damaged or otherwise lost. Encrypted content 45 is prepared by encrypting digital content 11 with a content key 44. A portion of the digital content 11 is extracted as sample data 41. A secret key 46, by which the content key 44 is encrypted with user information 14, is embedded as invisible information into the sample data 41, thus preparing watermarked sample data 47. The watermarked sample data 47 is synthesized with the encrypted content 45 to form synthesized data 48. The synthesized data 48 is distributed.

Abstract: An up-sampled data stream, upsampled times a factor P, is generated by the input block providing signal samples having a frequency rate, while an intermediate data stream is generated by a Rate Adapting Stage providing signal samples adapted to an intermediate frequency rate. An output data stream is delivered by a final low pass filter, and includes M signal samples having a desired output sample frequency rate (fOUT=M/Ts). The method provides generation of a provisional stream in the Rate Adapting Stage, wherein this provisional stream is affected by aliases falling within the output Nyquist band [?fOUT/2, fOUT/2], although being adapted to the output frequency rate by a direct insertion of zero samples into the processed stream when L<M, or by a direct cancellation of samples when L>M. Then these aliases are suppressed in the Rate Adapting Stage by weighting the provisional stream via a set of weights.

Abstract: A sample rate converting device includes a noise shaper and a sample rate converter. The noise shaper is for receiving a digital input signal, noise-shaping the digital input signal, and then outputting an n-bit digital stream. The sample rate converter, which is coupled to the noise shaper, receives the n-bit digital stream and outputs a digital output signal. Since the n-bit digital stream is a digital signal with a smaller number of bits in each sample, the computation efforts of interpolation are reduced. Hence, less resource is needed to complete the conversion.

Abstract: Methods and systems for filtering an analog signal sampled at a very high frequency and outputting a digital signal that has a very low sampling frequency to drive a material metering machine. The high frequency digital input signal is input to a first decimation element, which filters out the noise in the signal introduced by an analog-to-digital (A/D) converter and reduces the sampling frequency of the digital signal to a lower sampling frequency of 1200 hertz. The reduced rate digital signal is input into a second decimation element that contains several decimation filters, which reject the 60 hertz line noise and its harmonics while simultaneously reducing the sampling frequency of the digital signal to 10 hertz. The output of the second decimation element is then passed to a bank of selectable filters with sub-hertz cutoff frequencies to remove the machine noise from the material metering machine.

Abstract: A sampling rate converter includes a chain of identical cells connected in series. An input of a first cell of the chain receives input digital sampling values according to an input frequency. An output of the first cell then delivers output digital sampling values according to an output frequency. The input and output digital sampling values correspond to identical respective reconstruction curves, and the output frequency may be greater than or less than the input frequency. Each cell includes a storage element, two multipliers and two adders.

Abstract: A method and apparatus of correcting a data signal sampled at a first rate to a data signal displayed on a video monitor at a second rate is claimed. A data signal is received at a first rate. The data signal is separated into data windows. The minimum and maximum values and positions of data points in data windows are identified relative to a reference, and displayed on a video monitor.

Abstract: The method is based on a controlled, direct insertion/cancellation of samples in a processed data stream. An up-sampled data stream is generated by the input block providing signal samples having a frequency rate. An intermediate data stream generated by a Rate Adapting Stage providing signal samples adapted to an intermediate frequency rate. An output data stream is delivered by a final low pass filter, including M signal samples having a desired output sample frequency rate. The method provides a generation of an up-sampled weighted stream in the Rate Adapting Stage by weighting the signal samples of the up-sampled data stream via a set of weight. Then, the input frequency rate is adapted to the output frequency rate in Rate Adapting Stage by a direct insertion of zero samples into the processed stream when L<M, or by a direct cancellation of samples when L>M.

Abstract: The present invention relates to a converter converting an input digital signal into an output digital signal. Said converter comprises in particular a set of shift registers able to contain samples of the input or output digital signal. It also comprises a calculation unit able to supply a shift signal (4) to said set of registers. Said calculation unit comprises a first storage unit (51) able to contain a value of a conversion ratio or of its inverse, so that the value stored is between 0 and 1. It also comprises a second storage unit (52) able to contain, at a cycle time i+1, i being an integer, a future signal (8) equal to a sum of a current signal (7) contained in the second unit at a cycle time i and of the content of the first storage unit. The shift signal then results from an exclusive OR function (54) between a most significant bit of the current signal (71) and a most significant bit of the future signal (81).

Abstract: A method and circuit to produce an optimal sampling phase for recovery of a digital signal is achieved. A digital signal is over-sampled by sampling on each phase of a multiple phase clock to generate a sample value per phase. The multiple phase clock may be generated by a DLL. A voted value is determined per phase comprising a majority value of a set of consecutive sample values. Transition phases are sensed. A transition phase is defined as two consecutive voted phases comprising different values. The transition phases are compared to a stored phase state to determine a signal shift direction. The signal shift direction is filtered to generate a state update signal. The stored phase state is updated based on the state update signal. The stored phase state corresponds to an optimal sampling phase for recovery of the digital signal.

Abstract: A communication system, source and destination ports of the communication system, and methodology is provided for transporting data in one of possibly three different ways. Data is transported across the network at a frame sample rate that can be the same as or different from the sample rate or master clock within the source port or the destination port. If the sample rate of the source port is known, the sample rate of the destination port can be created using a PLL within the destination port and simply employing a phase comparator in the source port. The phase comparator forwards the phase or frequency difference of the network transfer rate and the source sample rate to the destination port, which then generates a local clock equivalent to the source which then compiles audio data being played at the same rate in which it was sampled at the source. Where economically feasible, sample rate conversion can be used at the source.

Abstract: We disclose a CIC digital filter having an arbitrary-integer decimation rate. The filter has a shifter connected to its input. The shifter receives a shift control input, where the shift control input is pre-computed as equal to the integer portion of 2 raised to the base-2 logarithm of the gain of the CIC filter. There is a multiplier connected between the input and the shifter. In other embodiments, the multiplier could be connected between the input and the shifter. Sequentially-connected integrator functions are connected to the shifter (or multiplier); a decimation function receives input from the integrator functions; and sequentially-connected differentiator functions receive input from the decimation function. The decimation function has a selectable rate equal to any integer between 1 and a number equal to the predetermined maximum decimation value.

Abstract: The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

Abstract: In a wireless local area network (WLAN), receiving or transmitting signals having multiple modulation schemes can require the use of multiple clock rates. Providing these multiple clock rates significantly increases silicon area and power consumption, both of which are highly undesirably in a wireless device. A sequencing interpolator can advantageously reduce the number of clock rates by receiving signals at a first rate and outputting signals at a second rate. The sequencing interpolator can include a multiplexer network that selectively determines which coefficients are applied to certain signals. Coefficients are chosen to ensure that an error in a frequency domain is within a given tolerance. The multiplexer network can be controlled by a counter value. At a predetermined count, the interpolated output signal is discarded and the counter is reset.

Abstract: A communication method for a radio LAN system provides communication at a first transmission rate. In the method, a first signal of the first transmission rate is time-divisionally distributed into n?1 second signals (n=3, 4, . . . ). The n?1 second signals are respectively converted into n?1 third signals of a second transmission rate less than the first transmission rate. The n?1 third signals of the second transmission rate are also transmitted through radio transmission paths between n?1 radio base stations and a terminal station connected to at least one terminal unit.

Abstract: A method for decoding using a general purpose processor, comprising the steps of extracting a bit field from a data stream; extracting one or more properties from the data stream; matching the one or more properties with one or more tags in a content addressable memory; and generating a new address in response to the content addressable memory.

Abstract: An enhancement that improves the performance of test and measurement equipment such as digital oscilloscopes and arbitrary waveform generators through the use of compression and decompression is described. The present invention is particularly effective for compressing and decompressing high-speed, bandlimited analog signals that are not appropriately or cannot effectively be compressed by prior art speech, audio, image, and video compression algorithms due to various limitations of such prior art compression solutions. The present invention improves digital oscilloscopes by compressing the sampled version of an analog waveform under observation in real time, allowing a significantly longer duration of the waveform to be stored in the oscilloscope's capture memory, when compared with the duration of the same signal's uncompressed waveform stored in the same memory.

Abstract: A data rate determination apparatus includes an edge detection and clock generation circuit for receiving an input bit stream. The edge detection and clock generation circuit generates a pulse for each edge detected in the input bit stream. The pulses are passed to a programmable re-triggerable monostable multivibrator circuit coupled to a binary counter, which counts how many pulses are received within a time period determined by the number of pulses received at a rate higher than a predetermined rate. The binary counter is coupled to a Gray code counter coupled to a processing unit. The processing unit uses different counts that are accumulated over different sampling periods with different predetermined rates to establish statistical data, which can be compared to known data for different data rate standards or formats.

Abstract: A data converter, or “gearbox,” for a padded protocol interface uses a reduced number of components by processing a narrower intermediate data stream, while at the same time multiplying the clock speed of its intermediate input and output so that it processes more data per clock cycle. The data streams can be narrowed to any integer factor of the original width (other than the original width).

Abstract: Techniques for sample rate conversion are disclosed. In one exemplary embodiment, a sample rate conversion occurs between first samples having a sample rate defined by a first clock signal and second samples having a sample rate defined by a second clock signal. Using a conversion ratio and at a first rate defined by the first clock signal, a given second sample is determined from at least one first sample. A write pointer is updated for a buffer when second samples are written into the buffer. A read pointer is updated for the buffer when second samples are read from the buffer. The second samples are read from the buffer at a second rate defined by the second clock signal. The conversion ratio is modified based on the write and read pointers.

Abstract: A system and method for determining a minimum pulse width for a digital data stream is described herein. The minimum pulse width is used to infer the data rate for the digital data stream. A measuring cell is used to measure the pulse widths by utilizing RC time constants. The measuring cell comprises a capacitor whose voltage is related to the pulse width. This voltage is then transferred by the measuring cell to a measurement node which determines the minimum pulse width of all the transferred voltages for the plurality of pulses.