Abstract: Decoding apparatus and method set interpolation flags in units smaller than an ECC block. The PI1 flag indicating an error on a row-by-row basis is generated for the first error correction result, while the PI2 flag also indicating an error on a row-by-row basis is generated for the second error correction result in the ECC block. The PO flag indicating an error on a column-by-column basis is further generated for the error correction result in the ECC block. Following these processing operations, the PI1, PI2 and PO flags are used for generating the interpolation flags.

Abstract: To carry out the processing operations relating to the implementation of a Viterbi algorithm, an integrated circuit comprising a processor and a coprocessor is made. The coprocessor is constructed so as to carry out operations of accumulation, comparison and selection in order to limit or reduce the work of a processor that would have to carry out these operations. By judiciously choosing the structure of the coprocessor, it is possible to make this co-processor sufficiently programmable so that it is suited to various situations of implementation of the Viterbi algorithm.

Abstract: Apparatus and method for coding to improve the minimum distance properties of sequence detectors operating at high densities in storage systems is presented. The coding scheme of the present invention is referred to as maximum transition run (MTR) code and eliminates data patterns producing long runs of consecutive transitions while imposing the usual k constraint necessary for timing recovery. The code has a distance gaining property similar to an existing (1,k) runlength-limited (RLL) code, but can be implemented with considerably higher code rates. When the MTR code is used with fixed delay tree search (FDTS) or high order partial response maximum likelihood (PRML) detectors, the bit error rate performance improves significantly over existing combinations of codes and detectors.

Abstract: A magnetic-tape recording/reproducing arrangement of the "helical scan" type adapted to record and/or reproduce a digitally coded video signal, includes a coding device (3). In the recording mode, the coding device (3) performs channel-encoding upon a digital recording signal (C) so as to form a channel signal (D) for recording on the magnetic tape (7.1). In the reproduction mode, the coding device (3) performs channel-decoding upon the channel signal (H) read from the magnetic tape (7.1), so that a digital reproduction signal is formed which is a replica of the original recording signal (C). For this purpose, the coding device (3) includes a data sequence generator (3.3) adapted to generate a data sequence (E) defined by the polynomial P(X)=X.sup.15 +X.sup.A +1, where A=7 or 8. Furthermore, the coding device (3) may include an XOR circuit (3.2) in which the signal (C, H) to be processed is combined with the generated data sequence (E), and a selection circuit (3.

Abstract: A system and method for extracting a data signal transmitted by a signal source encoding the data signal onto first and second binary signals as a known two-bit binary state of the two signals taken together includes memory storing single bit binary patterns representative of known bit pattern and a reference table of two bit binary state couples representative of a data signal bit encoded onto the first and second binary signals. A processor monitors one of the first or second binary signals and compares the one monitored binary signal to the stored single bit binary patterns in memory. The processor stores, if a match is found, the respective binary states of the first and second binary signals in memory as a pair of two bit binary states.

Abstract: A method for encoding and decoding the digital information sequence uses a combination of two block codes to simultaneously correct and detect errors. The information sequence is encoded by a first stage of the encoder to produce an information code word including an information vector and a primary redundancy vector. The primary redundancy vector is encoded in a second stage of the encoder to obtain a redundancy code word. The information code word and redundancy code word are interleaved and transmitted to the receiver. At the receiver, the information code word and redundancy code word are decoded in a first stage of the decoder to obtain a first estimate of the information code word. The first estimate of the information code word is decoded in the second stage of the decoder to produce a second estimate of the information code word. The distance between the first and second estimates of the information code word is evaluated. If the distance is more than one, the received code word is erased.

Abstract: A new Test FP Data Class operation is provided which utilizes a 12-bit mask to determine to which of the 12 possible data classes a floating point number belongs and sets a condition code accordingly. As preferably embodied, a typical IBM System 390 instruction format is adapted to implement a Test FP Data Class operation. The class and sign of the first operand are examined to select one bit from the second-operand address. A condition code of 0 or 1 is set according to whether the selected bit is 0 or 1. The second-operand address is not used to address data; instead, individual bits of the address are used to specify the applicable combinations of operand calls and sign.

Abstract: An encoder functions to perform a modulo-two dot product of an n-bit information word with a succession of n-bit projector words which are n-bit words chosen at random or generated pseudorandomly. These projectors are also known by the decoder. The parity of the successive dot products is sent as the output bits of the coder. The decoder receives the incoming bits which have been generated at the encoder and subsequently passed through a noisy channel. In the decoder, the projectors serve as successive n-bit addresses to a table. If the incoming i-th bit is a zero, the content of the indicated table location is incremented. If the incoming bit is a one, the content is decremented. After the table has been filled, the table contents are considered as a vector, V. The Hadamard transform is then taken. The largest (most positive) coefficient of the transform is identified. The table address corresponding to the location of the largest coefficient is the estimate of the decoded information word.

Abstract: A majority logic circuit is supplied with output values of adjacent three comparators. The majority logic circuit outputs, as an output signal, the supplied three output values including at least two equal output values. Inverter circuits and AND circuits produce and output a read signal of an encoder which is a logical product between the output signal and an inverted signal of the output signal.

Abstract: The present invention relates to a method and apparatus in which a differentially coded signal having forward error correction added to the encoded data can be decoded with an improved bit error rate performanceApparatus for decoding a differentially encoded input signal having forward error correction added to the encoded data, the apparatus comprising: a differential decoder to receive the input signal and to decode the data in each differentially encoded signal interval thereof by reference to the data in a previous differentially encoded signal interval; error correcting means to correct errors in the decoded signal form the decoder; and means for supplying to the decoder the corrected data from each signal interval to act as a reference for decoding the data in a following signal interval.

Abstract: A compensation system is configured to improve the accuracy of digital signals that are communicated through a digital network by reducing loss from digital attenuation quantization (DAQ; digital pad quantization) and rob bit signaling (RBS). The combined DAQ/RBS compensation system can be employed within a transmitting modem connected to the digital network and is constructed as follows. In a first embodiment, a first adjustment mechanism combines a DAQ compensation quantity with each segment of the digital data, prior to transmission, in order to enhance accuracy of the received digital data. The value of the DAQ compensation quantity depends on feedback that is provided to the compensation system during a series of test transmissions.

Abstract: Data is transmitted and received over a channel in a telecommunications system includes encoding the data by providing a plurality of fixed length code tables, wherein each of the fixed length code tables has a size that is different from a size of every other fixed length code table, and encoding the data as a plurality of information code words, wherein each information code word is a selected value from one of the fixed length code tables. A plurality of marker codes is also provided, wherein the marker codes are variable length codes. A unique one of the marker codes is then associated with each of the fixed length code tables, and channel code words are generated by inserting the associated marker code one bit at a time into each of the information code words at a fixed bit interval. The encoded data may be decoded by processing in a forward direction to extract and decode marker code words. Information code bits associated with valid decoded marker code words are extracted and decoded.

Abstract: A rob bit compensation system improves the accuracy of digital signals transmitted to a digital network, such as a telephone network, that employs rob bit signaling (RBS) wherein the network periodically robs a bit for its own use. The rob bit compensation system can be employed within the transmit subsystem of a digital modem connected with the digital network that periodically robs a bit every nth frame, where n is, for example, 6, 12, or 24. The system may also be employed in association with the communications path within a coder/decoder (codec) that transmits data to the digital network. A feedback system advises the rob bit compensation system as to which frames of outgoing digital data are to have a bit robbed therefrom by the digital network. The feedback system causes a quantity to be mathematically combined with the digital data corresponding with each RBS frame in order to enhance accuracy of the RBS frames.

Abstract: A device for establishing boundaries in a bit stream is disclosed, which converts a first number of bits of the bit stream into a second number of bits (that is, the CRC is determined) and compares the second number of bits with a third number of bits of the bit stream. The converting means comprises discounting means for discounting the effect on the conversion process of at least one bit situated outside the first number of bits. The device establishes the boundary of the bit stream after a minimal time span, even for very high bit rates per bit shift.

Abstract: A digital signal decoding apparatus for preventing errors which cannot be corrected sufficiently by error correction from reflecting on a decoded signal. An uncorrectable error part of a digital signal or a data part including the error part is replaced with a special code including a synchronous code, and is output to decoding means. Because the decoding means capable of identifying the synchronous code can also identify the special code, a proper error processing can be executed by confirming the presence of errors at the time of decoding. Therefore, by using the decoding means, it is possible to prevent errors which cannot be sufficiently corrected from reflecting on a decoded signal.

Abstract: Relationships between amplitude patterns, each being composed of a train of a predetermined number of samples including a target sample, and correction values corresponding to quantizing errors of the target samples are obtained in advance from a relationship between a plurality of samples of the same amplitude pattern and actual amplitude values of their target samples. Each of the sample values of inputted digital data is corrected by a correction value corresponding to an amplitude pattern specified by the sample values around such sample value to be corrected. As a result of this operation, a correction value consisting of a few bits is added to the lower of the LSB of the digital data, thereby reducing quantization noise of the digital data.

Abstract: A data detection apparatus retrieved binary data modulated in conformity with the (d, k) constraint from an analog signal includes a timing extracting unit for generating a timing signal representing the timing at which the analog signal crosses the threshold value, a clock generating unit for generating a clock signal having a cycle corresponding to one bit of the binary data from the timing signal, a timing position detector for detecting the position in the cycle of the timing, and an error correcting unit for correcting an error in the binary data in accordance with the detected position.

Abstract: A method and apparatus are described for coding a frame of N-bit bytes into a frame of coded M-bit bytes wherein M>N>0 and wherein said frame has a frame boundary including the steps of storing a frame of M-bit bytes; providing a code containing a set of M-bit bytes which is a subset of all possible M-bit bytes; for each of the 2.sup.

Abstract: In a speech decoder which experiences frame erasure, the pitch delay associated with the first of consecutive erased frames is incremented. The incremented value is used as the pitch delay for the second of consecutive erased frames. Pitch delay associated with the first of consecutive erased frames may correspond to the last correctly received pitch delay information from a speech encoder (associated with a non-erased frame), or it may itself be the result of an increment added to a still previous value of pitch delay (associated with a still previous erased frame).

Abstract: In a signal processing method to compress digital audio data by a block floating process, digital signal encoding/decoding apparatuses prevent deterioration of sound quality of the digital audio signal and improve the compression ratio of the digital audio signal when the digital audio signal is converted on a frequency axis per predetermined time frame, and data on the frequency axis is then divided into a plurality of blocks to be recorded, otherwise, bits are allocated per block to compress the digital audio signal for minimizing transmitted parameters. Also, encoding/decoding methods are provided to enable highly efficient encoding/decoding without recording or transmitting word length, allowing one to obtain a high-quality audio signal by allocating bits conventionally held by the word length to hold quantization data of a spectrum signal.

Abstract: A recorded signal reproduction circuit in an optical disc information reading and recording apparatus converts a recorded signal recovered from an optical disc to PR (1, 2, 1) characteristics through a equalizer circuit, digitizes it through an A/D converter and at the same time also generates a clock signal synchronized in phase with the equalizer circuit output signal by using a binary edcoder circuit and a PLL circuit. This clock signal is then provided to an A/D converter as the sampling clock. The A/D converter output signal is then decoded to the original channel bit stream based on the clock signal. Because the equalizer circuit output signal is provided to both the binary encoder/PLL circuit and the A/D converter together, additional circuity for converting signals into a binary series of pulses is unnecessary and reduction of circuit scale is possible.

Abstract: A method and apparatus detects whether more than one object has been selected from a set of objects. A unique code and an error code is coupled to objects in the set. At least one object is selected and the unique codes from the selected object are logically summed, as are the error codes from the selected objects. A test code is generated from the logically summed unique code and tested for equality with the logically summed error code to determine if more than one object was selected.

Abstract: A method of generating codes for error checking from a first and second types of data trains, first type of data trains having m symbols, second type of data trains having n symbols, m and n being natural numbers and m<n, comprising the steps of: generating n-m dummy data: and attaching the n-m dummy data to the first types of data train is disclosed.

Abstract: A method for re-synchronizing a variable length code at a high speed by comparing an input bit string with a plurality of synchronous code patterns in a parallel manner using a parallel-processing pattern matching algorithm when a transmission error is involved in the variable length code received in a variable length decoder used in systems using digital signals requiring a fixed length code pattern, such as broad band-integrated service digital network (B-ISDN) terminal, high definition TV, digital TV, multimedia, video TAX, facsimile and etc..

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: A method of coding, and a coder, using a code in which data words are assigned to code word pairs in a selective manner, so that the value of a data word error resulting from inversion of a bit in a code word may be specific to and dependent solely upon the position within the code word of the inverted bit.

Abstract: An observed binary code sequence which has been corrupted by noise is operated upon to determine the configuration of a code generator capable of generating an equivalent code sequence. A method and apparatus is introduced to determine the code generator configuration based on rapid testing and elimination of a large set of hypothesis code generator configurations.

Abstract: A data signal processing method and apparatus capable of obtaining a high quality signal performs the following operation. M bits of code information are separated into upper N bits and lower (M-N) bits wherein M>N. A change mode of the upper N bits is detected using a first resolution wherein values are represented in units of 1/2.sup.N of the predetermined dynamic range of the signal. A change mode of the lower (M-N) bits is detected using a second resolution wherein values are represented in units of 1/2.sup.M of the predetermined dynamic range. Correction code data is generated at the time when an accumulated value of the lower (M-N) bits reaches the value associated with 1 LSB in the first resolution. The accumulated value is obtained for adding sequential sampling values using the second resolution in each period.

Abstract: In a decoding system which decodes a transmitted signal encoded by using a Reed-Solomon code, an error locator polynomial of the nth iteration is calculated based on a predetermined number of syndrome values; a group of variables of the (n-1)st iteration including a discrepancy and an error locator polynomial thereof; and an error locator polynomial of the (n-2)nd iteration. The method for providing the error locator polynomial comprises the steps of calculating a discrepancy of the nth iteration based on the syndrome values and the error locator polynomial of the (n-1)st iteration; calculating a temporal term based on the discrepancy of the (n-1)st iteration and the error locator polynomial of the (n-2)nd iteration; determining a correction term based on the temporal term and the discrepancy of the nth iteration; and computing the error locator polynomial of the nth iteration based on the correction term and the error locator polynomial of the (n-1)st iteration.

Abstract: In an optical transmission system applicable to a SDH network, communication between two line terminating equipments is performed in a form of a STM frame composed of a SOH field and a payload, which is determined by CCITT recommendations. The line terminating equipment provides a FEC circuit which is preferably arranged at a location between MSP and MST function blocks. The FEC circuit is designed to perform coding/decoding operations, using a cyclic Hamming code, directly on each AU-4 message derived from the STM frame. Otherwise, the FEC circuit performs operations on each k-bit interleaved AU-4 message (where `k` is an integer larger than 1). Check bits generated by a FEC coding circuit are written into undefined byte areas in a MSOH field, and error correcting is performed at a decoder circuit on the basis of embedded check bits, therefore FEC operations are performed within a multiplex-section layer.

Abstract: Encoder for the conversion of a signal of thermometric or cyclic type including a set of n Exclusive OR gates (X1, Xi, . . . , Xn) and an encoding matrix with n rows (1 . . . n) and a plurality of pairs of columns for a differential output of one bit of the binary signal, a matrix in which a row/column coupling is produced by a transistor (T). A pair of pseudo-columns of order zero is coupled to the rows in a way comparable to the coupling of the pair of columns of order 1, but by applying a cyclic shift in respect of the rank of the rows (rows of rank i of the pseudo-columns of order zero, coupled like the rows of rank (i modulo n)+1 of the columns of order 1). The bit of order zero [Bo] is obtained at the output of an additional Exclusive OR gate the inputs of which respectively receive the logic signal [Bo*] output by the pair of pseudo-columns of order zero, and the logic signal [B1] output by the pair of columns of order one.

Abstract: A method and apparatus for improving the performance of coding systems in the presence of frame erasures or lost packets. The encoded signal is modified after transmission but prior to decoding by a decoder preprocessor. The preprocessor recognizes that a given frame has been corrupted and modifies the encoded signal so that the decoding thereof will result in improved coding system performance. Specifically, based on the decoding process and on a predetermined target signal, the encoded signal is modified so that the decoding thereof will generate an approximation to the target signal. In a first illustrative embodiment, a CELP speech coder is used and the target signal is an excitation signal comprised of all-zero excitation vectors. In this case, the portion of the corrupted excitation signal indices which identify the corresponding gain factors are set to values which represent a low gain factor.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.

Abstract: The present invention relates to a serial/parallel converter circuit with uncertainty removing function. The object of the invention is to offer that signals can be instantaneously rearranged in the same data arrangement as that of original parallel signals prior to a parallel to serial conversion.

Abstract: A decoder in the form of a Euclid's algorithm operation circuit in which division polyonomials are repeatedly divided by residues resulting from the division process of dividend polynomials and division polynomials until the degree of residues of the division process satisfies a prescribed condition. The Euclid's algorithm operation circuit comprises register groups for storing dividend polynomials and division polynomials, respectively, a feedback loop for storing residues resulting from the division process of the dividend polynomials by the division polynomials, a shifter for shifting contents of registers, and an exchanger for exchanging coefficients of the dividend polynomials with coefficients of the division polynomials.

Abstract: A Viterbi decoder includes a branch metric generator, a subset maximum likelihood estimator, an accumulator switch circuit (ACS circuit), a most likely path setter, a first selector, and a path-memory circuit for the purpose of estimating encoding bits of a 4-bit error-correcting encoded information symbol string. The Viterbi decoder also includes a noncoding bit detector, eight j-level shift registers, and a second selector for the purpose of estimating a noncoding bit of the 4-bit error-correcting encoded information symbol string. The j-level shift registers are provided for temporarily holding the output signals of the noncoding bit detector. The second selector is provided for selecting one output signal from the output signals of the j-level shift registers in accordance with the output signal of the selector.

Abstract: A decoding circuit for 2T encoded binary signals, comprises: a data input terminal; a first D-type flip flop having an input coupled to the input terminal; a first exclusive OR gate having inputs coupled to the input terminal and an output of the first D-type flip flop; a shift register having an input coupled to an output of the exclusive OR gate; a second D-type flip flop having an input coupled to the shift register; and, a second exclusive OR gate having inputs coupled to an output of the second D-type flip flop and to a tap of the shift register, the second exclusive OR gate having an output at which decoded input signals are reconstituted. The second D-type flip flop may be a constituent stage of the shift register, the inputs of the second exclusive OR gate being coupled to adjacent taps of the shift register. At least one of the adjacent taps is the output of the constituent stage formed by the second D-type flip flop.

Abstract: A multiplex transmission system includes a plurality of multiplex nodes interconnected by a common multiplex transmission line. Data frames are transmitted among the multiplex nodes through the multiplex transmission line. A data frame transmitted from a sending multiplex node includes a data area which is divided into subdivided areas in accordance with data transmitted therefrom and data transmitted from receiving multiplex nodes which send data in response to a send request, in accordance with the number of data pieces or the number of bits, and the receiving nodes send data to respective subdivided areas in a predetermined order, to thereby carry out a data transmission. Accordingly, the sending multiplex node can simultaneously collect data from the receiving multiplex nodes which are functionally subordinate. When any of the receiving multiplex nodes fails to return an ACK signal, the sending multiplex node retransmits the data frame.

Abstract: Apparatus for decoding an input digital signal by replacing successive n-bit groups of the input digital signal with respective ones from an ensemble of m-bit data words, each m-bit data word having an associated n-bit code word, where n is greater than m, comprises: means for determining the Hamming distance between an n-bit group of the input digital signal and each of the n-bit code words associated with the ensemble of m-bit data words; and means for replacing that n-bit group of the input digital signal with an m-bit data word from the ensemble of m-bit data words for which the Hamming distance between the n-bit code word associated with that m-bit data word and that n-bit group is the lowest.

Abstract: The present invention is a reduced iteration decoder circuit and method to compute error-locator sequence values for use in the correction of bit errors in Reed-Solomon or BCH coded information. By utilizing special properties of Reed-Solomon code and BCH codes, the decoder circuit of the present invention can detect n symbol errors using approximately n mathematical iterations with substantially reduced decoding processing time. A further reduction of decoding time is achieved by the performance of a substantial portion of the decoding processing in a parallel manner. The present invention may be utilized in digital communication systems and data storage systems or other information systems where Reed-Solomon or BCH encoding is utilized.

Abstract: The present invention provides an encoding and decoding apparatus used for the compression and expansion of data. A state machine is provided having a plurality of states. Each state has at least one transition pair. Each element of the transition pair comprises zero or more bits representative of the compact code to be output and the identification of the next state to proceed to. The transition pair reflects an output for a yes and no response associated with the probability of the data to be compacted and whether the data falls within that probability.

Abstract: A semi-flash type analog/digital converter for eliminating errors in its output signals which are caused by noise. The analog/digital converter includes a D/A converter for outputting a plurality of analog signals which are produced based on a plurality of input signals. A plurality of comparators compare the voltage of an analog input signal, provided via a sample and hold circuit, with the analog signals output from the D/A converter. The output from the comparators are supplied to two latches, which further provide the outputs to a plurality of encoders. One of the encoders encodes the signals provided by one of the latches and outputs signals representative of high order bits of a digital signal. A second encoder, which encodes output signals provided by the other latch, is a correction encoder. The correction encoder corrects the signals provided by the latch if it determines that any of the signals are in error, and outputs signals representing the lower order bits of a digital output signal.

Abstract: Apparatus for reproducing coded audio signals includes interpolation circuitry for substituting interpolated signal values for erred or lost audio signal. To minimize undesirable audible artifacts which may be introduced into the audio signal by virtue of the substitution process, the rate of substitution is monitored. When the rate of substitution exceeds a predetermined rate, the higher frequency components of the audio signal, including the substituted values, are attenuated.

Abstract: An improved approximation of the desired codebook boundary is achieved, when quantizing data from a source with memory, by adding a dither sequence, the samples of which are contained within the Voronoi region of an unpartitioned lattice or the first level of lattice partitioning used to generate the trellis code. A sequence of data generated by the source with memory is quantized to a nearest sequence of a predetermined trellis code which is based on coset partitioning of a predetermined lattice into translates of a coset lattice. The trellis code sequence is then filtered with an inverse source filter. A dither sample is added to each sample of the sequence, such that (1) a sum of the dither sample and the filtered trellis code sequence sample lies on a super-lattice of the coset lattice, and (2) the dither sample is inside the Voronoi region of the super-lattice.

Abstract: A Viterbi decoding apparatus includes a brand metric calculation circuit for calculating a branch metric for a plurality of time slots at one time by an add-compare-select-state-metric (ACS-SM) calculation circuit for performing add-compare-select (ACS) calculation an add-compare-select-state-metric calculation circuit according to a branch metric for a plurality of time slots obtained by the branch metric calculation circuit and a state metric in the preceding stage at intervals of a plurality of time slots, and a maximum likelihood sequence decision circuit for decoding input data according to the content of the path obtained through the ACS calculation, wherein on the outside of a loop composed of the ACS-SM normalization circuit and a state metric storage circuit, there is provided a normalization command circuit, whereby a decision as to the necessity for normalization, a setting of the timing of normalization, and the like are performed, and, when it is decided that normalization is necessary, the state

Abstract: Apparatus for decoding digital signals, such as digital television signals, which have been transmitted by concatenated coded modulation using partitioning levels of a constellation of points representing different code values. The apparatus includes successive decoding stages which respectively operate on the successive partitioning levels of the constellation. Each decoding stage includes a detector for detecting received points in the relevant partitioning level. At least one stage includes an internal decoder for generating estimated bit sequences in accordance with an inner code and erasures of bit sequences for which the estimation is found to be ambiguous, an external decoder decoding in accordance with an outer code and correcting bit sequence erasures, and an encoder for encoding the output of the external decoder and supplying the resulting re-encoded bit sequences to the succeeding stages of the decoding apparatus to validate detection thereby of points in their partitioning levels.

Abstract: A circuit for minimizing the number of cycles needed to add a first number of quantities together to produce a first result in parallel with the addition of a similar number of quantities to produce a second result, subtracting one result from the other to determine which result is the least, and selecting and storing the least result. For the various additions and the subtraction above named, n bit addends are divided into m upper bits and n-m lower bits. m bit addends (upper bits) are added together separately from and simultaneously with the addition of the n-m bits (lower bits). The first m bit result is subtracted from the second m bit result and the upper bit of that subtraction is adjusted according to the number of carry bits produced by the various lower bit additions and subtraction. In that manner, an accurate comparison of the two m bit results is obtained. A logic array and a mux array provide fast adjustment so that the entire add, compare, and select process is accomplished in one cycle.

Abstract: This invention describes the use of a counter and digital logic to provide a timing pulse needed to decode Gray code position information on the tracks of a rotating disk storage media when the timing pulse is missing because the head of the disk drive is straddling two tracks as the Gray code passes beneath the head. The logic synchronizes the timer to provide a pulse at precisely the right time if and only if a pulse originated by the Gray code is missing.

Abstract: Input values are data encoded for improved signal characteristics (e.g., limited maximum run length and limited cumulative DC-offset) so as to form "data codewords," and then a number of the data codewords, collectively referred to as a block, are error protection encoded, preferably using a conventional linear and systematic forward error control ("FEC") code, to yield an FEC code block. Preferably, an FEC code block is formed by generating a number of check bits or FEC bits equal to the number of data codewords in the block, and then concatenating one FEC bit and its binary complement with each data codeword, so that one FEC bit and its complement is interposed between each successive codeword.

Abstract: In an encoding side, an estimate of input data is generated. An estimation error which is equal to a difference between the estimate and the input data is calculated. The estimation error is classified, thereby generating a category index indicative of a category corresponding to the estimation error. The input data is divided by a divisor, and a remainder of a result of the dividing is generated. The divisor is equal to a given value which is greater than a difference between an upper limit value and a lower limit value defining a range of the category. The category index and the remainder are encoded into corresponding codes which are outputted. In a decoding side, input data is decoded into a category index and a remainder. An estimate is generated from previous output data. A divisor is generated in accordance with the category index. An offset is generated in accordance with the divisor and the estimate. The offset is equal to the divisor multiplied by an integer.