Abstract: In a shift correction decoder which processes d,k-constrained RLL data that is encoded in accordance with a shift correction code whose symbols in GF(p) comprise modulo p reductions of cumulative sums of successive run symbols of the RLL data (where p is an odd prime), additive errors (i.e., drop-out and drop-in errors) in the received RLL data are corrected by relying in part on information pertaining to the sequence of the polarities of successive 1-bits in the received RLL data. The polarity information is used to either insert missing 1-bits (due to drop-outs) or delete spurious 1-bits (due to drop-ins) and specify to the shift correction decoder the location of an additive error as an erasure. Synchronization slips are corrected by pre-multiplying the received codeword polynomial by a factor which reduces to two the number of errors created by a single synchronization slip. GF(p) is selected such that p.ltoreq.

Abstract: A maximum likelihood decoder (28) comprises a Viterbi decoding unit (30) and a symbol concluding unit (29). Final N-M bit data of data of N (>M) bit unit, to which M-bit original data is converted, is supplied to the symbol concluding unit (29) as a terminal portion and other data is supplied to the Viterbi decoding unit (30), thereby being demodulated by a demodulator (37). A maximum likelihood decoding apparatus is provided in which image data or the like can be recorded and reproduced at high speed and maximum likelihood parallel decoding is effected. A reproducing data demodulating apparatus using such maximum likelihood decoding apparatus is also provided.

Abstract: A method for validating Manchester Encoded Gray Coded serial binary signals wherein the Manchester Encoded, Gray Coded data word is first tested for missing data bits by constructing first and second copies of the data word wherein the first copy has a one inserted in a position where a missing data bits is detected and the second copy has a zero inserted in a position where a missing data bit was detected. Thereafter, the first and second copies of the data word are then converted from Gray Code into corresponding coded binary words and the second binary word is subtracted from the first binary word to obtain an absolute value. Only when the absolute value is one is the missing bit the least significant and the received data word valid information.

Abstract: An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.

Abstract: An HDB3 code violation detector includes a converting part for receiving positive polarity data and negative polarity data from a PCM line and for converting an HDB3 code received via the PCM line into an NRZ signal, and a first judging part receiving the positive polarity data, the negative polarity data and the NRZ signal, for judging whether or not a pattern of the NRZ signal received from the converting part is possible when the NRZ signal is NRZ "1" and for outputting a judgement result. In addition, the detector includes a second judging part receiving the positive polarity data, the negative polarity data and the NRZ signal, for judging whether or not a pattern of the NRZ signal received from the converting part is possible when the NRZ signal has a maximum of three consecutive NRZ "0"s and for outputting a judgement result.

Abstract: A data compression/decompression method incorporating aliasing error reduction. An array of terrain data is first scanned for a set of modes and indexes are assigned to those modes. These modes are used as precision points for compression and decompression. A compressed index database is created using the associated modes for the original terrain data. If the number of modes exceed a predetermined number the number of modes is collapsed using an aliasing technique. The alias error is tracked during the compression cycle. Total aliasing error is kept to a local minimum. The compressed data is decompressed by decoding and accessing the index database for the elevation alias. Further compression is accomplished using a lossless coding technique.

Abstract: The encoder is particularly for high speed and high resolution flash analog-to-digital converters. The number of components is drastically reduced, error correction scheme extended, the conversion speed and reliability increased. A suitable error correction can be accomplished by changing content of the decoders. The encoder comprises a register for sampling and interim storage of the input code, and providing a plurality of section codes, a plurality of section decoders for converting the section codes into a first portion of the output code, and a selective circuit for selecting one of the section codes in response to the first portion of the output code and converting the selected section code into a section portion of the output code.

Abstract: Disclosed is a method and circuit for modifying the check code of a data packet based on a first seed to accommodate the addition or substraction of a header. A number of bits, which include a second seed, an exclusive OR function of the first seed and a portion of a header, and a string of zeros dependent upon the length of an incoming data packet, is sent through a CRC generator. The resulting CRC calculation and the incoming packet check code are exclusive ORed to produce a modified check code taking into account the addition or substraction of the header.

Abstract: An Off-premises CATV system having an interdiction apparatus includes a remote microprocessor which receives commands and data from the headend over the cable distribution plant. The data is in a modified Manchester format (biphase-M) at 19.2 K baud which is then frequency modulated on a carrier of 108.2 MHz. A receiver detects the base band signal and outputs a serial digital signal to one input port pin of the microprocessor. The microprocessor rejects incorrect messages by measuring the duration between the negative transitions in the data signal. For those negative transitions which do not fall within predetermined windows where data transitions or a start of message character should be, an error is detected and the message is discarded.

Abstract: A signal reproducing method comprising the steps of: inputting a reproduction signal of a signal which was encoded by a predetermined coding system; converting states of a plurality of portions of the waveform of the reproduction signal into numerical values in order to reproduce the input reproduction signal as the signal of a code train of "1" or "0"; and sequentially determining the portions as many as only the number specified by the coding system among the plurality of portions which were converted into the numerical values to be "1" on the basis of the magnitudes of the numerical values. By this arrangement, a signal reproducing method which can be reduced code errors of the reproduced signal may be provided.

Abstract: A running disparity circuit for 8B/10B decoding which reduces power consumption and substantially reduces the number of gates and the required silicon area by employing a combination of state type devices and combinatorial logic instead of combinatorial devices exclusively.

Abstract: In a Viterbi Algorithm decoder (204) as used to decode convolutionally encoded information, reliability information is developed for various path discard decisions made within the Viterbi Algorithm. These decisions are made for discard opportunities that impact one or more error detection windows (601). Based upon these metrics, a reliability factor sequence can be provided and compared against a fixed (or varying) threshold. When unreliability appears, appropriate action can be taken. For example, all of the information can be discarded, or only certain portions of the information can be discarded, as appropriate to the particular application.

Abstract: A signal processor which is specially adapted for decoding sequential codes, including trellis codes, convolutional codes and detecting signals in partial response channels. The processor has three units, a branch metric generator unit, an add-compare-select unit and a survivor-trace and decoding unit, each of which is independently programmable. A central control unit synchronizes operations between the units at the received symbol rate. Between synchronizations, each of the units operate concurrently and independently of the others.

Abstract: Channel encoded data (for example run length limited encoded data) is further encoded in accordance with a shift correction code prior to transmission. Upon reception, forward and backward shift errors present in the received channel encoded data are corrected by a shift correction decoder. The shift error correction is accomplished using a code, such as (for example) a BCH code over GF(p) or a negacyclic code, which treats each received symbol as a vector having p states. For a single shift error correction, p=3 and there are three states (forward shift, backward shift, no shift). In one embodiment, conventional error correction codewords which encode the user data may be interleaved within successive shift correction codewords prior to channel encoding, thereby enabling the error correction system to easily handle a high rate of randomly distributed shift errors (which otherwise would result in a high rate of short error bursts that exceed the capacity of the block error correction code).

Abstract: The anomaly handling facility provides a system for controlling conversion, detecting anomalies, providing analysis of anomaly content in an array of floating-point elements, and preserving reconstruction data to recover value accuracy typically lost when anomalies are encountered during conversion.Although the preferred embodiment specifically handles anomalies relative to the commonality of value representation by both IBM ESA/370 hexadecimal floating-point notations and ANSI/IEEE 754-1985 binary floating-point stand notations, the systematic design provided by the disclosed floating-point notation conversion anomaly handling facility can be applied to an pair of floating-point notation systems that are not totally coincident in value coverage.

Abstract: In a cell delineation circuit, an input signal is converted into parallel signals, and a plurality of parallel signals (i.e. series of parallel signals) which are shifted one bit by one bit from each other are formed from those parallel signals. CRC (Cyclic Redundancy Check) calculations are executed in parallel for the plurality of parallel signals. A series in which a pattern to be calculated satisfies a CRC rule is determined from results of the CRC calculations, and this series is generated, thereby establishing a cell delineation.

Abstract: Input values are data encoded for improved signal characteristics (e.g., limited maximum run length and limited cumulative DC-offset) so as to form "data codewords, " and then a number of the data codewords, collectively referred to as a block, are error protection encoded, preferably using a conventional linear and sytematic forward error control ("FEC") code, to yield an FEC code block. Preferably, an FEC code block is formed by generating a number of check bits or FEC bits equal to the number of data codewords in the block, and then concatenating one FEC bit and its binary complement with each data codeword, so that one FEC bit and its complement is interposed between each successive codeword.

Abstract: A circuit having a completely synchronous and digital implementation for encoding a stream of digital data (NRZ form) into the coded marked inversion (CMI) format. The circuit includes a state machine having a predetermined number of defined legal and illegal states, an illegal state detection circuit, and an output circuit. When the state machine enters an illegal state because of, for example, the effects of noise or distortion on the digital data signal, the illegal state detection circuit forces the state machine back into a legal state.

Abstract: A method for coding a binary data string for a partial-response channel having a transfer function with a spectral null at zero frequency to provide a coding rate 8/10 and an output which is invariant to 180-degree phase shifts in the channel output signal. A finite-state machine is created having two pairs of states and a plurality of codewords each corresponding to a respective binary data byte. The binary data string is encoded by said machine into a string of binary codewords having a power spectrum value of zero for a frequency of zero. In response to each successive data byte in the binary data string, there is generated one of two complementary codewords from the one of that pair of the states designated by said machine as corresponding to the data byte for the then current state of the machine.

Abstract: The invention provides a method of encoding data, e.g. video signals at a lower bit rate for use in digital transmission or recording, and a method of decoding to perform inverse transformation of the encoded data. In the coding method, a block having a plurality of input data is used as an encoding unit. The input data in each block are predicted to obtain estimates thereof. Predictive errors, which are the difference between the input data and the estimates, are evaluated, and a maximum and a minimum of the predictive errors, SX and SN, are determined. A predetermined value larger than SX-SN is used as divisor data OU, which is used in dividing the respective input data to obtain remainders E for each block. The remainders E along with information on the predictive errors, i.e., SX, SN, and OU, are encoded and outputted. In the decoding method, information on a range for the predictive errors and the divisor OU are obtained by use of transmitted additional codes.

Abstract: A method and apparatus for correcting errors in a thermometer code data array (32). A parallel A/D converter (22) comprises an array (26) of comparators and an encoder (30). The correction of errors in the data array (32) produced by the comparators (26) is accomplished by an array (24) of majority error correction gates which is placed between the array (26) of comparators and the encoder (30) in the A/D converter (22).

Abstract: In a noise shaping requantization circuit, a requantized output digital signal and an input digital signal are processed in an operational circuit whose output signal is requantized to provide the requantized output signal. The processing circuit can be configured in a variety of ways but has fixed limitations established for circuit parameters which determine the relationship between the output signal therefrom and the two input signals. By comparison with prior art noise shaping requantization circuits, a substantially better S/N ratio (assuming equal values of output signal resolution), or a substantially lower degree of output signal resolution (assuming equal values of S/N ratio) can be achieved, with stable operation.

Abstract: A circuit for eliminating illegal data sequences from a data stream is disclosed. The circuit examines a portion of an input data stream. The previously received data sequence is then examined. If the previously received data matches an illegal sequence, the stored data is altered. The stored data is then outputted to form an output data sequence.

Abstract: A high performance, low power analog to digital converter is designed in BIFET technology utilizing the high gain, high performance of a bipolar comparator and the low power of a CMOS latch and CMOS encoding logic circuits. Using a FET dynamic latch, metastability is avoided, significantly reducing soft error rate.

Abstract: A method and circuit arrangement is disclosed for converting Gray code signals into counting pulses, forming a counter status, detecting interference signals infringing the Gray code and for forming an error signal with a network defining a finite automaton according to Moore or Mealy, wherein the network forms no error signal when a Gray code infringement is followed by a second Gray code infringement. The disclosed network arrangement in one embodiment comprises a quadruple interpolator (quadrature decoder) for precision dimension measuring machines with optoelectronic scale scanning. Interruptions of the measuring procedure and errors are reduced by not generating an error signal when a Gray code infringement is followed by a second Gray code infringement.

Abstract: A circuit for randomizing data or de-randomzing previously randomized data according to a randomization scheme utilizing an irreducible generator polynomial which operates on a serial bit stream of words of data which is supplied to said circuit in a format, either LSB or MSB first, different from the format according to which the data was previously randomized or will be subsequently de-randomized. The circuit includes means for generating said irreducible generator polynomial; means for triggering said generating means in a given direction in response to a clock signal; means for exclusively ORing the contents of a bit in said generating means with a bit in said bit stream; and means for periodically interrupting said triggering means and instead setting the state of said generating means a predetermined number of states in a direction effectively the opposite to which said generating means normally generates data.

Abstract: A system for bit character synchronization of an 8/10 bit code being deserialized is provided by a deserializer with a skip bit function input used to move a character boundary one bit at a time, and 8/10 code error detector, a zero disparity character detector and skip pulse generator. After character sychronism is lost, the skip pulse generator is permitted to generate a skip pulse if the following sequence occurs: all bits of the old character boundary have been flushed through the logic circuits, at least one non-zero disparity character has been detected, and an 8/10 code error is detected. After character synchronism is re-acquired, then the skip pulse generator is no longer permitted to generate a skip pulse.

Abstract: In an encoder for use in encoding each input signal unit of N bits into each of error correcting codewords, each input signal unit is grouped into a plurality of parts which have bit lengths N1 and N2 in consideration of a transmission rate on a transmission path and which are individually encoded into partial encoded codewords which individually include redundancy signals, respectively. The partial encoded codewords may have different error correction ability and different code lengths. The partial encoded codewords are combined together into each of the error correcting codeword which may be transmitted to the transmission path at a transmission rate close to an allowable transmission rate of the transmission path. A decoder decodes each error correcting codeword into each of output signal units by dividing each error correcting codeword into divided codewords and by individually decoding the divided codewords.

Abstract: A decoder is capable of decoding on a maximum likelihood basis coded symbols of requivalently high coding rate which are produced by deleting those code bits which are located at particular positions in a time sequence of convolutional symbols of low coding rate. The decoder includes a serial-to-parallel (SP) converter for converting a serial data sequence from a dummy bit inserter into parallel sequences. The frequency division phase of the SP converter is determined by a second timing signal which the dummy bit inserter produces in synchronism with a dummy bit inserted phase. A code synchronization is established, frequency division phase synchronization is automatically established. This eliminates the need for the repetitive trial for frequency division phase synchronization only and thereby reduces a synchronization capture time.

Abstract: A data compression system implementing expansion protection employs one or more pairs of FIFOs to compare the lengths of raw and processed versions of a block of received data. The shorter version is transmitted so that the data transmitted by the data compression system is at most negligibly expanded relative to the system input. A code is inserted in the output stream to indicate the beginning of the transmission of a raw data block so that a receiving or retrieving system can determine whether the data following needs to be decompressed or not. Further codes can be injected to indicate a switch from raw data to processed data in the output of the compression system.

Abstract: An error correction circuit employs a digital averaging technique to overcome transition bit errors in a plurality of original binary bits ideally arranged as a thermometer or circular code. The circuit first generates a like plurality of intermediate signals respectively corresponding to the original bits. Each intermediate signal varies according to a weighted analog summation of a specified odd number of consecutive original bits centered about the corresponding bit. The circuit then compares the intermediate signals with corresponding further signals to produce a corrected code.

Abstract: A separate operational section for determining the degree of a polynomial is provided to increase the process speed in determining both error locator and evaluator polynomials. When a received word is decoded based on the error location found, the received word is stored in a memory and corrected and output through the designation of the address. The formula ##EQU1## is derived from the error locator equation ##EQU2## and the value of which satisfies .sigma.(.alpha.)=0 is determined to increase the process speed. The decoder and the encoder share part of the hardware to make the system compact.

Abstract: A fault detecting system is provided for detecting fault of an ADPCM codec for transcoding an input signal between an ADPCM and a PCM to produce a first code converted signal. The ADPCM codec has a data RAM for storing data used for the transcoding and is provided with a data transmitter for transmitting the data. A fault detecting processor receives the data and generates a second code conversion signal from the received data. The fault detecting processor compares the first and the second code converted signals and produces a fault signal when both of the signals are not coincident with each other. The input signal can be supplied to the fault detecting processor directly or as a part of the data transmitted thereto. The fault detecting processor can detect fault of a plurality of ADPCM codecs by a time division fashion.

Abstract: A parallel pulse transmission system, wherein the sending side converts original signals into line coded signals of a block coding type (mBnB line codes, m/2.gtoreq.2/3, n.gtoreq.3) and transmits them after aligning the timings of the blocks receiving side. The regenerates of the systems transmitted line codes and thereafter, aligns the timings of blocks of the line codes.

Abstract: Method and means for detecting any single errors introduced into an arithmetic data compression code string as a result of coding, transmission, or decoding through testing according to a modulo-n function, n being an odd number not equal to +1 or -1, an arithmetic compression coded data stream C'(s) genmerated by n-scaling an arithmetically recursive function that produces a non-scaled arithmetically data compressed code stream C(s) as a number in the semi-open coding range [0,1].