Abstract: A method and apparatus for synchronizing the execution of a sequence of graphics pipelines is provided. For a representative embodiment a sequence of graphics pipelines are connected in a daisy-chain sequence. Each pipeline operation can be controlled to operated in one of two modes. The first is a local mode where the pipeline outputs its own digital video data. The second is a pass-through mode where the pipeline outputs digital video data received from preceding graphics pipelines. The pipelines are configured to allow an application executing on a host process to select the next pipeline that will enter local mode operation. The pipeline that is selected to enter local mode operation asserts a local ready signal when it is ready to begin outputting its digital video information. Each of the pipelines monitors the state of a global ready signal. When the global ready signal becomes asserted it means that the pipeline that is selected to enter local mode operation is ready.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: A graphics processing device includes a variable performance setup engine that processes vertexes of polygons to create surface coefficients, and a rasterizer that processes the surface coefficients to create pixel values corresponding to each pixel location within each polygon. The variable performance setup engine is structured so as to provide the surface attributes of each polygon within a time that is correlated to the size of the polygon. In this manner, the overall polygon processing rate will be substantially related to the size of the polygon. By providing a short processing time for small polygons, and a longer processing time for larger polygons, the image processing rate is shown to be less dependent upon the sizes of the polygons that comprise the image. The invention thereby provides for an overall image processing rate that is substantially independent of the complexity of the image being rendered.

Abstract: Improved techniques for controlling buses of a computer system are disclosed such that peripheral devices (and/or their associated buses) can be connected or disconnected to the computer system while the computer system is active. The peripheral devices are connected to the computer system by being inserted into a slot or other receptacle of the computer system. The peripheral devices are disconnected from the computer system by being removed from a slot or other receptacle of the computer system. The slots or receptacles typically includes connectors designed to receive peripheral devices, such as PC CARD slots, expansion bays, and the like. Given that the peripheral devices can be inserted or removed while the computer system is active is active, the computer system according to the invention permits “hot-plugging” of peripheral devices. The invention is particularly well suited for controlling PCI buses for peripheral devices connecting to a computer system by way of peripheral ports.

Abstract: In an information processing apparatus, priorities are assigned to a plurality of central processing units (CPUS) and the CPUs transfer their respective display lists of drawing instructions to a drawing unit on a priority basis. With such a scheme, when a master CPU (Geometry Subsystem 0) is creating a display list (List #0-1) and a drawing unit (a rendering system) is in an idle state, a right to make an access to the drawing unit is handed over to a slave CPU (Geometry Subsystem 1), enabling the slave CPU to supply a display list (List 1-1) created thereby, if any, to the drawing unit. Receiving the display list (List #1-1), the drawing unit starts drawing processing in accordance with List #1-1. As the master CPU completes the creation of the display list (List #0-1), the slave CPU returns the right to make an access to the drawing unit to the master CPU, enabling the master CPU to supply List #0-1 to the drawing unit.

Abstract: An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer floating point operations is provided. Independent execution paths are provided for different graphics instructions to allow parallel execution of instructions which commonly occur together. The invention also optimizes the use of register file accesses to avoid, as much as possible, interference between graphics instructions needing to access a register file and other instruction accesses which would occur in combination with graphics instructions, thereby avoiding pipeline stalls and allowing parallel execution.

Abstract: An embodiment of a method for terminating direct memory access transfers from system memory to a video device includes completing a current byte transfer from a graphics controller to a video device and then refraining from initiating any further write cycles associated with a DMA transfer to the video device. The graphics controller then allows uninterrupted or atomic read and write cycles to the video device. The graphics controller also completes any current read cycles on a system bus that had previously been initiated. The graphics controller then resets its DMA engine and invalidates all information in a first-in, first-out (FIFO) storage buffer.

Abstract: An embodiment of a graphics device that maintains load balance on a graphics bus when an upgrade graphics device is installed is disclosed. The embodiment includes load balancing buffers for the strobe compliment signals AD_STB0#, AD_STB1#, and SB_STB# on a 2× mode AGP graphics device. The load balancing buffers couple the 2× mode AGP graphics device to the strobe compliment signals AD_STB0#, AD_STB1#, and SB_STB#, but the load balancing buffers are not connected to any internal circuits within the 2× mode AGP graphics device. The load balancing buffers provide equal capacitive loading between the strobe signals AD_STB0, AD_STB1, and SB_STB and their compliment signals AD_STB0#, AD_STB1#, and SB_STB# when an upgrade 4× mode AGP graphics device is installed.

Abstract: A graphics accelerator including an address remapping memory which straddles slow address spaces and fast address spaces.

Abstract: When performing gamma-compensation processing, contour adjustment processing and resolution conversion processing, in that order, for example, on prescribed picture image data, the addresses in a memory in which the functions for performing those processes are also stored in that order. The data processing apparatus can modify the order of processing in response to user inputs. A new processing order is created, and the picture image processing is carried out according to the modified order.

Abstract: The invention is a modular bus bridge that comprises an I/O controller board, an optional display, and various connectors. The connectors allow a choice of backplane mounting or cable connections. The I/O controller board interconnects bus interfaces and controls the display. The I/O controller board is connected to the display by releasable connectors, so the display may be optionally added or removed. The display allows an end-user to scroll through a menu presented on the display and select from the menu. The I/O controller board is coupled to a backplane connector for backplane mounting. A cable interface can be releasably connected to the backplane connector if cable connections are desired instead of backplane mounting.

Abstract: An image processing system is described in which a data buffer memory 4 is provided between an image processor 2 and an image frame memory 8. The data buffer memory 4 stores a sub-set of the raster lines stored within the image frame memory 8. This data can be read in either an intra-raster-line mode from adjacent memory cells within a bank or in an inter-raster-line mode from memory cell locations at corresponding positions within different banks. The data may be 8-bit pixel data or 16-bit pixel data. In the case of 8-bit pixel data a single bank contains a full raster line whereas in the case of 16-bit pixel data a single raster line extends over two banks.

Abstract: A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, or as a bridge between a system area network interface and the host bus and the system memory bus. The function of the multiple use chipset is determined at the time of manufacture of the computer system, or in the field whether an AGP bus bridge or a system area network interface is to be implemented. Selection of the type of bus bridge (AGP or system area network interface) in the multiple use core logic chipset may be implemented by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP device or a system area network interface connected to the core logic chipset.

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: A method for configuring an Accelerated Graphics Port (AGP) chipset having an AGP chipset cache. The method includes providing an operating system with a persistent data file, the persistent data file storing cache configuration parameter information for configuring the AGP chipset cache, loading the cache configuration parameter information from the persistent data file upon execution of an AGP chipset driver, and configuring the AGP chipset cache based upon the cache configuration parameter information.

Abstract: A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: This graphics system has a geometric sub-system that does not have to take into consideration memory resources for the raster sub-system of the graphics system. The graphics system sequentially receives from a host computer system data sets that define a graphic object and downloads texture data for graphics from the host computer system, so that geometric processing and rasterization are performed on the graphic object for display on a computer screen.

Abstract: A method and apparatus for rasterizing a geometric shape. A rasterizer is outfitted with a counter. The counter is started in the rasterizer and a geometric shape is rasterized in the rasterizer while the counter is counting. One or more signals are output from the rasterizer to indicate that a predetermined rasterization time for the geometric shape has been exceeded if the counter reaches a target count before rasterization of the geometric shape is completed.

Abstract: The invention is a method and apparatus of a graphic request management system which provides for storing in the header of bitmaps indicative of the last time a bitmap was included in a request as a destination or source bitmap. Where the system determines that a request is to be processed by a graphic coprocessor, the system updates the bitmap headers of the bitmaps included in that request when that request is stored in the queue of the graphic coprocessor. Where the system determines that a request is to be processed by the CPU, the system holds that request until the last operation on any bitmap included in that request, which could effect the results of the request, has been completed by the graphic coprocessor. The request, if only containing source bitmaps, is processed by the CPU immediately after the completion of any writing into all of the source bitmaps due to request stored in the queue.

Abstract: A graphics system enables an automatic choice between existing host rendering programs, existing hardware acceleration methods, and enhanced software acceleration programs for rendering graphic primitives. The graphics system accesses the speed and accuracy characterizations of a hardware accelerator attached to the system. Then, for each graphics primitive available from the enhanced software acceleration programs, the graphics system invention compares the speed and accuracy of the attached hardware accelerator with that of the enhanced software acceleration programs. The graphics system invention then selects which graphics primitives should be rendered by the enhanced software acceleration programs and which graphics primitives should be rendered by the attached hardware accelerator.

Abstract: An operation for combining multiple video streams permits combining any number of overlay images and base images regardless of processes performed upon one or more of the images. Specifically, where the base images are dynamically sized and resized to provide a constant frame rate (despite varying frame complexity), the process similarly treats overlay images and even other base images. In the dynamic sizing process, a rendering time is compared to high and low water marks. During dynamic resizing, two double buffering operations and a synchronization operation are performed. After dynamic sizing and resizing, the resulting resized images are combined together, regardless of the frame rate of the individual images. Consequently, multiple video streams at varying frame rates are combined at a constant frame rate.

Abstract: A device and method to eliminate contention for an accelerated graphics port (AGP). A video system includes an accelerated graphics port, a first location adapted to receive and couple an AGP controller to the accelerated graphics port, a second location adapted to receive and couple an AGP graphics accelerator chip to the accelerated graphics port, and at least one connector coupled to the accelerated graphics port that is adapted to receive an AGP graphics accelerator add-in card. Further, a device is coupled to the accelerated graphics port that selectively disables an AGP graphics accelerator chip coupled to the second location or an AGP graphics accelerator add-in card coupled to the connector.

Abstract: Graphically intense utility programs for an industrial control system, requiring the same operating system as is used to run the control program, are run on remote computers having insufficient memory or processing power to support the operating system, by using a shell program executing on a control-computer to run the utilities. The shell program uses the control-computer's operating system except for calls to the remote computer's display or its manual input devices which are routed to a virtual machine updated periodically by communication with the remote machine.

Abstract: A write blocking accelerator provides maximum concurrency between a central processing unit (CPU) and the accelerator by allowing writes to the front buffer of a dual-buffered system. The CPU issues a series of drawing commands followed by a "page flip" command. When a command parser within the accelerator receives a page flip command, it notifies a screen refresh unit reading from the front buffer that the command was received. The screen refresh unit signals a memory interface unit (MIU) to enter a write blocking mode and provides the address of the current line in the front buffer from which the screen refresh unit is reading, and the address of the last line in the front buffer. The MIU blocks all writes from drawing engines that fall into the range defined between the two addresses. The screen refresh sends updated front buffer addresses to the MIU as display data is read out of the front buffer. Accordingly, the blocked address range constantly shrinks until all writes are allowed by the MIU.

Abstract: A method and apparatus for a processing system to utilize a ring buffer includes a host processor, memory, and at least one co-processor. The host processor generates a plurality of data blocks that relates to a particular application (e.g., word processing application, drafting application, presentation application, spreadsheet application, video game application, etc.). The host processor writes data elements of the data blocks into the memory, which is organized in a ring buffer manner. As the host processor enters the data elements into the ring buffer, it updates a head pointer, which indicates the most current address of a data element entered into the ring buffer, in its local cache. The co-processor retrieves the data elements from the ring buffer and performs a co-processor function in support of the particular application.

Abstract: A system for the storage of a digital image in an image database, the system comprises: a processor; software for automatically generating with said processor open space metadata from the digital image independent of manually inputting data; and software for storing the open space metadata along with the associated image in the image database.

Abstract: An address generating and mapping device of a video capture system includes: a microprocessor having a counter counted by being synchronized with a horizontal synchronizing signal of a video signal, an address port for outputting an address to be used when reading from a memory, and a counter port for outputting the counter value and a bank selection signal by using predetermined higher bits among the counter output as the bank selection signal for selecting data banks of the memory; a counter for performing a predetermined operation according to a signal for selecting a mode, when a mode for generating an address necessary for storing the video signal is referred to as an address generating mode and a mode for mapping an address necessary for accessing the memory is referred to as an address mapping mode; multiplexers for outputting a counter value from the microprocessor to higher addresses of the memory when the mode selection signal is the address generating mode and outputting the addresses output from t

Abstract: The present invention discloses methods and apparatus for implementing automatic graphics operations with selectable triggering mechanism. One mechanism is hardware related, using the vertical counter in the video control section of the graphics processor. The other mechanism is software related, using the host to directly command the graphics processor. The graphics operations are specified in the header file written by the host in the frame buffer memory. Several header files can be chained together to form a sequence of header files corresponding to very complex graphics operations. Automatic graphics operations, therefore, can be completed without further host intervention resulting in powerful graphics, video, and animation performance.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-ship frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: A computer system having a core logic chipset that interconnects a processor(s), a system memory and peripheral device agents. The core logic chipset has a programmable memory access arbiter that may be programmed to optimize accesses by the computer system processor(s) and agents to the system memory for best computer system performance. The memory access arbiter may be programmed specifically for each system agent. An access count register may be incorporated into the core logic chipset wherein each system agent may be represented by a portion of the access count register. The values programmed into the portions of the access count register determine how many memory accesses the associated agent may take before another agent is granted a memory access, and how many cachelines may be transferred during a memory access.

Abstract: A multiprocessor unit (11) for a printer system. The multiprocessor unit (11) is comprised of a master processor (21) and multiple parallel processors (22). The processing unit (11) interprets a page description program or some other graphics programming. A master processor (21) selects certain interpretation tasks that are to be executed as "cofunctions" and queues these tasks. Cofunctions of the same type are placed in the same queue (30). Parallel processors (22) access the queues and execute the cofunctions.

Abstract: A graphics controller (IMC) which performs pointer-based and/or display list-based video refresh operations that enable screen refresh data to be assembled on a per window or per object basis, thereby greatly increasing the performance of the graphical display. The graphics controller maintains pointers to various buffers in system memory comprising video or graphics display information. The graphics controller manipulates respective object information workspace memory areas corresponding to each object or window, wherein the workspace areas specify data types, color depths, 3D depth values, alpha blending information, screen position, etc. for the respective window or object on the screen. Each workspace area also includes static and dynamic pointers which point to the location in system memory where the pixel data for the respective window or object is stored.

Abstract: A system is provided for achieving high speed data transfers from a host memory to an ancillary processor, where the ancillary processor is preferably a geometry accelerator of a graphics machine. In accordance with a preferred embodiment, the system includes at least one memory segment having at least one enable bit and a starting address. The system further includes a data transfer queue defined in a portion of the host memory beginning at the starting location, where the data transfer queue has at least one header portion and at least one data portion, the header portion including at least one data ready bit that is indicative of whether the associated block of data is ready to be transferred to the ancillary processor.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes a pixel data striping control logic which determines whether fetch and store requests by the graphics processor crosses an X boundary in the internal SRAM devices. If a fetch or store request crosses an X boundary, the memory control logic stripes the access into separate blocks of pixel data for each access which are then simultaneously accessed during a single data request cycle.

Abstract: A 3D graphics accelerator operates in parallel with a host central processing unit (CPU). Software executing on the host CPU performs transformation and lighting operations on 3D-object primitives such as triangles, and generates gradients across the triangle for red, green, blue, Z-depth, alpha, fog, and specular color components. The gradients for texture attributes are also generated and sent to the graphics accelerator. Both the graphics accelerator and the CPU software perform triangle edge and span walking in synchronization to each other. The CPU software walks the triangle to interpolate non-texture color and depth attributes, while the graphics accelerator walks the triangle to interpolate texture attributes. The graphics accelerator performs a non-linear perspective correction and reads a texture pixel from a texture map. The texture pixel is combined with a color pixel that is received from the CPU software interpolation of non-texture attributes.

Abstract: A coprocessor system is disclosed in which a CPU in a game machine body and a CPU in a game cartridge are formed by CPU cores having the same architecture and memory mapping functions. The cycle time of a second CPU, for example the CPU in the game cartridge, is shorter than the cycle time of the first CPU, for example the CPU in the game machine body. The first CPU accesses memory during a first time period that is longer than the program memory access time but shorter than the first CPU cycle time. The second CPU accesses the program memory during a second time period, which is the time difference between the end of the first time period and the end of the first CPU's cycle time. The second CPU may also access the program memory during the first time period if no first CPU memory access is pending. Since the first CPU's memory access during the first time period has priority over the second CPU's, the first CPU never waits to access shared memory.

Abstract: A graphics processor is disclosed having two processing units and two dual-port RAMs for passing data between the processing units. The hardware is configured to detect whether input data is primitive information or pass-through information. If it is the former, the information is processed as a primitive. If it is the latter, the hardware determines whether one of the dual-port RAMs is available. If so, the available RAM is converted into a pass-through FIFO, and the pass-through information is stored therein. An output process operates continually to send primitive results and pass-through information from the pass-through FIFO out of the graphics processor output as the information becomes available, and ensures that the correct ordering of the information is maintained. If necessary, and if both RAMs are available, both of the dual-port RAMs in the graphics processor may be used as pass-through FIFOs at the same time.

Abstract: A video controller in a graphic accelerators suitable for use in three dimensional graphics and texture mapping is disclosed. The controller includes an address generator for generating addresses for reading out texture data stored in the video memory and a mode register for generating a directional signal for prefetching the texture data. A prefetch controller is provided to produce an address for another texture data predicted to be used at the next time, based on the directional signal supplied from the mode register and the address of the address generator. Also provided are a memory controller for accessing the texture data corresponding to the address generated in the prefetch controller via the memory interface, and a buffer memory for storing the prefetched texture data outputted from the memory controller and the address of the prefetched texture data.

Abstract: A method and apparatus for co-processing multi-formatted data which begins when a host processor writes data blocks, in a substantially continuous manner, into memory. Each of the data blocks includes a plurality of data elements and each data element has one of a plurality of data formats. As the data block is being stored in memory, a co-processor retrieves selected data elements from the memory. Upon retrieving the selected data elements, the co-processor interprets them to identify the data format. If the data format is consistent with the data format of the co-processor, the co-processor processes the data element without conversion. If, however, the data format of the selected data element is not consistent with the data format of the co-processor, the co-processor converts the format of the selected data element into the format consistent with the co-processor.

Abstract: A method for drawing graphics is carried out in a graphics processing and display system. The system has a display unit, a host for generating graphics data defining graphics images to be displayed on the display, a graphics controller for receiving information from the host and controlling graphics to be displayed, a frame buffer memory for storing graphics data, an index register for receiving an index value from the host and a coordinate register for storing a coordinate value which is obtained by the graphics controller. With the method, when a line graphics is draw, only information regarding two coordinates are used in the graphics controller by incrementing the index value by an increase which is specified according to the selected object-type. When a triangle graphics is drawn, only information regarding three coordinates are used in the graphics controller.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. One of the feature flags is used as a Present Bit for a corresponding memory page.

Abstract: A display system includes an input device sending information on a vehicle bus to a display controller. Based upon the information from the input device, the display controller selects one of a plurality of graphics stored on a local memory. The selected graphic is displayed on a display by the display controller.

Abstract: A highly integrated, single chip computer system having not only a central-processing unit (CPU) but also specialized coprocessors. The specialized coprocessors, for example, enable the single chip computer system to be reasonably sized, yet perform high quality video (e.g., MPEG-2) and graphics operations (e.g., three-dimensional graphics). The single chip computer system offers improved performance of video and graphics operations, resource scheduling and security. The improved security offered by the single chip computer system enables program code or data stored external to the single chip computer system to be encrypted so as to hinder unauthorized access, while internal to the single chip computer system the program code or data is decrypted. The single chip computer system is particularly suitable for video game consoles having high quality graphics and/or video, digital video disk (DVD) players, and set-top boxes.

Abstract: A multimedia display system includes a central processing unit, a storage device associated with the central processing unit, a standard interface bus to which the central processing unit and the storage device are connected, a graphics processor connected to the bus for generating graphics data in response to commands from the central processor, a digitizer for converting an analog video signal to digital form and for producing synchronization signals, a video processor for processing the digitized video data to produce pixel representations of the digitized video signal, a shared frame buffer for storing the graphics data generated by the graphics processor and the pixel representations of the video signal, a device for converting the stored digital data to a data stream appropriate for driving a video monitor, and a video monitor for displaying the graphics data and the video information, wherein the video processor generates a programmable variable phase vertical synchronization signal for synchronizing v

Abstract: A Digital Elevation Database is converted to a Polygon Database by creating square cells of varying sizes, starting with a minimum size cell. A center elevation point in the cell is used to form four three-dimensional triangles. The points within the cell are then tested against the flatness criteria. If the cell meets the flatness criteria it is expanded and tested again. This goes on until the cell fails the flatness criteria or a maximum specified cell size is reached. The cell parameters for the last trial cell meeting the flatness criteria or the maximum specified cell size are then entered into the polygon database. The points in the cell are then removed from the elevation database and the process starts over until all the points have been processed. In a second embodiment the procedure starts with a maximum size cell and the cell size is reduced until the cell meets the flatness criteria.

Abstract: A multi-display video system for ensuring the proper synchronization of scene switching. Before each display switches to pixel data corresponding to the next scene to be rendered, new pixel data is written into a currently unused bank of frame buffer memory within a corresponding graphics accelerator. When each graphics accelerator in the video system has completed writing the new pixel data to its respective frame buffer, the scene switch may take place. Each graphics accelerator is configured to display an image corresponding to the next scene in response to the indicator output signal indicating that the pixel data updates for all graphics accelerators are complete.

Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.

Abstract: A software queue located in an offscreen portion of video memory is used as a large-capacity software queue for queuing messages to a graphics accelerator. Although the software queue is typically stored in a dynamic RAM (DRAM) memory, advantages of faster static RAM (SRAM) are achieved by shadowing some of the queuing information in SRAM. Usage of a large-capacity software queue in video DRAM memory and information shadowing in faster SRAM memory achieves an advantageous balance between throughput speed and queue size. The large-capacity of the software queue ensures that the queue is virtually never filled to capacity so that delays while awaiting free space in the queue are virtually never incurred. The capacity of the software queue is determined in software and is therefore adaptable to match a particular graphics application.

Abstract: A video game device is disclosed which is composed of a console apparatus in which a processor is installed to execute a game software program. The video game device also includes a memory device, such as a memory cartridge which is removably attached to the console apparatus and which stores the game program. An enhanced function board is attached to the main body of the video game device for improving and enhancing the functions of the video game. The enhanced function board includes a pair of buses, first and second digital processors connected to the buses, a FIFO memory connected between the buses, and an interface circuit connected to the pair of buses. The interface circuit operates to connect the first and second digital processors to the processor of the video game device.