Abstract: A dataflow graph has operation units that are configured to be producer operation units to produce tensors for execution of the application, and to be consumer operation units to consume the tensors for execution of the application. Compile time logic is configured to process the dataflow graph to determine, for the tensors, expected producer memory layouts, expected consumer memory layouts, and current memory layouts. The expected producer memory layouts specify memory layouts required by the producer operation units that produce the tensors. The expected consumer memory layouts specify the memory layouts required by the consumer operation units that consume the tensors. The current memory layouts specify the memory layouts of the tensors. Each of the memory layouts includes a vector dimension and at least one of a vector ordering and a data alignment.

Abstract: In some aspects, systems and methods provide for forming groupings of a plurality of independently-specified computation workloads, such as graphics processing workloads, and in a specific example, ray tracing workloads. The workloads include a scheduling key, which is one basis on which the groupings can be formed. Workloads grouped together can all execute from the same source of instructions, on one or more different private data elements. Such workloads can recursively instantiate other workloads that reference the same private data elements. In some examples, the scheduling key can be used to identify a data element to be used by all the workloads of a grouping. Memory conflicts to private data elements are handled through scheduling of non-conflicted workloads or specific instructions and/or deferring conflicted workloads instead of locking memory locations.

Abstract: An embodiment method for converting an initial digital image into a converted digital image, electronic chip, system and computer program product are disclosed, the initial digital image comprising a set of pixels, the pixels being associated respectively with colors, the initial digital image being acquired by an acquisition device, and the converted digital image able to be used by a neural network. The embodiment method comprises redimensioning of the initial digital image in order to obtain an intermediate digital image, the redimensioning being carried out by a reduction in the number of pixels of the initial image, modification of a format of one of the pixels of the intermediate digital image in order to obtain a converted digital image, the modification being carried out, after the redimensioning, by increasing the number of bits used to represent the color of the pixel.

Abstract: A memory system, a memory controller and an operating method are disclosed. When a target command which instructs an operation of writing target data to a memory device is received from a host, the target data is divided into data units, and a first data unit among the data units is controlled such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device. As a consequence, it is possible to write data in specific units in a memory system using a multi-core.

Abstract: Disclosed techniques relate to memory space management for graphics processing. In some embodiments, first and second graphics cores are configured to execute instructions for multiple threadgroups. In some embodiments, the threads groups include a first threadgroup with multiple single-instruction multiple-data (SIMD) groups configured to execute a first shader program and a second threadgroup with multiple SIMD groups configured to execute a second, different shader program. Control circuitry may be configured to provide access to data stored in memory circuitry according to a shader memory space. The shader memory space may be accessible to threadgroups executed by the first graphics shader core, including the first and second threadgroups, but is not accessible to threadgroups executed by the second graphics shader core. Disclosed techniques may reduce latency, increase bandwidth available to the shader, reduce coherency cost, or any combination thereof.

Abstract: Generating signatures within a network that includes a plurality of computing devices of varying processing capabilities is disclosed. Chips may be transmitted, from a network video recorder and over the network, to an analytics appliance having a GPU processing power that is higher than a GPU processing power possessed by the network video recorder. The GPU processing power possessed by the analytics appliance may be employed to process the chips therein and generate respective signatures.

Abstract: A method, a device, an apparatus for identifying a graphics card of a GPU server, and a medium are provided. The method includes: obtaining correlation information of a graphics card captured by an operation of enumerating PCI devices during a startup process of running a BIOS; determining whether the graphics card belongs to a preset category; reading a memory address of the graphics card in a configuration space of the PCI device in a case that the graphics card belongs to the preset category, and obtaining an actual memory address based on the memory address and an offset; and resetting the graphics card based on the actual memory address, and sending a restart instruction to perform a restart operation.

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

Abstract: A storage apparatus includes a storage device that stores a table mapping a logical address to a physical address and a controller that manages the table and controls write of data to and read of data from the storage device according to a request from a host. The controller allocates, in a memory, a cache area for temporarily storing a part of the table, and a write buffer area for storing a part of the table that has been updated by the host and is to be written to the storage device, upon receipt of a request that requires update of the table from the host, determines whether a first part of the table to be updated is in the write buffer area, and upon determining that the first part is in the write buffer area, updates the first part in the write buffer area according to the request.

Abstract: An image processing apparatus in which image processing is executed by each of objects of an object group in which the objects each executing the image processing are connected to one another in a directed acyclic graph form, includes: a division portion that divides image data, which is a target of the image processing, into plural first divided image data pieces when the image processing is processing having sequentiality in processing sequence; and a control portion that makes control to enable computing devices to execute first partial processings in parallel, the first partial processings being pieces of the image processing to be performed on the first divided image data pieces and being allowed to be processed in accordance with dependent relations with front and rear stages and a processing sequence dependent relation.

Abstract: Aspects of the subject disclosure may include, for example, obtaining image content over a communication network, determining a predicted viewpoint of a user associated with the image content, and adjusting the image content to equirectangular image content according to the predicted viewpoint. Further aspects can include downscaling the equirectangular image content according to a display capability of a mobile device resulting in a downscaled equirectangular image content, cropping the downscaled equirectangular image content resulting in a cropped equirectangular image content, and providing, over the communication network, the cropped equirectangular image content to the mobile device. Other embodiments are disclosed.

Abstract: Methods, systems, and devices for graphics processer unit (GPU) operations are described. A device may monitor one or more states of a GPU during a duration. Based on monitoring the one or more GPU states, the device may determine an execution of a GPU command that is common to at least two GPU operations for clearing the GPU buffer. The device may determine whether the GPU clear command has previously been executed during a duration or a GPU cycle in which the device monitored the GPU states. The device may process the GPU clear command based on the determination of whether the GPU clear command has previously been executed. For example, the device may drop the GPU clear command based on the determination or modify a portion of the GPU clear command and execute at least the modified portion of the GPU clear command.

Abstract: A method for graphics processing. The method including rendering graphics for an application using a plurality of graphics processing units (GPUs). The method including dividing responsibility for the rendering geometry of the graphics between the plurality of GPUs based on a plurality of screen regions, each GPU having a corresponding division of the responsibility which is known to the plurality of GPUs. The method including generating information regarding a piece of geometry with respect to a first screen region for which a first GPU has a first division of responsibility, while rendering the piece of geometry at a second GPU for an image. The method including rendering the piece of geometry at the first GPU using the information.

Abstract: A computer implemented method uses memory coherence to enhance latency and bandwidth performance, the method including receiving, by a host, a call from an application. The method also includes, determining that the call includes a device allocation command, wherein the device allocation command is configured to allocate a set of data on a graphical processing unit. The method further includes intercepting the call. The method includes, initiating an alternate data allocation command; and returning the alternate data allocation command to the application. Further aspects of the present disclosure are directed to systems and computer program products containing functionality consistent with the method described above.

Abstract: An apparatus, a system, and a method for allocating power to a graphics processing unit, where the apparatus includes a frame rate detection module configured to detect a frame rate of current image data to-be-displayed, and a power allocation module configured to: determine whether the frame rate is lower than a preset frame rate threshold; if the frame rate is lower than the preset frame rate threshold, determine that displaying of the image data is in a frame freezing state; determine, in response to the frame freezing state, whether a graphics processing unit reaches a power bottleneck state; and if determining that the graphics processing unit reaches the power bottleneck state, increase power of the graphics processing unit and reduce power of another module related to the displaying.

Abstract: Examples disclosed herein may involve (i) obtaining 2D image data and 3D sensor data that is representative of an area, (ii) identifying a first set of pixels associated with ephemeral objects detected in the area and a second set of pixels associated with non-ephemeral objects detected in the area, (iii) identifying a first set of ephemeral 3D data points associated with the detected ephemeral objects and a second set of non-ephemeral 3D data points associated with the detected non-ephemeral objects, (iv) mapping the first and second sets of 3D data points to a grid of voxels associated with the area, (v) making a determination that one or more voxels in the grid each contain a threshold extent of ephemeral data points, and (vi) based at least in part on the determination, filtering the 3D sensor data to remove the 3D data points contained within the one or more voxels.

Abstract: In graphics processing data is received representing one or more vertices for a scene in a virtual space. A projection of the vertices onto a screen space of a display device is performed. A density of the vertices is adjusted for selected portions of the screen space, such that a lower density of vertices is present in selected portions of the screen space. Primitive assembly is performed on the vertices to generate a one or more primitives in screen space from the projection of the vertices onto the screen space. A finished frame is then generated by performing pixel processing to assign pixel values to the pixel or pixels that are part of the corresponding primitives. In some implementations, the finished frame can be stored in the memory or displayed on the display device.

Abstract: Described herein are techniques for removing control of a display from an operating system. The disclosed techniques decouple operation of the physical display device from control of the operating system so that the display device may be powered down while not needed during streaming. The device driver for the graphics card, into which a display device cable is plugged, simulates operation of the display but allows the display to be powered down. Simulating the display involves properly responding to queries or commands from the operating system, and generating the signals that would be expected from the display device by the operating system. While simulated in this manner, whether the display device is actually powered down does not matter to the operation of an application being streamed, because the operating system still “believes” the display device is powered on. Thus application streaming is not interrupted by powering down the display device.

Abstract: A processor and an instruction scheduling method for X-channel interleaved multi-threading, where X is an integer greater than one. The processor includes a decoding unit and a processing unit. The decoding unit is configured to obtain one instruction from each of Z predefined threads in each cyclic period, decode the Z obtained instructions to obtain Z decoding results, and send the Z decoding results to the processing unit, where each cyclic period includes X sending periods, one decoding result is sent to the processing unit in each sending period, a decoding result of the Z decoding results may be repeatedly sent by the decoding unit in a plurality of sending periods, wherein 1?Z<X or Z=X, and wherein Z is an integer. The processing unit (32) is configured to execute the instruction based on the decoding result.

Abstract: A method of transmitting an audio and/or audiovisual content to a receiver. The method starts with receiving a determined stream broadcast on a network and playing back the contents transmitted by the stream in the receiver. Then a first event external to the receiver is detected and triggers interruption of the playback of the content in progress and recording of the instant of the interruption. Sometime later, a second external event triggers a transmission, from the receiver to a remote server, of the instant dating the first event and of a request for resuming the playback of the interrupted content. A piece of information specifying the identifiers of the data packets of the content at the instant of the interruption is then transmitted from the remote server to the receiver. Finally, the receiver receives the identified data packets and replays the content of the packets.

Abstract: Described herein are techniques for generating a stitched shader program. The techniques include identifying a set of shader programs to include in the stitched shader program, wherein the set includes at least one multiversion shader program that includes a first version of instructions and a second version of instructions, wherein the first version of instructions uses a first number of resources that is different than a second number of resources used by the second version of instructions. The techniques also include combining the set of shader programs to form the stitched shader program. The techniques further include determining a number of resources for the stitched shader program. The techniques also include based on the determined number of resources, modifying the instructions corresponding to the multiversion shader program to, when executed, execute either the first version of instructions, or the second version of instructions.

Abstract: In example implementations, an apparatus is provided. The apparatus includes a first interface, an upstream device detector, a second interface, and a processor. The first interface receives a multi-channel connection. The upstream device detector is to detect a connection to external graphical processor unit (eGPU) via the first interface. The second interface is to connect a peripheral device that transmit data over the multi-channel connection via the first interface through the eGPU and to a host computer. The processor disables a portion of the multi-channel connection on the first interface when the upstream device detector detects the connection to the eGPU.

Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.

Abstract: A GPU virtualization method based on a container comprises the steps of: transmitting, if the container is created, a configuration file including GPU resource constraint information and an API profile to the container, by a node controller; and implementing a virtual GPU, when the container is executed, by intercepting a library call and changing an argument related to a GPU resource amount by a library controller provided in the container, and by intercepting a system call and changing argument and return values by a system call controller.

Abstract: A video processing apparatus includes a programmable hardware encoder configured to execute an encoding process on a plurality of input video frames. The video processing apparatus further includes a controller coupled with the programmable hardware encoder. The controller is configured to execute a set of instructions to cause the video processing apparatus to: determine first information of the plurality of input video frames, and adjust the encoding process based on the first information.

Abstract: Described herein are systems, methods, and non-transitory computer readable media for memory address encoding of multi-dimensional data in a manner that optimizes the storage and access of such data in linear data storage. The multi-dimensional data may be spatial-temporal data that includes two or more spatial dimensions and a time dimension. An improved memory architecture is provided that includes an address encoder that takes a multi-dimensional coordinate as input and produces a linear physical memory address. The address encoder encodes the multi-dimensional data such that two multi-dimensional coordinates close to one another in multi-dimensional space are likely to be stored in close proximity to one another in linear data storage. In this manner, the number of main memory accesses, and thus, overall memory access latency is reduced, particularly in connection with real-world applications in which the respective probabilities of moving along any given dimension are very close.

Abstract: An image processing apparatus of the technique of this disclosure includes processing units, storage units, a control unit, dividing units which divide image data, and combining units which combine image data. The control unit specifies processing for which image data is divided according to a status of use of the storage units. The control unit causes one of the image processing units to process one of parts of image data divided based on a dividing position, combines the processed part of image data with the other part of image data, causes the other of the image processing units to process the other of parts of image data, the other of parts of image data being not processed by the one of the image processing units, and combines the processed part of image data with the one part of image data.

Abstract: Video or graphics, received by a render engine within a graphics processing unit, may be segmented into a region of interest such as foreground and a region of less interest such as background. In other embodiments, an object of interest may be segmented from the rest of the depiction in a case of a video game or graphics processing workload. Each of the segmented portions of a frame may themselves make up a separate surface which is sent separately from the render engine to the display engine of a graphics processing unit. In one embodiment, the display engine combines the two surfaces and sends them over a display link to a display panel. The display controller in the display panel displays the combined frame. The combined frame is stored in a buffer and refreshed periodically.

Abstract: An organic light-emitting display device includes a data converter which generates, using first data corresponding to a first type and supplied from an external device, second data corresponding to a second type different from the first type, and generates, using the second data, third data corresponding to a third type different from the first or second type, and a display unit which displays, using a plurality of unit pixels, an image corresponding to data output from the data converter. Each of the unit pixels includes a first subpixel and a second subpixel disposed on a first column, and third subpixels disposed on a second column parallel to the first column. The data converter generates the second data based on an arrangement of the first to third subpixels.

Abstract: The present disclosure provides a method for driving a display device and a driver. The method includes obtaining image data; determining whether the image pixels are detail pixels according to the image data; determining a plurality of screen pixel groups; and driving the screen pixels for display.

Abstract: A method for graphics processing. The method including rendering graphics for an application using a plurality of graphics processing units (GPUs). The method including using the plurality of GPUs in collaboration to render an image frame including a plurality of pieces of geometry. The method including during a pre-pass phase of rendering, generating information at the GPUs regarding the plurality of pieces of geometry and their relation to a plurality of screen regions. The method including assigning the plurality of screen regions to the plurality of GPUs based on the information for purposes of rendering the plurality of pieces of geometry in a subsequent phase of rendering.

Abstract: A first electronic device according to various embodiments of the present invention comprises: a communication module; a touch screen; and a processor, wherein the processor receives first data, from a second electronic device registered with the first electronic device, representing the second electronic device via the communication module, and, in response to the movement of the second electronic device to the touch screen, displays second data, corresponding to the first data, on a first area of the touch screen corresponding to the movement of the second electronic device.

Abstract: A method for graphics processing. The method including rendering graphics for an application using graphics processing units (GPUs). The method including using the plurality of GPUs in collaboration to render an image frame including a plurality of pieces of geometry. The method including during the rendering of the image frame, subdividing one or more of the plurality of pieces of geometry into smaller pieces, and dividing the responsibility for rendering these smaller portions of geometry among the plurality of GPUs, wherein each of the smaller portions of geometry is processed by a corresponding GPU. The method including for those pieces of geometry that are not subdivided, dividing the responsibility for rendering the pieces of geometry among the plurality of GPUs, wherein each of these pieces of geometry is processed by a corresponding GPU.

Abstract: A system and method allocates partitions to be used to perform a query to multiple GPUs and each partition is also allocated to a CPU to which the GPU is attached. The GPUs use any assigned data in GPU memory, and otherwise request it from a CPU, which provides it from CPU memory if possible, and otherwise copies it from long term storage, CPU memory and makes it available to GPU memory. The GPUs process the query against the partitions assigned, optionally by performing portions of the query at a time, for example performing an innermost nested query and then performing the next outermost nested query. The results from any given portion of a query may be accumulated across all GPUs and some or all of the results distributed to each of the GPUs. The remaining work may be balanced by redistributing only some of the accumulated results.

Abstract: An adaptive mechanism may include a receiver, an Arithmetic Logic Unit (ALU) identifier, and an assignment module. The receiver may receive tasks representing iterations of inexact algorithms. Each task may have a corresponding iteration power level. The ALU identifier may identify a set of available ALUs. Each ALU may have a corresponding ALU power level. The assignment module may assign tasks to available ALUs to optimize a total ALU power used.

Abstract: Systems and methods for charting audio files and/or attributes of audio files associated with a spreadsheet are provided. For instance, when an audio file is associated with a spreadsheet, the audio file may be treated as a new type of data within the spreadsheet. In some aspects, a plurality of audio files may be associated with a spreadsheet, e.g., within a single cell or within a range of cells. In some aspects, the audio files themselves, as well as audio data (e.g., modulated data representing soundwaves, etc.), audio attributes (e.g., frequency, amplitude, sampling rate, codec, bitrate, volume, pitch, speed, channel, audio effects, author/artist, creation date and/or time, file name, file size, duration, etc.), and/or spreadsheet data (e.g., values in cells, user comments, etc.) may be incorporated into a report (e.g., a chart) using a spreadsheet charting function, either automatically or by user selection.

Abstract: Technologies for management of data layers in a heterogeneous geographic information system (GIS) map are disclosed. A compute device may maintain a GIS database that includes geo-quads that represent physical locations of various scales. Data layers and layer tracks may be dynamically added to the GIS database at different scales, allowing for an extensible framework that enables a mechanism for integrating additional functionality. In the illustrative embodiment, a graph database is used to store the GIS database, allowing for a flexible structure. In some embodiments, entries in layer tracks may include binary large objects that may have properties and associated methods, allowing for application-specific functionality.

Abstract: A method for managing backups includes obtaining a plurality of parameters for a data item, filtering the plurality of parameters to obtain a plurality of filtered parameters, evaluating each filtered parameter of the plurality of filtered parameters to obtain a plurality of evaluated parameters, updating a promotion parameter register based on the plurality of evaluated parameters, and processing a backup request using the promotion parameter register, wherein the backup request specifies the data item.

Abstract: An electronic device according to one embodiment of the present invention can comprise a display panel, a display controller, a memory, and a processor electrically connected to the display panel, the display controller, and the memory.

Abstract: An image processing apparatus includes a processor configured to process an image; a reading direct memory access controller (DMAC) configured to read data from the memory; a writing DMAC configured to write data to the memory, each DMAC configured to control direct memory access to a memory; an upper first-in first-out (FIFO) unit connected to the reading and writing DMACs and includes FIFOs of the number equal to the number of channels of each of the reading and writing DMACs and a lower FIFO unit connected between the upper FIFO unit and the processor and includes FIFOs that correspond to the FIFOs of the upper FIFO unit at a ratio of 1 upper FIFO unit to F lower FIFO units (F being an integer equal to 2 or larger).

Abstract: In a multi-GPU simulation environment, frame buffer management may be implemented by multiple GPUs rendering respective frames of video, or by rendering respective portions of each frame of video. One of the GPUs controls HDMI frame output by virtue of receiving frame information from the other GPU(s) and reading out complete frames through a physically connected HDMI output port. Or, the outputs of the GPUs can be multiplexed together.

Abstract: A mechanism is described for facilitating consolidated compression/de-compression of graphics data streams of varying types at computing devices. A method of embodiments, as described herein, includes generating a common sector cache relating to a graphics processor. The method may further include performing a consolidated compression of multiple types of graphics data streams associated with the graphics processor using the common sector cache.

Abstract: Provided are computer-implemented methods and systems for optimization of publication of an application to a web browser. An example method for optimization of publication of an application to a web browser may include capturing, by a server-side agent, a video frame of a virtual screen associated with the application. The method may further include comparing, by the server-side agent, the video frame to a previous video frame of the virtual screen to detect a change in the video frame. The method may continue with generating, by the server-side agent, an image of the change based on the detection. The method may further include sending, by the server-side agent, the image of the change to a client device. The virtual screen may be re-rendered on the client device based on the image of the change and the previous video frame.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. In an example apparatus, an input/output (I/O) device can receive signaling that includes a command to write to or read data from an address corresponding to a non-persistent memory device, and can determine where to redirect the request. For example, the I/O device can determine to write or read data to and/or from the non-persistent memory device or the persistent memory device based at least in part on one or more characteristics of the data.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes an allocation circuit that allocates a single level cell block of a plurality of single level cell blocks to a first stream in response to a multi level cell block of a plurality of multi level cell block being allocated to the first stream.

Abstract: The present invention relates to an acceleration method for an FPGA-based distributed stream processing system, which accomplishes computational processing of stream processing operations through collaborative computing conducted by FPGA devices and a CPU module and at least comprises following steps: building the FPGA-based distributed stream processing system having a master node by installing the FPGA devices on slave nodes; dividing stream applications into first tasks suitable to be executed by the FPGA devices and second tasks suitable to be executed by the CPU module; and where the stream applications submitted to the master node are configured with kernel files that can be compiled and executed by the FPGA devices or with uploading paths of the kernel files, making the master node allocate and schedule resources by pre-processing the stream applications.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: Implementations of enhanced content collaboration technology are disclosed herein. In an implementation, a collaboration service determines which collaboration commands to surface in association with each user in a list of users collaborating on a document. The collaboration commands are selected based on each user's collaboration state. The service updates local applications with information indicative of the user state, so that the local applications may surface a user-specific, collaboration state-driven selection of commands.

Abstract: Systems and methods are provided that may be implemented to enable the same internal display panel assembly (e.g., HDR display panel assembly) of an information handling system to support proper operation with image data provided from different types of graphics processing units (GPUs). A single configuration or type of the internal display panel assembly may be provided within the system to support graphics from one or more GPUs from multiple different graphics suppliers, and one or more programmable integrated circuits of the system may be configured to communicate information or signal/s to a timing controller (TCON) of the internal display panel assembly that corresponds to a proper DPCD profile or interface specification selection for use with a currently-selected GPU of the system.

Abstract: Embodiments described herein provide a graphics, media, and compute device having a tiled architecture composed of a number of tiles of smaller graphics devices. The work distribution infrastructure for such device enables the distribution of workloads across multiple tiles of the device. Work items can be submitted to any one or more of the multiple tiles, with workloads able to span multiple tiles. Additionally, upon completion of a work item, graphics, media, and/or compute engines within the device can readily acquire new work items for execution with minimal latency.