Abstract: An image forming apparatus includes first and second processors controlling first and second image formers that form first and second images using color material having first and second color compositions, the second image to be superimposed on the first image; and a display displaying information. If an image formation instruction, including information indicating that the first and second images are to be superimposed is received, with a different image formation instruction being received, the first processor causes the first image former to form the first image in accordance with a first image formation instruction, corresponding to the first color composition, out of the image formation instruction and the different image formation instruction; and transmit to the second processor a second image formation instruction corresponding to the second color composition. The second processor causes the second image former to form the second image in accordance with the second image formation instruction.

Abstract: Apparatus and method for double-precision traversal and intersection.

Abstract: A method of processing rays in a ray tracing system, the method comprising: allocating a block of memory for a task on a per-task basis; processing rays in the task causing at least one child ray to be emitted; writing intermediate data for the task to said block of memory; suspending processing of the task; and when the task is ready to resume, reading intermediate data for the task from the block of memory, and resuming the processing of the task.

Abstract: A display substrate includes: a base, and pixel units arranged in an array, each pixel unit including at least two sub-pixels each including: a pixel driving circuit, and a light-emitting element. The light-emitting element includes: a first electrode, a light-emitting layer, and a second electrode arranged on the base sequentially. Each sub-pixel is configured with a corresponding operating voltage transmission line. The pixel driving circuit includes: a driving transistor with a first pole electrically connected to the operating voltage transmission line. The operating voltage transmission line is located between a layer structure where a control pole of the driving transistor is located and a layer structure where the first electrode is located. The at least two sub-pixels include: at least one first sub-pixel and at least one second sub-pixel. The first and second sub-pixels are configured with first and second operating voltage transmission lines insulated from each other, respectively.

Abstract: An adaptive, large graph-oriented unified memory management method is proposed; according to the order of priorities of different types of graph data structure in a graph computing application, whether the current GPU memory is full is sequentially determined by means of GPU memory checking; whether the size of current graph data exceeds the available memory capacity of the GPU is determined by means of data overflow checking; and then a unified memory management policy is configured; the method uses different graph algorithms based on the characteristics of graph data structure and the size of the available GPU memory; the method can significantly improve the performance of processing large graphs, which exceed the video memory capacity under a unified memory architecture, including improving GPU bandwidth utilization, reducing the number of page faults and the overhead of processing page faults, and speeding up the execution of graph computing programs.

Abstract: A multi-GPU-based image rendering method includes: acquiring a target image, and detecting first rendering durations for different number of available devices to render the target image, where the available devices are GPU devices for image rendering; comparing the first rendering durations corresponding to different number of available devices, and acquiring the available devices corresponding to a minimum one of the first rendering durations as target devices; dividing the target image according to the target devices and a second rendering duration to obtain second images, where the second rendering duration is a duration required for a single target device to render the target image; rendering the second images based on rendering tasks in the target devices to obtain second image results, and combining the second image results to obtain a rendering image of the target image, where the rendering tasks are configured to render the second images.

Abstract: A cloud native 3D scene game and method thereof, including: initiating a game request by one or more users to a cloud server through a game client, creating and starting one corresponding game process according to the game request of the one or more users by the cloud server, and processing the game data of the one or more users at the same time by the game process. The invention has the advantages that: game data of multiple users are processed through one game process, and multiple virtual cameras are controlled to generate corresponding game screens for different users at the same time in one game process which can obviously reduce consumption of server resources and reduce the number of the servers, meanwhile, the fluency of game screens can be guaranteed, the user experience can be improved, and the interaction fluency among different users can be improved.

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

Abstract: The present disclosure relates to a device for driving a motor, including a lower case having an accommodating space formed therein and an open upper side; an upper case closing an open surface of the lower case to form an inner space; a central case disposed in the lower case to partition an inner space formed by the lower case and the upper case; a first board disposed on the lower case and comprising a first connector; a second board disposed on the central case and comprising a second connector; and a connection board disposed in the inner space and comprising a first connection connector electrically connected to the first connector and a second connection connector electrically connected to the second connector to transmit electric signals between the board.

Abstract: Game screen rendering based on multiple graphics cards. Recognizing M physical graphics cards on a physical host, determining a rendering task and segmenting it into at least one rendering part; determining a target physical graphics card according to the at least one rendering part, wherein the target physical graphics card is one or more of the M physical graphics cards; rendering the at least one rendering part through the target physical graphics card; and outputting a rendering result through an output device.

Abstract: The present application provides a bridge supply circuit of a multipath Efuse chip and a server. The supply circuit includes: a first Efuse chip and multiple second Efuse chips, inputs of the first Efuse chip and the multiple second Efuse chips being connected to a power supply, an output of the first Efuse chip being connected to each of the Graphics processing units (GPUs), an output of each of the multiple second Efuse chips being separately connected to each of the GPUs except for a first GPU; damping circuits, each of the damping circuits being separately provided between the output of each of the multiple second Efuse chips and the GPU; and current paths, each of the current paths being separately provided between the output of the first Efuse chip and each of the GPUs except for the first GPU.

Abstract: An encoded data pattern touchscreen sensing computing device includes a touchscreen, a plurality of electrodes, a plurality of drive-sense circuits, and a processing module. When enabled and in close proximity to an encoded data pattern, the plurality of drive-sense circuits detect changes in electrical characteristics of the plurality of electrodes caused by one or more electrical materials of the encoded data pattern. The encoded data pattern includes one or more electrical materials arranged in a pattern. Electrical properties of the one or more electrical materials and the pattern are representative of data. The processing module is operable to receive a set of detected changes in electrical characteristics of the set of drive-sense circuits, interpret the detected changes in electrical characteristics as a set of impedance values representative of the one or more electrical materials of the encoded data pattern, and interpret the set of impedance values to determine the data.

Abstract: Methods and systems for restoring data are described. According to some embodiments, the method, in response to receiving a first restore request, initiates a second restore request to a hybrid data buffer to route blocks of backup data to the hybrid data buffer. The method further invokes an interrupt service routine (ISR) that is initialized with reserved addresses. When the blocks of backup data are transmitted to the hybrid data buffer, the method further tags, by the ISR, the blocks of backup data to a specified location, where the specified location is one of the reserved addresses.

Abstract: System and methods for providing multiple distinct and private video streams, where the streams are temporally and spatially overlapping, and a person uses a visual aid to substantially perceive a single distinct stream from within the multiplicity. A preferred embodiment using two or more projectors comprising a composite of three or more private streams implements the combination of spatial and temporal filtering for steam differentiation. Composite streams from multiple projectors are temporally synchronized, and each composite stream comprises one or more private streams, wherein two or more private streams are temporally interleaved. Each composite stream comprises a succession of spatially composite images. A spatially composite image comprises two or more spatially differentiable private images belonging to different distinct private image streams.

Abstract: An interface software layer is interposed between at least one application and a plurality of coprocessors. A data and command stream issued by the application(s) to an API of an intended one of the coprocessors is intercepted by the layer, which also acquires and stores the execution state information for the intended coprocessor at a coprocessor synchronization boundary. At least a portion of the intercepted data and command stream data is stored in a replay log associated with the intended coprocessor. The replay log associated with the intended coprocessor is then read out, along with the stored execution state information, and is submitted to and serviced by at least one different one of the coprocessors other than the intended coprocessor.

Abstract: Apparatus and method for migrating a container including graphics processor state.

Abstract: A light emitting assembly is described. In one embodiment, one or more light emitting diode (LED) devices and one or more microcontrollers are bonded to a same side of a substrate, with the one or more microcontrollers to switch and drive the one or more LED devices.

Abstract: Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

Abstract: The invention provides, in some aspects, a system for implementing a rule derived basis to display image sets. In various embodiments of the invention, the selection of the images to be displayed, the layout of the images, as well as the rendering parameters and styles can be determined using a rule derived basis. The rules are based on meta data of the examination as well as image content that is being analyzed by neuronal networks. In an embodiment of the present invention, the user is presented with images displayed based on their preferences without having to first manually adjust parameters.

Abstract: Embodiments of the present disclosure relate to techniques for providing a remoted application to a client device over a network. Certain embodiments involve receiving, by a web server and from the client device, a request for the remoted application. The request may comprise a tag which identifies one or more attributes of the remoted application. Embodiments further involve launching, by the web server and based on the tag, the remoted application. Embodiments further involve providing, by the web server and to the client device, a video stream of the remoted application. The video stream of the remoted application may comprise one or more images rendered based on raw data of the remoted application. Embodiments further involve receiving, by the web server and from the client device, user input and providing, by the web server and based on the user input, application input to the remoted application.

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

Abstract: The system and method described herein may upgrade kernels in cloud images deployed in cloud computing environments without having to rebuild a machine image that contains a root file system for the cloud image. For example, the cloud image may include a ramdisk that compares the kernel booted in the cloud image to the root file system to verify whether the machine image contains a directory hierarchy matching an operating system release for the kernel. In response to the machine image containing the matching directory hierarchy, the root file system may be mounted for execution in the cloud computing environment. Alternatively, in response to the machine image lacking the matching directory hierarchy, the ramdisk may dynamically create the matching directory hierarchy and inject modules that support the kernel into the root file system prior to mounting and delivering control to the root file system.

Abstract: A display device includes a display panel and an image processor. The display panel includes pixels, each pixel among the pixels including sub-pixels. The image processor is configured to process image data for image display via the display panel. An arrangement of sub-pixels of a pixel in an odd-numbered pixel column of the display panel is different from an arrangement of sub-pixels of a pixel in an even-numbered pixel column of the display panel. The image processor includes an edge determiner and a sub-pixel renderer. The edge determiner is configured to determine an edge from the image data. The sub-pixel renderer is configured to perform sub-pixel rendering on pixel data about sub-pixels configured to display a same color in adjacent pixels in the odd-numbered pixel column or the even-numbered pixel column located at the edge.

Abstract: Systems, apparatuses, and methods for dynamically coalescing multi-bank memory commands to improve command throughput are disclosed. A system includes a processor coupled to a memory via a memory controller. The memory also includes processing-in-memory (PIM) elements which are able to perform computations within the memory. The processor generates memory requests targeting the memory which are sent to the memory controller. The memory controller stores commands received from the processor in a queue, and the memory controller determines whether opportunities exist for coalescing multiple commands together into a single multi-bank command. After coalescing multiple commands into a single combined multi-bank command, the memory controller conveys, across the memory bus to multiple separate banks, the single multi-bank command and a multi-bank code specifying which banks are targeted. The memory banks process the command in parallel, and the PIM elements process the data next to each respective bank.

Abstract: A dataflow graph has operation units that are configured to be producer operation units to produce tensors for execution of the application, and to be consumer operation units to consume the tensors for execution of the application. Compile time logic is configured to process the dataflow graph to determine, for the tensors, expected producer memory layouts, expected consumer memory layouts, and current memory layouts. The expected producer memory layouts specify memory layouts required by the producer operation units that produce the tensors. The expected consumer memory layouts specify the memory layouts required by the consumer operation units that consume the tensors. The current memory layouts specify the memory layouts of the tensors. Each of the memory layouts includes a vector dimension and at least one of a vector ordering and a data alignment.

Abstract: In some aspects, systems and methods provide for forming groupings of a plurality of independently-specified computation workloads, such as graphics processing workloads, and in a specific example, ray tracing workloads. The workloads include a scheduling key, which is one basis on which the groupings can be formed. Workloads grouped together can all execute from the same source of instructions, on one or more different private data elements. Such workloads can recursively instantiate other workloads that reference the same private data elements. In some examples, the scheduling key can be used to identify a data element to be used by all the workloads of a grouping. Memory conflicts to private data elements are handled through scheduling of non-conflicted workloads or specific instructions and/or deferring conflicted workloads instead of locking memory locations.

Abstract: An embodiment method for converting an initial digital image into a converted digital image, electronic chip, system and computer program product are disclosed, the initial digital image comprising a set of pixels, the pixels being associated respectively with colors, the initial digital image being acquired by an acquisition device, and the converted digital image able to be used by a neural network. The embodiment method comprises redimensioning of the initial digital image in order to obtain an intermediate digital image, the redimensioning being carried out by a reduction in the number of pixels of the initial image, modification of a format of one of the pixels of the intermediate digital image in order to obtain a converted digital image, the modification being carried out, after the redimensioning, by increasing the number of bits used to represent the color of the pixel.

Abstract: A memory system, a memory controller and an operating method are disclosed. When a target command which instructs an operation of writing target data to a memory device is received from a host, the target data is divided into data units, and a first data unit among the data units is controlled such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device. As a consequence, it is possible to write data in specific units in a memory system using a multi-core.

Abstract: Disclosed techniques relate to memory space management for graphics processing. In some embodiments, first and second graphics cores are configured to execute instructions for multiple threadgroups. In some embodiments, the threads groups include a first threadgroup with multiple single-instruction multiple-data (SIMD) groups configured to execute a first shader program and a second threadgroup with multiple SIMD groups configured to execute a second, different shader program. Control circuitry may be configured to provide access to data stored in memory circuitry according to a shader memory space. The shader memory space may be accessible to threadgroups executed by the first graphics shader core, including the first and second threadgroups, but is not accessible to threadgroups executed by the second graphics shader core. Disclosed techniques may reduce latency, increase bandwidth available to the shader, reduce coherency cost, or any combination thereof.

Abstract: Generating signatures within a network that includes a plurality of computing devices of varying processing capabilities is disclosed. Chips may be transmitted, from a network video recorder and over the network, to an analytics appliance having a GPU processing power that is higher than a GPU processing power possessed by the network video recorder. The GPU processing power possessed by the analytics appliance may be employed to process the chips therein and generate respective signatures.

Abstract: A method, a device, an apparatus for identifying a graphics card of a GPU server, and a medium are provided. The method includes: obtaining correlation information of a graphics card captured by an operation of enumerating PCI devices during a startup process of running a BIOS; determining whether the graphics card belongs to a preset category; reading a memory address of the graphics card in a configuration space of the PCI device in a case that the graphics card belongs to the preset category, and obtaining an actual memory address based on the memory address and an offset; and resetting the graphics card based on the actual memory address, and sending a restart instruction to perform a restart operation.

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

Abstract: A storage apparatus includes a storage device that stores a table mapping a logical address to a physical address and a controller that manages the table and controls write of data to and read of data from the storage device according to a request from a host. The controller allocates, in a memory, a cache area for temporarily storing a part of the table, and a write buffer area for storing a part of the table that has been updated by the host and is to be written to the storage device, upon receipt of a request that requires update of the table from the host, determines whether a first part of the table to be updated is in the write buffer area, and upon determining that the first part is in the write buffer area, updates the first part in the write buffer area according to the request.

Abstract: An image processing apparatus in which image processing is executed by each of objects of an object group in which the objects each executing the image processing are connected to one another in a directed acyclic graph form, includes: a division portion that divides image data, which is a target of the image processing, into plural first divided image data pieces when the image processing is processing having sequentiality in processing sequence; and a control portion that makes control to enable computing devices to execute first partial processings in parallel, the first partial processings being pieces of the image processing to be performed on the first divided image data pieces and being allowed to be processed in accordance with dependent relations with front and rear stages and a processing sequence dependent relation.

Abstract: Aspects of the subject disclosure may include, for example, obtaining image content over a communication network, determining a predicted viewpoint of a user associated with the image content, and adjusting the image content to equirectangular image content according to the predicted viewpoint. Further aspects can include downscaling the equirectangular image content according to a display capability of a mobile device resulting in a downscaled equirectangular image content, cropping the downscaled equirectangular image content resulting in a cropped equirectangular image content, and providing, over the communication network, the cropped equirectangular image content to the mobile device. Other embodiments are disclosed.

Abstract: A computer implemented method uses memory coherence to enhance latency and bandwidth performance, the method including receiving, by a host, a call from an application. The method also includes, determining that the call includes a device allocation command, wherein the device allocation command is configured to allocate a set of data on a graphical processing unit. The method further includes intercepting the call. The method includes, initiating an alternate data allocation command; and returning the alternate data allocation command to the application. Further aspects of the present disclosure are directed to systems and computer program products containing functionality consistent with the method described above.

Abstract: Methods, systems, and devices for graphics processer unit (GPU) operations are described. A device may monitor one or more states of a GPU during a duration. Based on monitoring the one or more GPU states, the device may determine an execution of a GPU command that is common to at least two GPU operations for clearing the GPU buffer. The device may determine whether the GPU clear command has previously been executed during a duration or a GPU cycle in which the device monitored the GPU states. The device may process the GPU clear command based on the determination of whether the GPU clear command has previously been executed. For example, the device may drop the GPU clear command based on the determination or modify a portion of the GPU clear command and execute at least the modified portion of the GPU clear command.

Abstract: A method for graphics processing. The method including rendering graphics for an application using a plurality of graphics processing units (GPUs). The method including dividing responsibility for the rendering geometry of the graphics between the plurality of GPUs based on a plurality of screen regions, each GPU having a corresponding division of the responsibility which is known to the plurality of GPUs. The method including generating information regarding a piece of geometry with respect to a first screen region for which a first GPU has a first division of responsibility, while rendering the piece of geometry at a second GPU for an image. The method including rendering the piece of geometry at the first GPU using the information.

Abstract: An apparatus, a system, and a method for allocating power to a graphics processing unit, where the apparatus includes a frame rate detection module configured to detect a frame rate of current image data to-be-displayed, and a power allocation module configured to: determine whether the frame rate is lower than a preset frame rate threshold; if the frame rate is lower than the preset frame rate threshold, determine that displaying of the image data is in a frame freezing state; determine, in response to the frame freezing state, whether a graphics processing unit reaches a power bottleneck state; and if determining that the graphics processing unit reaches the power bottleneck state, increase power of the graphics processing unit and reduce power of another module related to the displaying.

Abstract: Examples disclosed herein may involve (i) obtaining 2D image data and 3D sensor data that is representative of an area, (ii) identifying a first set of pixels associated with ephemeral objects detected in the area and a second set of pixels associated with non-ephemeral objects detected in the area, (iii) identifying a first set of ephemeral 3D data points associated with the detected ephemeral objects and a second set of non-ephemeral 3D data points associated with the detected non-ephemeral objects, (iv) mapping the first and second sets of 3D data points to a grid of voxels associated with the area, (v) making a determination that one or more voxels in the grid each contain a threshold extent of ephemeral data points, and (vi) based at least in part on the determination, filtering the 3D sensor data to remove the 3D data points contained within the one or more voxels.

Abstract: In graphics processing data is received representing one or more vertices for a scene in a virtual space. A projection of the vertices onto a screen space of a display device is performed. A density of the vertices is adjusted for selected portions of the screen space, such that a lower density of vertices is present in selected portions of the screen space. Primitive assembly is performed on the vertices to generate a one or more primitives in screen space from the projection of the vertices onto the screen space. A finished frame is then generated by performing pixel processing to assign pixel values to the pixel or pixels that are part of the corresponding primitives. In some implementations, the finished frame can be stored in the memory or displayed on the display device.

Abstract: Described herein are techniques for removing control of a display from an operating system. The disclosed techniques decouple operation of the physical display device from control of the operating system so that the display device may be powered down while not needed during streaming. The device driver for the graphics card, into which a display device cable is plugged, simulates operation of the display but allows the display to be powered down. Simulating the display involves properly responding to queries or commands from the operating system, and generating the signals that would be expected from the display device by the operating system. While simulated in this manner, whether the display device is actually powered down does not matter to the operation of an application being streamed, because the operating system still “believes” the display device is powered on. Thus application streaming is not interrupted by powering down the display device.

Abstract: A processor and an instruction scheduling method for X-channel interleaved multi-threading, where X is an integer greater than one. The processor includes a decoding unit and a processing unit. The decoding unit is configured to obtain one instruction from each of Z predefined threads in each cyclic period, decode the Z obtained instructions to obtain Z decoding results, and send the Z decoding results to the processing unit, where each cyclic period includes X sending periods, one decoding result is sent to the processing unit in each sending period, a decoding result of the Z decoding results may be repeatedly sent by the decoding unit in a plurality of sending periods, wherein 1?Z<X or Z=X, and wherein Z is an integer. The processing unit (32) is configured to execute the instruction based on the decoding result.

Abstract: A method of transmitting an audio and/or audiovisual content to a receiver. The method starts with receiving a determined stream broadcast on a network and playing back the contents transmitted by the stream in the receiver. Then a first event external to the receiver is detected and triggers interruption of the playback of the content in progress and recording of the instant of the interruption. Sometime later, a second external event triggers a transmission, from the receiver to a remote server, of the instant dating the first event and of a request for resuming the playback of the interrupted content. A piece of information specifying the identifiers of the data packets of the content at the instant of the interruption is then transmitted from the remote server to the receiver. Finally, the receiver receives the identified data packets and replays the content of the packets.

Abstract: Described herein are techniques for generating a stitched shader program. The techniques include identifying a set of shader programs to include in the stitched shader program, wherein the set includes at least one multiversion shader program that includes a first version of instructions and a second version of instructions, wherein the first version of instructions uses a first number of resources that is different than a second number of resources used by the second version of instructions. The techniques also include combining the set of shader programs to form the stitched shader program. The techniques further include determining a number of resources for the stitched shader program. The techniques also include based on the determined number of resources, modifying the instructions corresponding to the multiversion shader program to, when executed, execute either the first version of instructions, or the second version of instructions.

Abstract: In example implementations, an apparatus is provided. The apparatus includes a first interface, an upstream device detector, a second interface, and a processor. The first interface receives a multi-channel connection. The upstream device detector is to detect a connection to external graphical processor unit (eGPU) via the first interface. The second interface is to connect a peripheral device that transmit data over the multi-channel connection via the first interface through the eGPU and to a host computer. The processor disables a portion of the multi-channel connection on the first interface when the upstream device detector detects the connection to the eGPU.

Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.

Abstract: A GPU virtualization method based on a container comprises the steps of: transmitting, if the container is created, a configuration file including GPU resource constraint information and an API profile to the container, by a node controller; and implementing a virtual GPU, when the container is executed, by intercepting a library call and changing an argument related to a GPU resource amount by a library controller provided in the container, and by intercepting a system call and changing argument and return values by a system call controller.

Abstract: A video processing apparatus includes a programmable hardware encoder configured to execute an encoding process on a plurality of input video frames. The video processing apparatus further includes a controller coupled with the programmable hardware encoder. The controller is configured to execute a set of instructions to cause the video processing apparatus to: determine first information of the plurality of input video frames, and adjust the encoding process based on the first information.