Abstract: A boundary macroblock of a video object is padded without significant synchronization overhead between a host processor and an existing coprocessor. The host processor determines horizontal and vertical graphics primitives as a function of shape data stored in a host memory. The shape data determine whether a dot, a line, or a rectangle primitive should be used to pad transparent pixels in the macroblock. The host processor communicates the primitives to a coprocessor, which renders the primitives in an interleaved pipeline fashion to pad transparent pixels of the macroblock based on texture data stored in video memory. The flow of primitives is in one direction from the host processor to the graphics coprocessor, and the texture data is not transferred back and forth between the host processor and coprocessor. This technique is especially useful for enabling acceleration of MPEG-4 video decoding utilizing existing coprocessors capable of accelerating MPEG-1/2 video decoding.

Abstract: An application processor and coprocessor communicate data, including command and control data, over a separate high-speed datapath. The data may be formatted into a pixel-stream format suitable for sending over the datapath. The application processor may utilize a graphics interface to send pixel-stream formatted data to a graphics interface of the coprocessor over the high-speed datapath rather than over a system bus. The coprocessor may reformat the formatted data to control and drive a graphics display.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer.

Abstract: In accordance with a specific implementation of the present invention, the control portion of a graphics processor receives a command having both a data portion and a data duration portion. When the data duration portion indicates the data is transient data for short-term use, the control portion stores the data associated with the data portion at the first memory partition. When the data duration portion indicates the data is persistent data for long-term use, the control portion stores the data associated with the data portion at a second memory partition. In a multiple processor system, transient data may be stored only in a memory partition associated with a first processor, while persistent data may be stored in multiple memory partitions, one for each graphics processor.

Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Abstract: A method and apparatus for executing loop and branch program instructions in a programmable graphics shader. The programmable graphics shader converts a sequence of instructions comprising a portion of a shader program and selects a first set of fragments to be processed. Subsequent sequences of instructions are converted until all of the instructions comprising the shader program have been executed on the first set of fragments. Each remaining set of fragments is processed by the shader program until all of the fragments are processed in the same manner. Furthermore, the instructions can contain one or more loop or branch program instructions that are conditionally executed. Additionally, when instructions within a loop as defined by a loop instruction are being executed a current loop count is pipelined through the programmable graphics shader and used as an index to access graphics memory.

Abstract: A disclosed coprocessor receives a user-defined command during execution of an instruction including the user-defined command, and performs a predetermined function in response to the user-defined command. The user-defined command includes multiple ordered bits having values assigned by a user. In one embodiment, the coprocessor includes logic coupled to receive the user-defined command and a datapath. The logic produces a control value in response to the user-defined command. The datapath receives data and the control value, and performs the predetermined function dependent upon the control value. In one embodiment, the predetermined function is a motion estimation function. Data processing systems are described including a processor coupled to the coprocessor. Another disclosed data processing system includes an arbiter coupled between a processor and multiple coprocessors.

Abstract: A method for processing 2D operations in a tiled graphics architecture is disclosed. A graphics controller processes both 3D primitives and 2D blit operations. The 3D primitives are sorted into bins using well-known techniques. When a 2D blit operation is to be processed, the 2D blit operation is also sorted into bins. The sorted 3D primitives and sorted 2D blit operations are then delivered to blit and rendering engines on a bin-by-bin basis. By sorting the 2D blit operations into bins along with the 3D primitives, there is no need to flush the bins (send primitives to rendering engines) whenever a 2D blit operation requires processing. The sorting of 2D blit operations into bins reduces the frequency of graphics cache misses and improves graphics memory bandwidth utilization, thereby improving overall computer system performance.

Abstract: An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of texture buffer accesses to potentially reduce the number of memory fetches. The unit maintains a queue of pending requests for tiles of data from the memory, and predicts the retrieval of redundant data within short sequences of requests. The redundant data is retrieved from the memory once, and repeated as necessary from local temporary storage registers.

Abstract: A graphics subsystem having a programmable shader controllable by both state-based control information, such as DirectX 8 control information, and program instructions, such as DirectX 9 shader program instructions. The programmable shader translates state-based control information received from a host computer into native control information. The programmable shader translates into native control information program instructions fetched from memory locations identified by a received memory reference and program instructions received from the graphics subsystem. Native control information configures computation units of the programmable shader. The programmable shader optimizes the generated native control information by combining certain operations. The graphics subsystem detects memory references sent from the host computer and pre-fetches program instructions for transmission to the programmable shader.

Abstract: In accordance with a first mode of operation of the present invention, a portrait image is received from a system device. The portrait image is translated and stored within the graphics engine memory such that it can be displayed on a landscape monitor that has been rotated 90 degrees. Likewise, when portrait data stored within the memory is sent to the system it is translated such that it is sent back in the same format received by the system. In a second mode of operation in accordance with the present invention, a landscape image received by the graphics adapter is stored in the graphics adapter memory without any translation.

Abstract: It cannot be ensured that display setting changes are made at once in a system in which the number of display settings for a display processing apparatus is extremely large, an application is running under an operating system and display setting register change time is unpredictable from the application due to another task, or an internal configuration is incapable of immediately reflecting access from a host CPU to a display setting register. According to the present invention, outputs of a plurality of first display setting registers mapped into an address space for temporarily holding display setting data generated and outputted by a host CPU under control of a write control signal are connected to inputs of a plurality of second display setting registers holding display setting parameters referenced by display output module.

Abstract: A highly integrated multimedia processor employs a shared cache between tightly coupled central processing and graphics units to provide the graphics unit access to data retrieved from system memory or data processed by the central processing unit before the data is written-back or written-through to system memory, thus reducing system memory bandwidth requirements. Regions in the shared cache can also be selectively locked down thereby disabling eviction or invalidation of a selected region, to provide the graphics unit with a local scratchpad area for applications such as, but not limited to, temporary video line buffering storage for filter applications and composite buffering for blending texture maps in multi-pass rendering.

Abstract: A graphics system configured to apply multiple layers of texture information to batches of primitives. The graphics system collects primitives into a batch that share a common set of texture layers to be applied. The batch is limited so that the total estimate size of the batch is less than or equal to a storage capacity of a texture accumulation buffer. The graphics system stores samples (or fragments) corresponding to the batch primitives in the texture accumulation buffer between the application of successive texture layers.

Abstract: A vertex data access apparatus and method. The apparatus receives a vertex index, compares the vertex index with any vertices' indices used before, issues a request if necessary for fetching vertex data in system memory, stores the return vertex data in a vertex data queue and gets corresponding vertex data from the vertex data queue for further processing and, more particularly, if the vertex index is the same as one of those vertices' indices, the corresponding vertex data can be directly fetched from the vertex data queue. The vertex data queue performs the vertex cache function.

Abstract: A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles processing non-expedite requests during the monitoring window.

Abstract: Systems and methods are provided for scheduling the processing of a coprocessor whereby applications can submit tasks to a scheduler, and the scheduler can determine how much processing each application is entitled to as well as an order for processing. In connection with this process, tasks that require processing can be stored in physical memory or in virtual memory that is managed by a memory manager. The invention also provides various techniques of determining whether a particular task is ready for processing. A “run list” may be employed to ensure that the coprocessor does not waste time between tasks or after an interruption. The invention also provides techniques for ensuring the security of a computer system, by not allowing applications to modify portions of memory that are integral to maintaining the proper functioning of system operations.

Abstract: A video graphics system employs a method and apparatus for improving throughput of the system. The video graphics system includes a graphics driver, a graphics processor, and a memory. Responsive to receiving a drawing command from an application, the graphics driver determines whether the graphics processor can begin executing the drawing command within a desired period of time. When the graphics processor is heavily loaded and cannot begin executing the command within the desired period of time, the graphics driver partially processes stored vertex information associated with the drawing command, and preferably stores the pre-processed vertex information in the memory. The graphics driver then preferably issues a new drawing command relating to the stored pre-processed information and instructing the graphics processor not to perform any of the processing already performed by the graphics driver. The graphics driver is preferably implemented in software and stored on a computer-readable storage medium.

Abstract: A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.

Abstract: A graphics display system integrated circuit processes analog video input, digital video input, and graphics input. The system incorporates a graphics accelerator that includes memory for graphics data. The accelerator preferably includes a coprocessor for performing vector type operations on a plurality of components of one pixel of the graphics data. The accelerator also includes an expanded instruction set for storing and loading data.

Abstract: In a rendering processing system having a rendering memory for storing rendering pixel data generated by a rendering operation circuit and a display memory for storing the image data of a current frame read out from the rendering memory, the display memory stores only the pixel data read out from the rendering memory with prescribed information excluded therefrom. Thus, it is possible to decrease the storage capacity of the display memory and also reduce the time required for writing data into the display memory.

Abstract: Image processing apparatus (60) for rendering (i.e. coloring, texturing or shading) an image includes a tiling device (66) which divides the image into sub-regions or tiles. Two rendering devices (70A, 70B) are provided, and the tiles are allocated so that some are processed by one rendering device and some by the other. Polygons representing surfaces of objects to be displayed are tested against the tiles. If the surface falls into one sub-region only, the data is sent to one rendering device only. On the other hand, if the surface falls into two sub-regions being handled by the different rendering devices, then the data is sent to both rendering devices. The result is that a substantial proportion of the data need only be supplied to and processed by one rendering device, thereby speeding the operation of the apparatus. The outputs of the two rendering devices (70A, 70B) are subsequently combined by tile interleaving and image display circuitry (72).

Abstract: To increase support a screen having a different aspect ratio or a large screen by use of existing graphics adapters, thus improving performance and flexibility of the whole system. Disclosed is a monitor system comprising a liquid crystal display having a liquid crystal panel which displays an image and has a display area virtually divided into a plurality of divided area, and a plurality of graphics adapters to for developing image data for the divided areas of the liquid crystal display, wherein the divided areas of a screen in the liquid crystal display are obtained by further dividing an area in which the graphics adapters to create images, and a reconstruction circuit for reading out image data developed in the graphics adapters in turn to reconstruct the image data is provided.

Abstract: Apparatus, methods, systems and computer program products are disclosed that optimize the application of deferred image operations on a tiled source image. The invention dynamically creates a data structure (such as a directed acyclic graph (DAG)) representing the operations performed on various instances of one or more images to create a final image. The invention analyzes the data structure to determine which source image tiles are needed when the actual image data comprising the final image is required. Each of these tiles are then separately processed by all of the deferred operations to create the final image data. This approach reduces the number of times a tile is read into memory for processing and improves the performance of deferred image operations on a tiled source image.

Abstract: A display controller for a display apparatus having a memory function which can reduce power consumption efficiently is disclosed. A rewriting comparison circuit detects whether or not rewriting of different data by a graphic engine since the last display updating by a reflect control circuit, and stores resulting information into a TagRAM. The refresh control circuit checks the address of the TagRAM prior to the updating of the display and, only when the data at a corresponding address of a VRAM has been rewritten since the last display updating, the refresh control circuit performs reading in of the data from the VRAM and signaling of the data to the display apparatus having a memory function.

Abstract: In a device and system which perform processing (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.

Abstract: One aspect of the invention is a method for displaying extended range pixel values. The method includes the step of receiving a plurality of image pixel values each with at least one associated data value. The method also includes the steps of sending at least one of the plurality of image pixel values to a first display device (94) having a maximum display value; and sending at least one of the plurality of image pixel values exceeding maximum display value to a second display device (98). In a further embodiment, the at least one associated data value may be at least one of the group consisting of a pixel intensity, a color, and a location of the pixel value.

Abstract: Idle frames received by a graphics controller are compressed by evaluating two idle frames to create an encoding table used to replace selected pixel byte values in subsequent idle frames with codes. Possible pixel byte values are associated with a first set of counters, with each counter counting several different byte values as they occur with the first idle frame. A first subset of the possible pixel byte values is selected based on the counts in the first counters and each byte value in the first subset is associated with a second counter. The occurrences of the first subset of pixel byte values are counted in the second idle frame, and a second subset of pixel byte values is selected based on the counts in the second counters and used to create the encoding table. In one aspect, the encoding table is created when the second set of pixel byte values satisfy a threshold.

Abstract: A microprocessor suitable for processing a large quantity of graphics data. Graphics processing apparatus and method using the microprocessor are also disclosed. The microprocessor independent of a CPU has two ports, and performs an instruction fetch and a data access or a memory access simultaneously to two memories mounted on separate buses. In the graphics processing apparatus in which this microprocessor is employed, the graphics transfer between a system memory and a frame memory can be performed at higher speed.

Abstract: Embodiments of the invention comprise a new device and technique to realize an improved graphics generation system. This improvement is preferably achieved by implementing an interface logic portion to interface with the CPU, a control register portion, a pixel FIFO array portion, a pixel processing logic portion, and a control logic portion. These portions are preferably implemented as an extension of the internal architecture of the CPU. The CPU may be attached to the graphics system via a data cache and a write buffer portion. Data is read from the system memory and placed in the data cache so that subsequent accesses to the same location only require access to the cache. System memory data is written to a write buffer, so that the data written may be queued up and sent to the main memory at an appropriate time. The display refresh controller also reads the data from the system memory and converts the data to a signal for output to a display.

Abstract: A personal computer system includes a core logic unit, a graphics accelerator, a first tile converter, a local memory, a second tile converter and a system memory. The core logic unit outputs first image data in a linear mode. The graphics accelerator is in communication with the core logic unit for processing the first image data into second image data in a linear mode. The first tile converter is in communication with the graphics accelerator for converting the second image data into third image data in a tile mode. The local memory is in communication with the first tile converter for storing therein the third image data. The second tile converter is in communication with the core logic unit for converting the first image data into fourth image data in a tile mode. The system memory is accessible by the core logic unit, and includes a graphics accelerating memory in communication with the second tile converter for storing therein the fourth image data.

Abstract: A video graphics system (300) employs a method and apparatus for efficiently processing vertex information required to render graphics primitives requested for display by an application (313), such as a video game. The video graphics system includes a graphics driver (317), a graphics processor (305), a memory component (309, 321) that is accessible by the graphics processor, and a memory component (319) that is inaccessible by the graphics processor. After receiving, from the application, a drawing command that includes vertex indices and a reference to a vertex buffer (325) stored in the graphics processor-inaccessible memory component, the graphics driver allocates a new temporary vertex buffer (327) in the graphics processor-accessible memory component and copies the contents of the graphics processor-inaccessible vertex buffer into the temporary vertex buffer.

Abstract: An interface for a graphics system includes simple yet powerful constructs that are easy for an application programmer to use and learn. Features include a unique vertex representation allowing the graphics pipeline to retain vertex state information and to mix indexed and direct vertex values and attributes; a projection matrix value set command; a display list call object command; and an embedded frame buffer clear/set command.

Abstract: A data processing method and an apparatus thereof, which process EIA-775 OSD graphic data received from the outside based on IEEE 1394 standards by using a combined software/hardware method. The data processing apparatus using a combined software/hardware method includes a first data processor, in response to an interrupt control signal, for analyzing predetermined data among graphic data received from the outside based on IEEE 1394 standards and processing the same to output control data, a second data processor for outputting an interrupt control signal to process the predetermined data when the graphic data is received from the outside based on IEEE 1394 standards, and for calculating a destination address and the size of graphic data excluding the predetermined data to be output according to the control data, and a graphic processor for mixing video data with the graphic data, of which the destination address and the size are calculated.

Abstract: A method and apparatus for parallel processing of geometric aspects of video graphics data include processing that begins by determining whether an object-element is within a clipped volume. The processing continues by determining whether the object-element is to be clipped when it is within the clipped volume. The processing then continues by performing in parallel, a clipping function and an attribute derivation function upon the object-element when the object-element is to be clipped. The attribute derivation function may include performing a light function, texture map function, etc.

Abstract: A method and system for processing graphics data in a computer system are disclosed. The method and system including providing a general-purpose processor and providing a vector co-processor coupled with the general-purpose processor. The general-purpose processor includes an instruction queue for holding a plurality of instructions. The vector co-processor is for processing at least a portion of the graphics data using a portion of the plurality of instructions. The vector co-processor is capable of performing a plurality of mathematical operations in parallel. The plurality of instructions is provided using software written in a general-purpose programming language.

Abstract: To reduce the hardware of the graphics computer in size and reduce the cost of the hardware, the frame buffer and the main memory are united into one unit to process graphics data in the CPU. The frame buffer is arranged in the main memory, and the graphics computer includes a DMAC used to read pixel data from the frame buffer for display, a display used to receive the pixel data and display it on a display device, such as an LCD, etc., and memories used to store the procedure used by the CPU to draw the pixel data in the said frame buffer. Especially, the said memories are formed so that a single function procedure and 2 multifunction procedure can be selected to suit the drawing object. In addition, the single function procedure includes 2 line drawing procedure that uses data tables and 2 multivalue expansion procedure that uses a pattern table and a mask table. Since the frame buffer and the main memory are united into one unit, the CPU can be used to process graphics data.

Abstract: An entertainment apparatus is configured to enable a program for an older version of the apparatus to be executed. In a normal mode, a main processing unit (MPU) operates as a main CPU, a graphics processor (GP) operates as a graphics processor, and an input/output subprocessor (IOP) operates as a subprocessor for input and output. In a compatible mode in which a program for an older version of the apparatus is executed, the IOP capable of executing the program for the older version of the apparatus operates as a main CPU, and the MPU and GP emulate a graphics processor for the older version of the apparatus.

Abstract: A method and apparatus for improving performance of an AGP device is provided. In one embodiment of the invention, a second-level cache is provided for a TLB, and part of the data or part of the address that is not otherwise used for determining a TLB entry is divided by a prime number to determine which TLB entry to allocate. One embodiment of the invention provides the ability to load multiple cache lines during a single memory access without incurring additional transfer, storage, or management complexities. The full number of bits of each memory access may be used to load cache lines. One embodiment of the invention loads multiple cache lines for translations of consecutive ranges of addresses. Since the translations included in the multiple cache lines cover consecutive ranges of addresses, the relationship between the multiple cache lines loaded for a single memory access is understood, and additional complexity for cache management is avoided.

Abstract: A method, computer program product, and graphics processor for stereoscopically displaying a primitive on a display device adds a row of pixels to the primitive to improve its appearance on the display device. To that end, it first is determined if the primitive is to be stereoscopically displayed on the display device. After it is determined that the primitive is to be stereoscopically displayed, then a row of pixels is added to the primitive. The primitive preferably is a point primitive or a line primitive.

Abstract: A processor has a data cache that is connected to a coprocessor via a bus, in which the coprocessor writes results of operations performed within the coprocessor in the data cache inside the processor. The data cache is equipped with a function to write data in a tag memory or a data memory according to a write request from the bus, and the coprocessor is equipped with an address generation device that is capable of designating an address of the data cache as a write address.

Abstract: A method and apparatus matches one or more clock speeds used in, or used by, a graphics accelerator so as to match graphics processing requirements to the speed of the clock source or sources. Clock speed is adjusted under software control to match current requirements. Power is conserved by reducing clock speeds from unnecessarily high rates to a rate that can satisfy current display mode settings and other graphics processing demands.

Abstract: A graphics system may include a frame buffer and a hardware accelerator. The frame buffer may include a sample buffer and a double-buffered display area. The hardware accelerator may be coupled to the frame buffer, and configured (a) to receive primitives, (b) to generate samples for the primitives based on a dynamically adjustable sample density value, (c) to write the samples into the sample buffer, (d) to read the samples from the sample buffer, (e) to filter the samples to generate pixels, (f) to store the pixels in a back buffer of the double-buffered display area. A host computer may be configured (e.g., by means of stored program instructions) to dynamically update programmable registers of the graphics system to reallocate the sample buffer in the frame buffer in response to user input specifying a change in one or more window size parameters.

Abstract: An apparatus for processing image data to minimize a size of the image data and for communicating the minimized image data and an apparatus and method for receiving the processed image data. The image processing apparatus includes an acceleration processor for accelerating rendering of a graphic signal and processing the graphic image upon a request of a display apparatus, and an encoder for encoding a difference portion between a previous image and the acceleratively processed graphic signal. The image processing apparatus transmits the minimized image signals via a graphic controller which compresses the images while excluding redundant portions of the transmitted image signals. The apparatus for receiving the image signals decodes the compressed image signal and displays the image signal. A plurality of images which are transmitted from a plurality of computers may be simultaneously displayed on a screen of the display apparatus.

Abstract: A method and system for processing graphics data in a computer system are disclosed. The method and system including providing a general-purpose processor and providing a vector co-processor coupled with the general-purpose processor. The general-purpose processor includes an instruction queue for holding a plurality of instructions. The vector co-processor is for processing at least a portion of the graphics data using a portion of the plurality of instructions. The vector co-processor is capable of performing a plurality of mathematical operations in parallel. The plurality of instructions is provided using software written in a general-purpose programming language.

Abstract: Apparatus and methods are provided for allowing two graphics controllers to cooperate on a single screen and for modifying the AGP protocol to provide symmetric capabilities for both AGP targets and AGP masters. According to one embodiment of the present invention, an Accelerated Graphics Port (AGP) master may initiate a data transaction. A graphics controller receives an AGP transaction request from a core logic device. The graphics controller buffers the AGP transaction request in a request queue. Then, the graphics controller initiates a data transaction in response to the AGP transaction request. According to another embodiment of the present invention, an AGP target may issue AGP transaction requests. The integrated graphics controller issues an AGP transaction request to a graphics controller residing on an expansion card.

Abstract: An apparatus for scalable image processing includes a display, multiple graphics functional units and a mode selector. Each of the graphics functional units has a configuration of a predetermined type to control the display. The mode selector determines which combination of graphics functional units controls the display. A method for scalable image processing includes monitoring at least one parameter, determining whether to switch from one graphics functional unit configuration to a new graphics functional unit configuration based upon one or more of the parameters, and switching to the new graphics functional unit configuration.

Abstract: A method and apparatus for motion compensation using a hardware-assisted abstraction layer is provided. A translator is added in the form of a set-up engine to convert graphics commands to a data structure compatible with a 3-D engine. By doing so, the 3-D engine may be used to serve the dual purposes of processing multiple types of graphics information, for example, 3-D graphics and MPEG video. As standards change and the 3-D engine is updated to accommodate new types of graphics information, the set-up engine may be modified to support the updated 3-D engine without requiring changes to drivers controlled by other entities.

Abstract: A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smaller low-level tiles combine to form larger mid-level tiles. Mid-level tiles combine to form high-level tiles. The tile hierarchy may be expanded to include more levels, or collapsed to included fewer levels. A graphics primitive is rasterized by selecting an starting vertex. The low-level tile that includes the starting vertex is then rasterized. The remaining low-level tiles that are included in the same mid-level tile as the starting vertex are then rasterized. Rasterization continues with the mid-level tiles that are included in the same high-level tile as the starting vertex. These mid-level tiles are rasterized by rasterizing their component low-level tiles.

Abstract: A method and apparatus that extends the video graphics bus from the computer unit to a monitor is used within a computer system that includes a computer unit and a monitor. The computer unit includes a central processing unit, system memory, an accelerated graphics port chip set, and a first AGP coupling converter. The first AGP coupling converter is operably coupled to the AGP chip set and receives video graphics data (e.g., vertex data for triangles corresponding to three-dimensional graphics) and converts the transport formatting of the video graphics. Such transport formatting conversion may include changing from a parallel transport to a serial transport or from a parallel transport to a reduced parallel transport. The monitor includes a second AGP coupling converter, a video graphics controller, and a display device. The second AGP coupling converter is operably coupled, via a cable, to the first AGP coupling converter.