Parallel Processors (e.g., Identical Processors) Patents (Class 345/505)
  • Patent number: 11321816
    Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: May 3, 2022
    Assignee: NVIDIA CORPORATION
    Inventors: Thomas Albert Petersen, Ankan Banerjee, Shishir Goyal, Sau Yan Keith Li, Lars Nordskog, Rouslan Dimitrov
  • Patent number: 11303942
    Abstract: A video processor card for outputting video data, the video processor card being arranged for insertion into a video media server and into communication with an output of the video media server, the card comprising: an input for receiving a first video data stream at a first video resolution from the output of the video media server; a processor arranged to demultiplex the received first video data stream at the first resolution into a plurality of second video data streams, each second video data stream being at a second video resolution; and a plurality of video outputs, each video output arranged to output one of the plurality of second video data streams, wherein the first video resolution is at a higher video resolution than the second video resolution.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: April 12, 2022
    Assignee: DISGUISE TECHNOLOGIES LIMITED
    Inventor: Ashraf Nehru
  • Patent number: 11294850
    Abstract: In one embodiment, a system on chip includes: a plurality of intellectual property (IP) agents formed on a semiconductor die; a mesh interconnect formed on the semiconductor die to couple the plurality of IP agents, and a plurality of mesh stops each to couple one or more of the plurality of IP agents to the mesh interconnect. The mesh interconnect may be formed of a plurality of rows each having one of a plurality of horizontal interconnects and a plurality of columns each having one of a plurality of vertical interconnects;, where at least one of the plurality of rows includes an asymmetrical number of mesh stops. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Brinda Ganesh, Yen-Cheng Liu, Swadesh Choudhary, Tejpal Singh, Pradeep Prabhakaran, Monam Agarwal
  • Patent number: 11288783
    Abstract: A method for image processing, which comprises the following steps: Generating a first histogram from a first image; Calculating a first parameter profile from the first image indicative of the quality of the first image; Adjusting the first parameter profile to generate a second parameter profile; Using the second parameter profile to generate a statistical distribution via a statistical distribution generator, wherein the statistical distribution is characterized by at least three parameters; Using the statistical distribution to perform a histogram specification to the first histogram of the first image to generate a second histogram; Generating a second image based on the first image and the second histogram.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: March 29, 2022
    Assignee: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Guoyin Wang, Tong Zhao, Bin Xiao
  • Patent number: 11277457
    Abstract: The present disclosure relates to an image processing method, a server, a client and an image processing system. The image processing method is applicable to the server and includes: receiving an image processing request from the client, wherein the image processing request includes a to-be-processed image in a first image format; acquiring the to-be-processed image according to the image processing request, and processing the to-be-processed image to obtain a target image in a second image format; and generating a feedback message according to the target image, and sending the feedback message to the client.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: March 15, 2022
    Assignee: BOE Technology Group Co., LTD
    Inventor: Xinquan Yan
  • Patent number: 11263718
    Abstract: A method for graphics processing. The method including rendering graphics for an application using a plurality of graphics processing units (GPUs). The method including dividing responsibility for the rendering of geometry of the graphics between the plurality of GPUs based on a plurality of screen regions that are interleaved, each GPU having a corresponding division of the responsibility which is known to the plurality of GPUs. The method including assigning a GPU a piece of geometry of an image frame generated by an application for geometry pretesting. The method including performing geometry pretesting at the GPU to generate information regarding the piece of geometry and its relation to each of the plurality of screen regions. The method including using the information at each of the plurality of GPUs when rendering the image frame.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: March 1, 2022
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Mark E. Cerny, Florian Strauss, Tobias Berghoff
  • Patent number: 11263142
    Abstract: Various embodiments described herein provide for a memory device that can service a high priority read request during data input without losing the data inputted to the memory device prior to the high priority read request, without re-requesting data from a host, and while leaving one or more internal resources of a memory sub-system available for use by an error correction function of the memory sub-system.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Ryan G. Fisher
  • Patent number: 11257178
    Abstract: A computer including a subdividing section subdividing image data into plural subdivided image data, a control section that causes each of plural cores included a first processing unit to execute in parallel tasks on the subdivided image data, the tasks enabled for processing according to their precedence dependency relationship, a registration section that, if a task is executable by a second processing unit asynchronously with respect to the first processing unit, register a finish detection task to detect completion of the task on the second processing unit in a list after causing a core of the first processing unit to execute an execution instruction task instructing execution of the task on the second processing unit, and a determination section that accesses the list and to determine whether or not there is a completed finish detection task.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 22, 2022
    Assignees: FUJIFILM Corporation, FUJIFILM Business Innovation Corp.
    Inventors: Kazuyuki Itagaki, Takashi Nagao
  • Patent number: 11245816
    Abstract: The present technology relates to an image processing apparatus, an image processing method, and a surgical system, by which a captured image can be displayed with low latency in almost real time. A DMA controller 51 of a CPU 31 divides image data, which is input via an IF card 34, by the number of GPU cards 35-1, 35-2 in a horizontal direction and allocates them. In each of the GPU cards 35-1, 35-2, the image data is subjected to time division processing in the vertical direction. With this, the use of the plurality of GPU cards 35-1, 35-2 increases the speed of processing associated with display for the image data. High-speed display is realized due to reduction in latency. The present technology is applicable to an endoscopic camera, a surgical microscope, and the like.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: February 8, 2022
    Assignee: SONY CORPORATION
    Inventors: Masahito Yamane, Tsuneo Hayashi
  • Patent number: 11244482
    Abstract: An image drawing device includes a first processor that generates second drawing data and second drawing command groups from first drawing data and first drawing command groups and a second processor. The first processor includes a drawing command reorder unit that generates third drawing command groups by changing an arrangement order of the first drawing command groups and deleting first drawing commands that have become unnecessary to execute due to the changing of the arrangement order of the first drawing command groups, a drawing command combination unit that generates the second drawing command groups by combining pieces of first drawing data corresponding to third drawing commands that can be executed by the second processor in the same drawing condition and deleting unnecessary third drawing commands, and a drawing command execution unit that executes each of the second drawing commands in an arrangement order of the second drawing commands.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: February 8, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Satoshi Sakurai
  • Patent number: 11237827
    Abstract: A graphics processing unit (GPU) sequences provision of operands to a set of operand registers, thereby allowing the GPU to share at least one of the operand registers between processing. The GPU includes a plurality of arithmetic logic units (ALUs) with at least one of the ALUs configured to perform double precision operations. The GPU further includes a set of operand registers configured to store single precision operands. For a plurality of executing threads that request double precision operations, the GPU stores the corresponding operands at the operand registers. Over a plurality of execution cycles, the GPU sequences transfer of operands from the set of operand registers to a designated double precision operand register. During each execution cycle, the double-precision ALU executes a double precision operation using the operand stored at the double precision operand register.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: February 1, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Bin He, Jiasheng Chen, Jian Huang
  • Patent number: 11238819
    Abstract: The present application discloses display apparatus for displaying image based on time-divisional data. The display apparatus includes a data processor including at least a first shift register and a data buffer, and configured to store a first matrix of data corresponding to the frame of image data to the data buffer at time t0, to shift the first matrix of data by m columns by the first shift register to obtain a second matrix of data stored to the data buffer at time t1. The display apparatus further includes an interface connector configured to output the first matrix of data in period T0 and the second matrix of data in period T1 in a same order same as the fixed sequential order respectively over the at least two time-divisional periods T0 and T1 of a unit-time through a driver circuit to a display panel for displaying one frame of image.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 1, 2022
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE Technology Group Co., Ltd.
    Inventors: Bingxin Liu, Jian Sun, Ziqiang Guo, Lin Lin, Yadong Ding, Binhua Sun, Jiyang Shao, Feng Zi, Yakun Wang, Ke Li
  • Patent number: 11222393
    Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: partition pixel values in a unit of row of an input image into a plurality of sections and allocates threads to the respective sections of the row, the threads being enabled to run in parallel by a processor; calculate, with each of the threads allocated in each row, distances each from a pixel having a certain value in the corresponding section of the row in the input image, and generates a first distance image which stores values indicating the distances; and calculate, with each of the threads allocated in each row, a first boundary value indicating a distance from a pixel having the certain value in another section of each row, by using a calculation result of the first boundary value in the another section of each row.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: January 11, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Tomonori Kubota, Yasuyuki Murata
  • Patent number: 11151474
    Abstract: Disclosed herein are an apparatus and method for adaptively accelerating a BLAS operation based on a GPU. The apparatus for adaptively accelerating a BLAS operation based on a GPU includes a BLAS operation acceleration unit for setting optimal OpenCL parameters using machine-learning data attribute information and OpenCL device information and for creating a kernel in a binary format by compiling kernel source code; an OpenCL execution unit for creating an OpenCL buffer for a BLAS operation using information about an OpenCL execution environment and the optimal OpenCL parameters and for accelerating machine learning in an embedded system in such a way that a GPU that is capable of accessing the created OpenCL buffer performs the BLAS operation using the kernel, and an accelerator application unit for returning the result of the BLAS operation to a machine-learning algorithm.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: October 19, 2021
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Seung-Tae Hong, Young-Joo Kim, Jeong-Si Kim, Jin-Ho Seol
  • Patent number: 11119802
    Abstract: A method for processing data includes receiving a write request by a host operating system during a predetermined time window, storing data associated with the write request in a shared memory, making a first determination that a threshold number of write requests are obtained within the predetermined time window, and, in response to the first determination, sending an offload request to a virtual machine (VM), wherein the offload request specifies at least the write request.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 14, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Jonathan I. Krasner, Sweetesh Singh, Steven R. Chalmer
  • Patent number: 11102436
    Abstract: Provided is a solid-state imaging device that includes a pixel array portion in which a plurality of pixels are arranged in a two-dimensional array, an AD conversion unit configured to perform AD conversion with respect to a pixel signal output from the pixel of the pixel array portion, a memory configured to retain a digital pixel signal after the AD conversion, and an image signal processing circuit configured to perform predetermined signal processing with respect to the digital pixel signal. The image signal processing circuit includes two or more PUs including one or more PEs configured to execute predetermined arithmetic processing, and a CU configured to operate the PE in an SIMD format, an IMEM configured to store one or more arithmetic processing instructions, and a CCU configured to control the PU.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: August 24, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Sayaka Shida
  • Patent number: 11099997
    Abstract: In a data prefetching method, a storage device obtains a first sequence stream length and a first access count of a target logical block after execution of a first data access request is completed. When a second data access request is received, the storage device modifies the first sequence stream length to a second sequence stream length and modifies the first access count to a second access count. The storage device further calculates a sequence degree of the target logical block based on the second sequence stream length and the second access count, and performs a data prefetching operation when the sequence degree of the target logical block exceeds a first prefetch threshold.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: August 24, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Chunhua Tan, Weiqiang Jia, Ding Li, Wenqiang Yang, Liyu Wang, Pengli Ji
  • Patent number: 11094038
    Abstract: An electronic device may include an electronic display to display an image based on scaled image data and variable scaling circuitry to generate the scaled image data. Generating the scaled image data may include receiving input pixel values in a first resolution and determining multiple tap point locations based on a scaling ratio to be applied to the input pixel values. Generating the scaled image data may also include determining weighting coefficients based on a scaling curve and the tap point locations, and weighting the input pixel values based on the weighting coefficients. The variable scaling circuitry may generate the scaled image data at a second resolution based on the aggregation of the weighted input pixel values.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: August 17, 2021
    Assignee: Apple Inc.
    Inventor: Alexey Kornienko
  • Patent number: 11095834
    Abstract: A living organism image monitoring system is provided, relating to the technical field of medical equipment. The living organism image monitoring system comprises a display module, a processor and a CIGS chip, the CIGS chip, the processor and the display module being electrically connected, the CIGS chip being used for detecting a near infrared light signal of a living organism and generating a current signal after having detected the near infrared light signal, the processor being used for generating a first pulse signal according to the current signal, and the display module being used for displaying an image according to the first pulse signal. The living organism image monitoring system provided by the present disclosure has the advantages of being capable of synchronously transmitting the images of a living organism to the display module for display and enabling the images to be clearer.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: August 17, 2021
    Assignee: PIONEER MATERIALS INC. CHENGDU
    Inventors: Chien-Chun Liu, Liu-Yuh Lin, Liang-Chih Weng, Tzu-Huan Cheng, Chen-Hsin Wu, Hao-Che Liu, Chien-Yao Huang, Leon A Chiu, Sau-Mou Wu, Ti-Hsien Tai, Yu-Hsiang Pan
  • Patent number: 11080814
    Abstract: A method including rendering graphics for an application using graphics processing units (GPUs). Responsibility for rendering of geometry is divided between GPUs based on screen regions, each GPU having a corresponding division of the responsibility which is known. First pieces of geometry are rendered at the GPUs during a rendering phase of a previous image frame. Statistics are generated for the rendering of the previous image frame. Second pieces of geometry of a current image frame are assigned based on the statistics to the GPUs for geometry testing. Geometry testing at a current image frame on the second pieces of geometry is performed to generate information regarding each piece of geometry and its relation to each screen region, the geometry testing performed at each of the GPUs based on the assigning. The information generated for the second pieces of geometry is used when rendering the geometry at the GPUs.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: August 3, 2021
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Mark E. Cerny, Florian Strauss, Tobias Berghoff
  • Patent number: 11074305
    Abstract: A technology is described for extending a data store operation using a function object. An example method may include receiving a request that includes request attributes to execute a data store operation. The request may be received at a data store system via a virtual computer network in a service provider environment. After receiving the request to execute the data store operation, the request may be analyzed to identify a request attribute associated with a function object that extends the functionality of the data store operation. The function object associated with the request attribute may be identified and the function object may be executed in association with executing the data store operation.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 27, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Michael Joseph Ruiz, David Ricardo Rocamora
  • Patent number: 11069022
    Abstract: An apparatus and method for multi-adapter and/or multi-pass encoding on dual graphics processors. For example, one embodiment of a processor comprises: a central processor integrated on a first die, the central processor comprising a plurality of cores to execute instructions and process data; an first graphics processor integrated on the first die, the first graphics processor comprising media processing circuitry to perform one or more preliminary lookahead operations on video content to generate lookahead statistics; an interconnect to couple the first graphics processor to a lookahead buffer, the first graphics processor to transmit the lookahead statistics over the interconnect to the lookahead buffer; wherein the lookahead statistics are to be used by a second graphics processor to encode the video content to generate encoded video.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Changliang Wang, Penne Lee, Dmitry Ermilov
  • Patent number: 11049211
    Abstract: Systems and method for triple buffering of a graphics display without use of interrupts using at least two command buffers that are capable of operating asynchronously. A first command buffer generally contains commands, which, when executed, write frame data to a plurality of frame buffers in round-robin fashion. A second command buffer, which is executed asynchronously to the first command buffer, contains commands to handle waiting for frames to be completed, handle display timing (e.g., display synchronization interval, such vertical sync or vertical blanking intervals), and to cause the display controller to display the correct frames.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: June 29, 2021
    Assignee: CHANNEL ONE HOLDINGS INC.
    Inventor: Aidan Fabius
  • Patent number: 10997929
    Abstract: A display scene processing method and a display scene processing device and a storage medium thereof are disclosed. The display scene processing method includes the following steps: obtaining a vertical synchronization signal; executing a rendering thread to render a first half-screen scene data and a second half-screen scene data based on the vertical synchronization signal; executing an asynchronous time warping thread to correct the rendered first half-screen scene data and the rendered second half-screen scene data to obtain first half-screen scene correction data and second half-screen scene correction data.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: May 4, 2021
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qingwen Fan, Yukun Sun, Jinghua Miao, Wenyu Li, Xuefeng Wang, Bin Zhao, Jianwen Suo, Jinbao Peng, Xi Li, Zhifu Li, Lili Chen, Hao Zhang
  • Patent number: 10997087
    Abstract: A system includes a direct memory access controller and a memory coupled to the direct memory access controller. The memory stores a linked list of records. Each record contains a first field determining the number of fields of a next record. For example, each record can be representative of parameters of execution of a data transfer by the direct memory access controller.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 4, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventor: Fran├žois Cloute
  • Patent number: 10991151
    Abstract: A game rendering method and a terminal are provided. The method includes the following. A rendering instruction is stored when a JS engine of the terminal receives the rendering instruction, where the rendering instruction carries a plurality of data identifiers of to-be-rendered data, a plurality of time interval identifiers corresponding to the data identifiers, and a plurality of rendering parameter identifiers corresponding to the time interval identifiers. The rendering instruction is sent to a target rendering system. A target time interval identifier corresponding to current time is determined, and a target data identifier and a target rendering parameter identifier corresponding to the target time interval identifier are determined. To-be-rendered data corresponding to the target data identifier and target rendering parameter corresponding to the target rendering parameter identifier, are determined.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 27, 2021
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Senlin Li
  • Patent number: 10979517
    Abstract: Some embodiments provide a non-transitory machine-readable medium that stores a program. The program receives a request to geo-enrich data comprising a set of location data. The program further accesses shape data comprising a plurality of shapes associated with a plurality of geographical regions. The program also associates, for each location data in the set of location data, a shape in the plurality of shape with the location data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 13, 2021
    Assignee: SAP SE
    Inventors: Christopher Bolognese, Jonathan Tiu, Xing Jin, Sae-Won Om, Lyndon Hiew
  • Patent number: 10970911
    Abstract: Embodiments disclosed herein relate to a graphics processing chip for rendering computer graphics. The graphics processing chip may include a controller configured to manage operations of the graphics processing chip in accordance with a graphics-rendering pipeline. The operations may include geometry-processing operations, rasterization operations, and shading operations. The chip may further include programmable memory components configured to store a machine-learning model configured to perform at least a portion of the shading operations. The chip may also include a plurality of processing units configured to be selectively used to perform the shading operations in accordance with the machine-learning model. The chip may also include at least one output memory configured to store image data generated using the shading operations.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: April 6, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Christoph Herman Schied, Anton S. Kaplanyan
  • Patent number: 10956212
    Abstract: A scheduler is provided for tall algorithms that include control flow statements that are dependent on tall computations. Thunks may be defined for the tall algorithms and the boundaries or limits of the thunks may be determined by places where tall variables are required to be gathered. The scheduler executes the tall algorithms by calling individually the thunks from the tall algorithms and pausing when a gather operation is required. The scheduler collectively gathers the tall variables from different tall algorithms by using an optimizer to combine I/O operations for the tall algorithms. The scheduler may put back the gathered variables into the context of each tall algorithm, and the scheduler may resume with the next thunk for each tall algorithm. This process may be repeated until all tall algorithms are finished.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 23, 2021
    Assignee: The MathWorks, Inc.
    Inventors: Lucio Andrade-Cetto, Thomas Lane, Richard Amos
  • Patent number: 10956793
    Abstract: Systems, methods, devices, media, and computer readable instructions are described for local image tagging in a resource constrained environment. One embodiment involves processing image data using a deep convolutional neural network (DCNN) comprising at least a first subgraph and a second subgraph, the first subgraph comprising at least a first layer and a second layer, processing, the image data using at least the first layer of the first subgraph to generate first intermediate output data; processing, by the mobile device, the first intermediate output data using at least the second layer of the first subgraph to generate first subgraph output data, and in response to a determination that each layer reliant on the first intermediate data have completed processing, deleting the first intermediate data from the mobile device. Additional embodiments involve convolving entire pixel resolutions of the image data against kernels in different layers if the DCNN.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 23, 2021
    Assignee: Snap Inc.
    Inventors: Xiaoyu Wang, Ning Xu, Ning Zhang, Vitor R. Carvalho, Jia Li
  • Patent number: 10949177
    Abstract: A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes a general purpose CPU executing commands in a CPU programming language and a graphic processing unit (GPU) executing commands in a GPU programming language. A command processor is coupled to the CPU and CPU. The command processor sequences jobs from a program for processing by the CPU or the GPU. The command processor creates commands from the jobs in a state free command format. The command processor generates a sequence of commands for execution by either the CPU or the GPU in the command format. A compiler running a meta language converts program data for the commands into a first format readable by the CPU programming language and a second format readable by the GPU programming language.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 16, 2021
    Assignee: Oxide Interactive, LLC
    Inventor: Daniel K. Baker
  • Patent number: 10949944
    Abstract: Systems, computer readable media, and methods for a unified programming interface and language are disclosed. In one embodiment, the unified programming interface and language assists program developers write multi-threaded programs that can perform both graphics and data-parallel compute processing on GPUs. The same GPU programming language model can be used to describe both graphics shaders and compute kernels, and the same data structures and resources may be used for both graphics and compute operations. Developers can use multithreading efficiently to create and submit command buffers in parallel.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: March 16, 2021
    Assignee: Apple Inc.
    Inventors: Richard W. Schreyer, Kenneth C. Dyke, Alexander K. Kan
  • Patent number: 10937119
    Abstract: An apparatus and method for virtualized scheduling. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising a plurality of graphics processing engines, each of the graphics processing engines usable to execute graphics program code for a plurality of graphics contexts, each of the graphics contexts associated with a particular user mode driver (UMD); and a scheduler to schedule the graphics program code for execution on the plurality of graphics engines, the scheduler comprising an integrated context queue to store program code from all of the graphics contexts, the scheduler to select graphics processing engines to execute the program code from each context based on a detected load and/or availability of each graphics processing engine and to determine an order for executing the program code from each context based on relative priorities associated with the different contexts.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Murali Ramadoss, Penne Lee, Ankur Shah, Ping Liu, Joseph Koston
  • Patent number: 10922585
    Abstract: Labeled data is deterministically generated for training or validating machine learning models for image analysis. Approaches are described that allow this training data to be generated, for example, in real-time, and in response to the conditions at the location where images are generated by image sensors.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: February 16, 2021
    Assignee: Recogni Inc.
    Inventors: Shabarivas Abhiram, Eugene M. Feinberg
  • Patent number: 10891303
    Abstract: Disclosed are systems and methods for editing aggregated data based on edit requests that are received. An edit file is updated to include a newly-received edit. The edit file includes anchor points that each point to one of a plurality of aggregate data objects. The anchor points are used to determine one of the objects to which the edit file corresponds. The edit file is then applied to update data in this object including making the new edit.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: January 12, 2021
    Assignee: VERIZON MEDIA INC.
    Inventors: Brian Hein, Peter Monaco, Richard Sarvate, Nitish Dalal
  • Patent number: 10831541
    Abstract: Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yang Liu, Yong Lu, Peng Ou, Hong Bo Peng
  • Patent number: 10831433
    Abstract: A method and apparatus that incorporate teachings of the present disclosure may include, for example, receiving at a mobile communication device a video stream from a computing device. The video stream is associated with images generated by a software application and is transmitted by the computing device responsive to a request to redirect control of the software application to the mobile communication device. The method may also include presenting the streamed video at the mobile communication device and transmitting to the computing device a stimulation of a remote user input function associated with the mobile communication device, where the transmitted stimulation corresponds to at least one action of a plurality of associable actions that can be executed by the software application. Additional embodiments are disclosed.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 10, 2020
    Assignee: STEELSERIES ApS
    Inventors: Bruce Hawver, Jacob Wolff-Petersen
  • Patent number: 10825128
    Abstract: A data processing system comprises processing circuitry arranged to generate data to form an output array of data, processing circuitry arranged to store the generated data in an output buffer 15 by writing compressed blocks of data representing particular regions of the output array of data to the output buffer, processing circuitry 14 arranged to read a compressed block of data representing a particular region of the array of data from the output buffer, processing circuitry 16 arranged to acquire meta-data from the compressed block of data, and processing circuitry 21 arranged to process the block of data. The acquired meta-data is used to affect the processing of the block of data.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 3, 2020
    Assignee: Arm Limited
    Inventors: Daren Croxford, Ben James, Sean Ellis, Edward Charles Plowman
  • Patent number: 10796472
    Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.
    Type: Grant
    Filed: June 30, 2018
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Michael Apodaca, Ankur Shah, Ben Ashbaugh, Brandon Fliflet, Hema Nalluri, Pattabhiraman K, Peter Doyle, Joseph Koston, James Valerio, Murali Ramadoss, Altug Koker, Aditya Navale, Prasoonkumar Surti, Balaji Vembu
  • Patent number: 10783695
    Abstract: In one embodiment, a computing system may determine a pixel area in a two-dimensional coordinate system associated with a display. The system may project the pixel area into a three-dimensional coordinate system to determine a projected area in the three-dimensional coordinate system. Based on the projected area, the system may access a portion of an analytical definition of a glyph, the portion of the analytical definition defining one or more areas of the glyph. The system may compute a coverage proportion of the pixel area that overlaps with the one or more areas of the glyph. The system may then determine a color for the pixel area based on the coverage proportion.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 22, 2020
    Assignee: Facebook Technologies, LLC
    Inventor: Warren Andrew Hunt
  • Patent number: 10768896
    Abstract: An apparatus and method for performing a reciprocal. For example one embodiment of a processor comprises: a decoder to decode a reciprocal instruction to generate a decoded reciprocal instruction; a source register to store at least one packed input data element; a destination register to store a result data element; and reciprocal execution circuitry to execute the decoded reciprocal instruction, the reciprocal execution circuitry to use a first portion of the packed input data element as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, the reciprocal execution circuitry to generate a reciprocal of the packed input data element using a combination of the coefficients and a second portion of the packed input data element.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Cristina Anderson, Elmoustapha Ould-Ahmed-Vall, Marius Cornea-Hasegan, Robert Valentine, Mark Charney, Jesus Corbal, Venkateswara Madduri
  • Patent number: 10740950
    Abstract: A geometry processing phase of tile-based rendering includes a plurality of parallel geometry pipelines, a plurality of tiling pipelines and a geometry to tiling arbiter situated between the plurality of geometry pipelines and the plurality of tiling pipelines. Each geometry pipeline is configured to: generate one or more geometry blocks for each geometry group of a subset of ordered geometry groups; generate a corresponding primitive position block for each geometry block, and compress each geometry blocks to generate a corresponding compressed geometry block. The tiling pipelines are configured to generate, from the primitive position blocks, a list for each tile indicating primitives that fall within the bounds of that tile. The geometry to tiling arbiter is configured to forward the primitive position blocks generated by the plurality of geometry pipelines to the plurality of tiling pipelines in the correct order based on the order of the geometry groups.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: August 11, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Tim Rollingson, Jairaj Dave
  • Patent number: 10732855
    Abstract: A storage system includes a storage device including a controller and a nonvolatile memory unit, and a host including a processor configured to determine whether or not the host is going to access the storage device within a predetermined range of time, and cause the storage device to be powered off when it is determined that the host is not going to access the storage device within the predetermined range of time.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Daisuke Hashimoto
  • Patent number: 10699464
    Abstract: Methods for enabling graphics features in processors are described herein. Methods are provided to enable trinary built-in functions in the shader, allow separation of the graphics processor's address space from the requirement that all textures must be physically backed, enable use of a sparse buffer allocated in virtual memory, allow a reference value used for stencil test to be generated and exported from a fragment shader, provide support for use specific operations in the stencil buffers, allow capture of multiple transform feedback streams, allow any combination of streams for rasterization, allow a same set of primitives to be used with multiple transform feedback streams as with a single stream, allow rendering to be directed to layered framebuffer attachments with only a vertex and fragment shader present, and allow geometry to be directed to one of an array of several independent viewport rectangles without a geometry shader.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: June 30, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Graham Sellers, Eric Zolnowski, Pierre Boudier, Juraj Obert
  • Patent number: 10691616
    Abstract: A method is provided for use in a distributed storage system having a write cache, the method comprising: receiving, by a first node in the distributed storage system, a first Remote Procedure Call (RPC) command to perform a partial update to a buffer that is stored in a memory of the first node, the partial update including replacing old data that is present in the buffer with new data that is stored in the write cache; transmitting, from the first node to a second node, a second RPC command instructing the second node to provide the new data to the first node by executing a Remote Direct Memory Access (RDMA) write operation into the memory of the first node; and performing the partial update based on the new data when the RDMA. write operation is completed and the new data is received by the first node as a result.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: June 23, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Lior Kamran
  • Patent number: 10679318
    Abstract: A graphics processing method is provided, adapted to a graphic processing unit, the steps including: receiving, via a CSP, a first command associated with all render targets from a display driver; determining, via the display driver, sizes and areas of a plurality of tiles in each frame; repeatedly controlling, via a scissor pool unit, a graphics processing unit to perform drawing processing for each tile according to the first command; comparing, via a signature comparing unit of a cache memory, a signature of a current tile of a current frame and a signature of a tile corresponding to the same position of a previous frame and generating a comparison result; and determining whether to flush the dirty data of the current tile stored in the cache memory from the cache memory to a memory access unit according to the comparison result.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: June 9, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Fengxia Wu, Deming Gu, Heng Que, Yi Zhou, Ying Wang
  • Patent number: 10628908
    Abstract: Methods, systems, and computer-readable media for application-specific virtualized graphics processing are disclosed. A virtual compute instance is provisioned from a provider network. The provider network comprises a plurality of computing devices configured to implement a plurality of virtual compute instances with multi-tenancy. A virtual GPU is attached to the virtual compute instance. The virtual GPU is selected based at least in part on requirements of an application. The virtual GPU is implemented using a physical GPU, and the physical GPU is accessible to the virtual compute instance over a network. The application is executed using the virtual GPU on the virtual compute instance.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 21, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Nicholas Patrick Wilt, Ashutosh Tambe, Nathan Lee Burns
  • Patent number: 10621109
    Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline to bypass a memory access for the first virtual page based on the first page table entry, wherein the graphics pipeline is to read a field in the first page table entry to determine a value of the clear color.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Abhishek R. Appu, Kiran C. Veernapu
  • Patent number: 10614772
    Abstract: A display method and a terminal device are provided, so as to resolve a prior-art problem that CPU power consumption of the terminal device is relatively high because a display system of the terminal device processes three procedures in parallel in a Vsync period. The method is: determining, by the display system of the terminal device, a start moment of a first procedure in an (M+1)th Vsync period according to first processing duration of the first procedure in an Mth Vsync period, so that the display system starts to execute a device display procedure before starting to execute the first procedure, the display system delays executing the first procedure in the (M+1)th Vsync period, so that a time required for processing three procedures in parallel in the (M+1)th Vsync period by the display system is reduced, and CPU power consumption of the terminal device is reduced.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: April 7, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jing Zhao, Bo Yu
  • Patent number: 10613806
    Abstract: A control device includes: a receiving unit that receives a request for processing; a determination unit that determines a processing apparatus to be moved from among a plurality of processing apparatuses based on a predetermined standard in a case where the receiving unit receives a request for processing; and a control unit that controls movement of the processing apparatus based on a result of determination performed by the determination unit.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: April 7, 2020
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Naoya Ogata, Hajime Kajiyama, Hideki Fujimoto, Kunitoshi Yamamoto, Akira Ichikawa, Mariko Miyazaki, Tetsuya Kobayashi