Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.

Abstract: Display filters, including color filters, can be enabled in collaborative environments. When a user of an end user device desires to have a color filter applied, a windowing system or other source of graphics data can render a frame via a graphics driver. Once the frame is rendered, the graphics driver can enable a collaboration tool to capture the frame and share it via a collaboration solution. Separately from the rendering of the frame, the windowing system can leverage a color filter module to directly apply a color filter to the frame. Once the color filter is applied, the windowing system can cause the frame to be displayed locally. Because the graphics driver is not used to apply the color filter, the color filter will not be applied to any frame that the collaboration tool captures and shares.

Abstract: A method to process tiles of a screen space includes determining a tile-processing order for tiles of a first batch of primitives based on a tile-processing order for a second batch of primitives in which the second batch of primitives are processed prior to the first batch of primitives. The tiles of the first batch of primitives are processed based on the tile-processing order determined for the tiles of the first batch of primitives. The tile-processing order is updated as tiles of the first batch of primitives are pushed to a backend processing portion of a graphics processing unit. In one embodiment, determining the tile-processing order for the tiles of the first batch of primitives include arranging the tiles of the first batch of primitives that have a same screen-space as tiles of the second batch of primitives based on a most-recently-processed-tile-to-a-least-recently-processed tile order of the second batch of primitives.

Abstract: A method for graphics processing. The method including rendering graphics for an application using graphics processing units (GPUs). The method including dividing responsibility for processing a plurality of pieces of geometry of an image frame during an analysis pre-pass phase of rendering between the plurality of GPUs, wherein each of the plurality of pieces of geometry is assigned to a corresponding GPU. The method including determining in the analysis pre-pass phase overlap of each the plurality of pieces of geometry with each of a plurality of screen regions. The method including generating information at the plurality of GPUs regarding the plurality of pieces of geometry and their relations to the plurality of screen regions based on the overlap of each the plurality of pieces of geometry with each of the plurality of screen regions.

Abstract: Techniques for inserting and extracting geolocation data using spatial indexing in a key value database are provided. In an embodiment, a system is provided for generating one or more geohashes for a geometry object, wherein the one or more geohashes comprises encoded bits that are stored as keys in a key value database. In one example, the system comprises a geometry indexing component that generates a spatial index, wherein the spatial index is based on a total number of the encoded bits generated for the one or more geohashes. In one example, the system comprises a geometry storing component that stores the geometry object and the one or more geohashes in the key value database using the spatial index to allow for faster retrieval of the geometry object. The advantage is that properly inserted and indexed spatial data can be quickly retrieved.

Abstract: A system and method runs a query using a GPU and generates a visualization of the query using the same GPU.

Abstract: A graphics processor is described that includes a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The multiprocessor can execute parallel threads of instructions associated with a command stream, where the multiprocessor includes a set of functional units to execute at least one of the parallel threads of the instructions. The set of functional units can include a mixed precision tensor processor to perform tensor computations to generate loss data. The loss data is stored as a floating-point data type and scaled by a scaling factor to enable a data distribution of a gradient tensor generated based on the loss data to be represented by a 16-bit floating point data type.

Abstract: A computer implemented method for generating synthetic training data to train a convolutional neural network is described. The method consists of steps including receiving a source image depicting an object for identification. The type and shape of the depicted object is determined. The source image is overlayed with a N×M grid of vertices, the grid including horizontal and vertical edges and being fit to the shape of the depicted object. For each vertex in the grid, perturbations are added to the (x,y) coordinates of the vertex and the pixel values in a range between the original and final (x,y) coordinates are interpolated, resulting in the generation of an item of synthetic training data. The method is repeated to generate multiple items of synthetic training data which are then used to train a neural network to identify the object in an image.

Abstract: Techniques related to selecting restoration filter coefficients for 2-dimensional loop restoration filters for super resolution video coding are discussed. Such techniques include upscaling reconstructed video frames along only a first dimension and selecting filter coefficients for portions of the frame by an evaluation that, for each pixel of the portion, uses only pixel values that are aligned with the first dimension. Selection of filter coefficients for the second dimension may be skipped or made using only a subset of available filter coefficients.

Abstract: A system for calculating. A scratch memory is connected to a plurality of configurable processing elements by a communication fabric including a plurality of configurable nodes. The scratch memory sends out a plurality of streams of data words. Each data word is either a configuration word used to set the configuration of a node or of a processing element, or a data word carrying an operand or a result of a calculation. Each processing element performs operations according to its current configuration and returns the results to the communication fabric, which conveys them back to the scratch memory.

Abstract: A computer can comprise a housing, a microprocessor disposed within the housing, a display, and a communication interface communicatively coupled to the microprocessor. The computer can be configured, responsive to locating decodable indicia within content viewable on the display, to decode the decodable indicia to produce at least one decoded message. The computer can be further configured to display the content with decoded message data being embedded into the content. The decoded message data can be provided by at least one decoded message, data derived from the decoded message.

Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.

Abstract: A video processor card for outputting video data, the video processor card being arranged for insertion into a video media server and into communication with an output of the video media server, the card comprising: an input for receiving a first video data stream at a first video resolution from the output of the video media server; a processor arranged to demultiplex the received first video data stream at the first resolution into a plurality of second video data streams, each second video data stream being at a second video resolution; and a plurality of video outputs, each video output arranged to output one of the plurality of second video data streams, wherein the first video resolution is at a higher video resolution than the second video resolution.

Abstract: In one embodiment, a system on chip includes: a plurality of intellectual property (IP) agents formed on a semiconductor die; a mesh interconnect formed on the semiconductor die to couple the plurality of IP agents, and a plurality of mesh stops each to couple one or more of the plurality of IP agents to the mesh interconnect. The mesh interconnect may be formed of a plurality of rows each having one of a plurality of horizontal interconnects and a plurality of columns each having one of a plurality of vertical interconnects;, where at least one of the plurality of rows includes an asymmetrical number of mesh stops. Other embodiments are described and claimed.

Abstract: A method for image processing, which comprises the following steps: Generating a first histogram from a first image; Calculating a first parameter profile from the first image indicative of the quality of the first image; Adjusting the first parameter profile to generate a second parameter profile; Using the second parameter profile to generate a statistical distribution via a statistical distribution generator, wherein the statistical distribution is characterized by at least three parameters; Using the statistical distribution to perform a histogram specification to the first histogram of the first image to generate a second histogram; Generating a second image based on the first image and the second histogram.

Abstract: The present disclosure relates to an image processing method, a server, a client and an image processing system. The image processing method is applicable to the server and includes: receiving an image processing request from the client, wherein the image processing request includes a to-be-processed image in a first image format; acquiring the to-be-processed image according to the image processing request, and processing the to-be-processed image to obtain a target image in a second image format; and generating a feedback message according to the target image, and sending the feedback message to the client.

Abstract: Various embodiments described herein provide for a memory device that can service a high priority read request during data input without losing the data inputted to the memory device prior to the high priority read request, without re-requesting data from a host, and while leaving one or more internal resources of a memory sub-system available for use by an error correction function of the memory sub-system.

Abstract: A method for graphics processing. The method including rendering graphics for an application using a plurality of graphics processing units (GPUs). The method including dividing responsibility for the rendering of geometry of the graphics between the plurality of GPUs based on a plurality of screen regions that are interleaved, each GPU having a corresponding division of the responsibility which is known to the plurality of GPUs. The method including assigning a GPU a piece of geometry of an image frame generated by an application for geometry pretesting. The method including performing geometry pretesting at the GPU to generate information regarding the piece of geometry and its relation to each of the plurality of screen regions. The method including using the information at each of the plurality of GPUs when rendering the image frame.

Abstract: A computer including a subdividing section subdividing image data into plural subdivided image data, a control section that causes each of plural cores included a first processing unit to execute in parallel tasks on the subdivided image data, the tasks enabled for processing according to their precedence dependency relationship, a registration section that, if a task is executable by a second processing unit asynchronously with respect to the first processing unit, register a finish detection task to detect completion of the task on the second processing unit in a list after causing a core of the first processing unit to execute an execution instruction task instructing execution of the task on the second processing unit, and a determination section that accesses the list and to determine whether or not there is a completed finish detection task.

Abstract: An image drawing device includes a first processor that generates second drawing data and second drawing command groups from first drawing data and first drawing command groups and a second processor. The first processor includes a drawing command reorder unit that generates third drawing command groups by changing an arrangement order of the first drawing command groups and deleting first drawing commands that have become unnecessary to execute due to the changing of the arrangement order of the first drawing command groups, a drawing command combination unit that generates the second drawing command groups by combining pieces of first drawing data corresponding to third drawing commands that can be executed by the second processor in the same drawing condition and deleting unnecessary third drawing commands, and a drawing command execution unit that executes each of the second drawing commands in an arrangement order of the second drawing commands.

Abstract: The present technology relates to an image processing apparatus, an image processing method, and a surgical system, by which a captured image can be displayed with low latency in almost real time. A DMA controller 51 of a CPU 31 divides image data, which is input via an IF card 34, by the number of GPU cards 35-1, 35-2 in a horizontal direction and allocates them. In each of the GPU cards 35-1, 35-2, the image data is subjected to time division processing in the vertical direction. With this, the use of the plurality of GPU cards 35-1, 35-2 increases the speed of processing associated with display for the image data. High-speed display is realized due to reduction in latency. The present technology is applicable to an endoscopic camera, a surgical microscope, and the like.

Abstract: A graphics processing unit (GPU) sequences provision of operands to a set of operand registers, thereby allowing the GPU to share at least one of the operand registers between processing. The GPU includes a plurality of arithmetic logic units (ALUs) with at least one of the ALUs configured to perform double precision operations. The GPU further includes a set of operand registers configured to store single precision operands. For a plurality of executing threads that request double precision operations, the GPU stores the corresponding operands at the operand registers. Over a plurality of execution cycles, the GPU sequences transfer of operands from the set of operand registers to a designated double precision operand register. During each execution cycle, the double-precision ALU executes a double precision operation using the operand stored at the double precision operand register.

Abstract: The present application discloses display apparatus for displaying image based on time-divisional data. The display apparatus includes a data processor including at least a first shift register and a data buffer, and configured to store a first matrix of data corresponding to the frame of image data to the data buffer at time t0, to shift the first matrix of data by m columns by the first shift register to obtain a second matrix of data stored to the data buffer at time t1. The display apparatus further includes an interface connector configured to output the first matrix of data in period T0 and the second matrix of data in period T1 in a same order same as the fixed sequential order respectively over the at least two time-divisional periods T0 and T1 of a unit-time through a driver circuit to a display panel for displaying one frame of image.

Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: partition pixel values in a unit of row of an input image into a plurality of sections and allocates threads to the respective sections of the row, the threads being enabled to run in parallel by a processor; calculate, with each of the threads allocated in each row, distances each from a pixel having a certain value in the corresponding section of the row in the input image, and generates a first distance image which stores values indicating the distances; and calculate, with each of the threads allocated in each row, a first boundary value indicating a distance from a pixel having the certain value in another section of each row, by using a calculation result of the first boundary value in the another section of each row.

Abstract: Disclosed herein are an apparatus and method for adaptively accelerating a BLAS operation based on a GPU. The apparatus for adaptively accelerating a BLAS operation based on a GPU includes a BLAS operation acceleration unit for setting optimal OpenCL parameters using machine-learning data attribute information and OpenCL device information and for creating a kernel in a binary format by compiling kernel source code; an OpenCL execution unit for creating an OpenCL buffer for a BLAS operation using information about an OpenCL execution environment and the optimal OpenCL parameters and for accelerating machine learning in an embedded system in such a way that a GPU that is capable of accessing the created OpenCL buffer performs the BLAS operation using the kernel, and an accelerator application unit for returning the result of the BLAS operation to a machine-learning algorithm.

Abstract: A method for processing data includes receiving a write request by a host operating system during a predetermined time window, storing data associated with the write request in a shared memory, making a first determination that a threshold number of write requests are obtained within the predetermined time window, and, in response to the first determination, sending an offload request to a virtual machine (VM), wherein the offload request specifies at least the write request.

Abstract: In a data prefetching method, a storage device obtains a first sequence stream length and a first access count of a target logical block after execution of a first data access request is completed. When a second data access request is received, the storage device modifies the first sequence stream length to a second sequence stream length and modifies the first access count to a second access count. The storage device further calculates a sequence degree of the target logical block based on the second sequence stream length and the second access count, and performs a data prefetching operation when the sequence degree of the target logical block exceeds a first prefetch threshold.

Abstract: Provided is a solid-state imaging device that includes a pixel array portion in which a plurality of pixels are arranged in a two-dimensional array, an AD conversion unit configured to perform AD conversion with respect to a pixel signal output from the pixel of the pixel array portion, a memory configured to retain a digital pixel signal after the AD conversion, and an image signal processing circuit configured to perform predetermined signal processing with respect to the digital pixel signal. The image signal processing circuit includes two or more PUs including one or more PEs configured to execute predetermined arithmetic processing, and a CU configured to operate the PE in an SIMD format, an IMEM configured to store one or more arithmetic processing instructions, and a CCU configured to control the PU.

Abstract: A living organism image monitoring system is provided, relating to the technical field of medical equipment. The living organism image monitoring system comprises a display module, a processor and a CIGS chip, the CIGS chip, the processor and the display module being electrically connected, the CIGS chip being used for detecting a near infrared light signal of a living organism and generating a current signal after having detected the near infrared light signal, the processor being used for generating a first pulse signal according to the current signal, and the display module being used for displaying an image according to the first pulse signal. The living organism image monitoring system provided by the present disclosure has the advantages of being capable of synchronously transmitting the images of a living organism to the display module for display and enabling the images to be clearer.

Abstract: An electronic device may include an electronic display to display an image based on scaled image data and variable scaling circuitry to generate the scaled image data. Generating the scaled image data may include receiving input pixel values in a first resolution and determining multiple tap point locations based on a scaling ratio to be applied to the input pixel values. Generating the scaled image data may also include determining weighting coefficients based on a scaling curve and the tap point locations, and weighting the input pixel values based on the weighting coefficients. The variable scaling circuitry may generate the scaled image data at a second resolution based on the aggregation of the weighted input pixel values.

Abstract: A method including rendering graphics for an application using graphics processing units (GPUs). Responsibility for rendering of geometry is divided between GPUs based on screen regions, each GPU having a corresponding division of the responsibility which is known. First pieces of geometry are rendered at the GPUs during a rendering phase of a previous image frame. Statistics are generated for the rendering of the previous image frame. Second pieces of geometry of a current image frame are assigned based on the statistics to the GPUs for geometry testing. Geometry testing at a current image frame on the second pieces of geometry is performed to generate information regarding each piece of geometry and its relation to each screen region, the geometry testing performed at each of the GPUs based on the assigning. The information generated for the second pieces of geometry is used when rendering the geometry at the GPUs.

Abstract: A technology is described for extending a data store operation using a function object. An example method may include receiving a request that includes request attributes to execute a data store operation. The request may be received at a data store system via a virtual computer network in a service provider environment. After receiving the request to execute the data store operation, the request may be analyzed to identify a request attribute associated with a function object that extends the functionality of the data store operation. The function object associated with the request attribute may be identified and the function object may be executed in association with executing the data store operation.

Abstract: An apparatus and method for multi-adapter and/or multi-pass encoding on dual graphics processors. For example, one embodiment of a processor comprises: a central processor integrated on a first die, the central processor comprising a plurality of cores to execute instructions and process data; an first graphics processor integrated on the first die, the first graphics processor comprising media processing circuitry to perform one or more preliminary lookahead operations on video content to generate lookahead statistics; an interconnect to couple the first graphics processor to a lookahead buffer, the first graphics processor to transmit the lookahead statistics over the interconnect to the lookahead buffer; wherein the lookahead statistics are to be used by a second graphics processor to encode the video content to generate encoded video.

Abstract: Systems and method for triple buffering of a graphics display without use of interrupts using at least two command buffers that are capable of operating asynchronously. A first command buffer generally contains commands, which, when executed, write frame data to a plurality of frame buffers in round-robin fashion. A second command buffer, which is executed asynchronously to the first command buffer, contains commands to handle waiting for frames to be completed, handle display timing (e.g., display synchronization interval, such vertical sync or vertical blanking intervals), and to cause the display controller to display the correct frames.

Abstract: A display scene processing method and a display scene processing device and a storage medium thereof are disclosed. The display scene processing method includes the following steps: obtaining a vertical synchronization signal; executing a rendering thread to render a first half-screen scene data and a second half-screen scene data based on the vertical synchronization signal; executing an asynchronous time warping thread to correct the rendered first half-screen scene data and the rendered second half-screen scene data to obtain first half-screen scene correction data and second half-screen scene correction data.

Abstract: A system includes a direct memory access controller and a memory coupled to the direct memory access controller. The memory stores a linked list of records. Each record contains a first field determining the number of fields of a next record. For example, each record can be representative of parameters of execution of a data transfer by the direct memory access controller.

Abstract: A game rendering method and a terminal are provided. The method includes the following. A rendering instruction is stored when a JS engine of the terminal receives the rendering instruction, where the rendering instruction carries a plurality of data identifiers of to-be-rendered data, a plurality of time interval identifiers corresponding to the data identifiers, and a plurality of rendering parameter identifiers corresponding to the time interval identifiers. The rendering instruction is sent to a target rendering system. A target time interval identifier corresponding to current time is determined, and a target data identifier and a target rendering parameter identifier corresponding to the target time interval identifier are determined. To-be-rendered data corresponding to the target data identifier and target rendering parameter corresponding to the target rendering parameter identifier, are determined.

Abstract: Some embodiments provide a non-transitory machine-readable medium that stores a program. The program receives a request to geo-enrich data comprising a set of location data. The program further accesses shape data comprising a plurality of shapes associated with a plurality of geographical regions. The program also associates, for each location data in the set of location data, a shape in the plurality of shape with the location data.

Abstract: Embodiments disclosed herein relate to a graphics processing chip for rendering computer graphics. The graphics processing chip may include a controller configured to manage operations of the graphics processing chip in accordance with a graphics-rendering pipeline. The operations may include geometry-processing operations, rasterization operations, and shading operations. The chip may further include programmable memory components configured to store a machine-learning model configured to perform at least a portion of the shading operations. The chip may also include a plurality of processing units configured to be selectively used to perform the shading operations in accordance with the machine-learning model. The chip may also include at least one output memory configured to store image data generated using the shading operations.

Abstract: Systems, methods, devices, media, and computer readable instructions are described for local image tagging in a resource constrained environment. One embodiment involves processing image data using a deep convolutional neural network (DCNN) comprising at least a first subgraph and a second subgraph, the first subgraph comprising at least a first layer and a second layer, processing, the image data using at least the first layer of the first subgraph to generate first intermediate output data; processing, by the mobile device, the first intermediate output data using at least the second layer of the first subgraph to generate first subgraph output data, and in response to a determination that each layer reliant on the first intermediate data have completed processing, deleting the first intermediate data from the mobile device. Additional embodiments involve convolving entire pixel resolutions of the image data against kernels in different layers if the DCNN.

Abstract: A scheduler is provided for tall algorithms that include control flow statements that are dependent on tall computations. Thunks may be defined for the tall algorithms and the boundaries or limits of the thunks may be determined by places where tall variables are required to be gathered. The scheduler executes the tall algorithms by calling individually the thunks from the tall algorithms and pausing when a gather operation is required. The scheduler collectively gathers the tall variables from different tall algorithms by using an optimizer to combine I/O operations for the tall algorithms. The scheduler may put back the gathered variables into the context of each tall algorithm, and the scheduler may resume with the next thunk for each tall algorithm. This process may be repeated until all tall algorithms are finished.

Abstract: A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes a general purpose CPU executing commands in a CPU programming language and a graphic processing unit (GPU) executing commands in a GPU programming language. A command processor is coupled to the CPU and CPU. The command processor sequences jobs from a program for processing by the CPU or the GPU. The command processor creates commands from the jobs in a state free command format. The command processor generates a sequence of commands for execution by either the CPU or the GPU in the command format. A compiler running a meta language converts program data for the commands into a first format readable by the CPU programming language and a second format readable by the GPU programming language.

Abstract: Systems, computer readable media, and methods for a unified programming interface and language are disclosed. In one embodiment, the unified programming interface and language assists program developers write multi-threaded programs that can perform both graphics and data-parallel compute processing on GPUs. The same GPU programming language model can be used to describe both graphics shaders and compute kernels, and the same data structures and resources may be used for both graphics and compute operations. Developers can use multithreading efficiently to create and submit command buffers in parallel.

Abstract: An apparatus and method for virtualized scheduling. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising a plurality of graphics processing engines, each of the graphics processing engines usable to execute graphics program code for a plurality of graphics contexts, each of the graphics contexts associated with a particular user mode driver (UMD); and a scheduler to schedule the graphics program code for execution on the plurality of graphics engines, the scheduler comprising an integrated context queue to store program code from all of the graphics contexts, the scheduler to select graphics processing engines to execute the program code from each context based on a detected load and/or availability of each graphics processing engine and to determine an order for executing the program code from each context based on relative priorities associated with the different contexts.

Abstract: Labeled data is deterministically generated for training or validating machine learning models for image analysis. Approaches are described that allow this training data to be generated, for example, in real-time, and in response to the conditions at the location where images are generated by image sensors.

Abstract: Disclosed are systems and methods for editing aggregated data based on edit requests that are received. An edit file is updated to include a newly-received edit. The edit file includes anchor points that each point to one of a plurality of aggregate data objects. The anchor points are used to determine one of the objects to which the edit file corresponds. The edit file is then applied to update data in this object including making the new edit.

Abstract: A method and apparatus that incorporate teachings of the present disclosure may include, for example, receiving at a mobile communication device a video stream from a computing device. The video stream is associated with images generated by a software application and is transmitted by the computing device responsive to a request to redirect control of the software application to the mobile communication device. The method may also include presenting the streamed video at the mobile communication device and transmitting to the computing device a stimulation of a remote user input function associated with the mobile communication device, where the transmitted stimulation corresponds to at least one action of a plurality of associable actions that can be executed by the software application. Additional embodiments are disclosed.

Abstract: Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.

Abstract: A data processing system comprises processing circuitry arranged to generate data to form an output array of data, processing circuitry arranged to store the generated data in an output buffer 15 by writing compressed blocks of data representing particular regions of the output array of data to the output buffer, processing circuitry 14 arranged to read a compressed block of data representing a particular region of the array of data from the output buffer, processing circuitry 16 arranged to acquire meta-data from the compressed block of data, and processing circuitry 21 arranged to process the block of data. The acquired meta-data is used to affect the processing of the block of data.

Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.