Parallel Processors (e.g., Identical Processors) Patents (Class 345/505)
  • Patent number: 10922585
    Abstract: Labeled data is deterministically generated for training or validating machine learning models for image analysis. Approaches are described that allow this training data to be generated, for example, in real-time, and in response to the conditions at the location where images are generated by image sensors.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: February 16, 2021
    Assignee: Recogni Inc.
    Inventors: Shabarivas Abhiram, Eugene M. Feinberg
  • Patent number: 10891303
    Abstract: Disclosed are systems and methods for editing aggregated data based on edit requests that are received. An edit file is updated to include a newly-received edit. The edit file includes anchor points that each point to one of a plurality of aggregate data objects. The anchor points are used to determine one of the objects to which the edit file corresponds. The edit file is then applied to update data in this object including making the new edit.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: January 12, 2021
    Assignee: VERIZON MEDIA INC.
    Inventors: Brian Hein, Peter Monaco, Richard Sarvate, Nitish Dalal
  • Patent number: 10831433
    Abstract: A method and apparatus that incorporate teachings of the present disclosure may include, for example, receiving at a mobile communication device a video stream from a computing device. The video stream is associated with images generated by a software application and is transmitted by the computing device responsive to a request to redirect control of the software application to the mobile communication device. The method may also include presenting the streamed video at the mobile communication device and transmitting to the computing device a stimulation of a remote user input function associated with the mobile communication device, where the transmitted stimulation corresponds to at least one action of a plurality of associable actions that can be executed by the software application. Additional embodiments are disclosed.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 10, 2020
    Assignee: STEELSERIES ApS
    Inventors: Bruce Hawver, Jacob Wolff-Petersen
  • Patent number: 10831541
    Abstract: Example embodiments of the present disclosure provide methods and devices for optimizing performance of hardware accelerators. The accelerator device may detect status information of a current acceleration task being executed. The detected status information is provided to a host associated with the accelerator device. The host makes preparation for a subsequent acceleration task based on the status information before termination of the current running acceleration task. The accelerator device may execute the subsequent acceleration task based on the preparation. In this way, the performance of hardware accelerator is optimized.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yang Liu, Yong Lu, Peng Ou, Hong Bo Peng
  • Patent number: 10825128
    Abstract: A data processing system comprises processing circuitry arranged to generate data to form an output array of data, processing circuitry arranged to store the generated data in an output buffer 15 by writing compressed blocks of data representing particular regions of the output array of data to the output buffer, processing circuitry 14 arranged to read a compressed block of data representing a particular region of the array of data from the output buffer, processing circuitry 16 arranged to acquire meta-data from the compressed block of data, and processing circuitry 21 arranged to process the block of data. The acquired meta-data is used to affect the processing of the block of data.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: November 3, 2020
    Assignee: Arm Limited
    Inventors: Daren Croxford, Ben James, Sean Ellis, Edward Charles Plowman
  • Patent number: 10796472
    Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.
    Type: Grant
    Filed: June 30, 2018
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Michael Apodaca, Ankur Shah, Ben Ashbaugh, Brandon Fliflet, Hema Nalluri, Pattabhiraman K, Peter Doyle, Joseph Koston, James Valerio, Murali Ramadoss, Altug Koker, Aditya Navale, Prasoonkumar Surti, Balaji Vembu
  • Patent number: 10783695
    Abstract: In one embodiment, a computing system may determine a pixel area in a two-dimensional coordinate system associated with a display. The system may project the pixel area into a three-dimensional coordinate system to determine a projected area in the three-dimensional coordinate system. Based on the projected area, the system may access a portion of an analytical definition of a glyph, the portion of the analytical definition defining one or more areas of the glyph. The system may compute a coverage proportion of the pixel area that overlaps with the one or more areas of the glyph. The system may then determine a color for the pixel area based on the coverage proportion.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 22, 2020
    Assignee: Facebook Technologies, LLC
    Inventor: Warren Andrew Hunt
  • Patent number: 10768896
    Abstract: An apparatus and method for performing a reciprocal. For example one embodiment of a processor comprises: a decoder to decode a reciprocal instruction to generate a decoded reciprocal instruction; a source register to store at least one packed input data element; a destination register to store a result data element; and reciprocal execution circuitry to execute the decoded reciprocal instruction, the reciprocal execution circuitry to use a first portion of the packed input data element as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, the reciprocal execution circuitry to generate a reciprocal of the packed input data element using a combination of the coefficients and a second portion of the packed input data element.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Cristina Anderson, Elmoustapha Ould-Ahmed-Vall, Marius Cornea-Hasegan, Robert Valentine, Mark Charney, Jesus Corbal, Venkateswara Madduri
  • Patent number: 10740950
    Abstract: A geometry processing phase of tile-based rendering includes a plurality of parallel geometry pipelines, a plurality of tiling pipelines and a geometry to tiling arbiter situated between the plurality of geometry pipelines and the plurality of tiling pipelines. Each geometry pipeline is configured to: generate one or more geometry blocks for each geometry group of a subset of ordered geometry groups; generate a corresponding primitive position block for each geometry block, and compress each geometry blocks to generate a corresponding compressed geometry block. The tiling pipelines are configured to generate, from the primitive position blocks, a list for each tile indicating primitives that fall within the bounds of that tile. The geometry to tiling arbiter is configured to forward the primitive position blocks generated by the plurality of geometry pipelines to the plurality of tiling pipelines in the correct order based on the order of the geometry groups.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: August 11, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Tim Rollingson, Jairaj Dave
  • Patent number: 10732855
    Abstract: A storage system includes a storage device including a controller and a nonvolatile memory unit, and a host including a processor configured to determine whether or not the host is going to access the storage device within a predetermined range of time, and cause the storage device to be powered off when it is determined that the host is not going to access the storage device within the predetermined range of time.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: August 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Daisuke Hashimoto
  • Patent number: 10699464
    Abstract: Methods for enabling graphics features in processors are described herein. Methods are provided to enable trinary built-in functions in the shader, allow separation of the graphics processor's address space from the requirement that all textures must be physically backed, enable use of a sparse buffer allocated in virtual memory, allow a reference value used for stencil test to be generated and exported from a fragment shader, provide support for use specific operations in the stencil buffers, allow capture of multiple transform feedback streams, allow any combination of streams for rasterization, allow a same set of primitives to be used with multiple transform feedback streams as with a single stream, allow rendering to be directed to layered framebuffer attachments with only a vertex and fragment shader present, and allow geometry to be directed to one of an array of several independent viewport rectangles without a geometry shader.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: June 30, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Graham Sellers, Eric Zolnowski, Pierre Boudier, Juraj Obert
  • Patent number: 10691616
    Abstract: A method is provided for use in a distributed storage system having a write cache, the method comprising: receiving, by a first node in the distributed storage system, a first Remote Procedure Call (RPC) command to perform a partial update to a buffer that is stored in a memory of the first node, the partial update including replacing old data that is present in the buffer with new data that is stored in the write cache; transmitting, from the first node to a second node, a second RPC command instructing the second node to provide the new data to the first node by executing a Remote Direct Memory Access (RDMA) write operation into the memory of the first node; and performing the partial update based on the new data when the RDMA. write operation is completed and the new data is received by the first node as a result.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: June 23, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Lior Kamran
  • Patent number: 10679318
    Abstract: A graphics processing method is provided, adapted to a graphic processing unit, the steps including: receiving, via a CSP, a first command associated with all render targets from a display driver; determining, via the display driver, sizes and areas of a plurality of tiles in each frame; repeatedly controlling, via a scissor pool unit, a graphics processing unit to perform drawing processing for each tile according to the first command; comparing, via a signature comparing unit of a cache memory, a signature of a current tile of a current frame and a signature of a tile corresponding to the same position of a previous frame and generating a comparison result; and determining whether to flush the dirty data of the current tile stored in the cache memory from the cache memory to a memory access unit according to the comparison result.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: June 9, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Fengxia Wu, Deming Gu, Heng Que, Yi Zhou, Ying Wang
  • Patent number: 10628908
    Abstract: Methods, systems, and computer-readable media for application-specific virtualized graphics processing are disclosed. A virtual compute instance is provisioned from a provider network. The provider network comprises a plurality of computing devices configured to implement a plurality of virtual compute instances with multi-tenancy. A virtual GPU is attached to the virtual compute instance. The virtual GPU is selected based at least in part on requirements of an application. The virtual GPU is implemented using a physical GPU, and the physical GPU is accessible to the virtual compute instance over a network. The application is executed using the virtual GPU on the virtual compute instance.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 21, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Nicholas Patrick Wilt, Ashutosh Tambe, Nathan Lee Burns
  • Patent number: 10621109
    Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline to bypass a memory access for the first virtual page based on the first page table entry, wherein the graphics pipeline is to read a field in the first page table entry to determine a value of the clear color.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Abhishek R. Appu, Kiran C. Veernapu
  • Patent number: 10613806
    Abstract: A control device includes: a receiving unit that receives a request for processing; a determination unit that determines a processing apparatus to be moved from among a plurality of processing apparatuses based on a predetermined standard in a case where the receiving unit receives a request for processing; and a control unit that controls movement of the processing apparatus based on a result of determination performed by the determination unit.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: April 7, 2020
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Naoya Ogata, Hajime Kajiyama, Hideki Fujimoto, Kunitoshi Yamamoto, Akira Ichikawa, Mariko Miyazaki, Tetsuya Kobayashi
  • Patent number: 10614772
    Abstract: A display method and a terminal device are provided, so as to resolve a prior-art problem that CPU power consumption of the terminal device is relatively high because a display system of the terminal device processes three procedures in parallel in a Vsync period. The method is: determining, by the display system of the terminal device, a start moment of a first procedure in an (M+1)th Vsync period according to first processing duration of the first procedure in an Mth Vsync period, so that the display system starts to execute a device display procedure before starting to execute the first procedure, the display system delays executing the first procedure in the (M+1)th Vsync period, so that a time required for processing three procedures in parallel in the (M+1)th Vsync period by the display system is reduced, and CPU power consumption of the terminal device is reduced.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: April 7, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jing Zhao, Bo Yu
  • Patent number: 10558466
    Abstract: Systems, apparatuses, and methods for adjusting group sizes to match a processor lane width are described. In early iterations of an algorithm, a processor partitions a dataset into groups of data points which are integer multiples of the processing lane width of the processor. For example, when performing a K-means clustering algorithm, the processor determines that a first plurality of data points belong to a first group during a given iteration. If the first plurality of data points is not an integer multiple of the number of processing lanes, then the processor reassigns a first number of data points from the first plurality of data points to one or more other groups. The processor then performs the next iteration with these first number of data points assigned to other groups even though the first number of data points actually meets the algorithmic criteria for belonging to the first group.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: February 11, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Mayank Daga
  • Patent number: 10554766
    Abstract: Some embodiments provide a non-transitory machine-readable medium that stores a program. The program receives a request to geo-enrich data comprising a set of location data. The program further accesses shape data comprising a plurality of shapes associated with a plurality of geographical regions. The program also associates, for each location data in the set of location data, a shape in the plurality of shape with the location data.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 4, 2020
    Assignee: SAP SE
    Inventors: Christopher Bolognese, Jonathan Tiu, Xing Jin, Sae-Won Om, Lyndon Hiew
  • Patent number: 10546411
    Abstract: Embodiments provide for an apparatus including one or more processors having logic to enumerate a directed path through nodes of a directed acyclic graph, the logic to determine a key for a node and a path identifier for a directed path between nodes of the directed acyclic graph.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 28, 2020
    Assignee: INTEL CORPORATION
    Inventor: Louis Feng
  • Patent number: 10545244
    Abstract: Methods, systems, and computer programs are presented for cloud-offloaded position calculation with on-device acquisition. One method includes operations for collecting raw global positioning system (GPS) signals for a set of positions, and storing in memory the raw GPS signals. The method further includes processing the raw GPS signals in batch mode at the computing device to obtain acquisition data for the positions, where the processing includes identifying tasks for parallel processing by a graphics processing unit (GPU), performing, by the GPU, the tasks in parallel by assigning each of the tasks to a core processor within the GPU, and combining results from performing the tasks to obtain the acquisition data. Additionally, the method includes an operation for transmitting the acquisition data to a server for calculating locations for the set positions at the server, the server storing the locations and making the locations available for location-tracking applications.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: January 28, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jie Liu, Nissanka Arachchige Bodhi Priyantha, Lucas N Joppa, Qiang Xu
  • Patent number: 10540583
    Abstract: Technical solutions are described to accelerate training of a multi-layer convolutional neural network. According to one aspect, a computer implemented method is described. A convolutional layer includes input maps, convolutional kernels, and output maps. The method includes a forward pass, a backward pass, and an update pass that each include convolution calculations. The described method performs the convolutional operations involved in the forward, the backward, and the update passes based on a first, a second, and a third perforation map respectively. The perforation maps are stochastically generated, and distinct from each other. The method further includes interpolating results of the selective convolution operations to obtain remaining results. The method includes iteratively repeating the forward pass, the backward pass, and the update pass until the convolutional neural network is trained. Other aspects such as a system, apparatus, and computer program product are also described.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leland Chang, Suyog Gupta
  • Patent number: 10521880
    Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive one or more frames for a workload, determine one or more compute resource parameters for the workload, and store the one or more compute resource parameters for the workload in a memory in association with workload context data for the workload. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 31, 2019
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Josh B. Mastronarde, Altug Koker, Nikos Kaburlasos, Abhishek R. Appu, Joydeep Ray
  • Patent number: 10509737
    Abstract: A data processing system for a graphical interface includes at least one graphics processing unit (GPU) and at least one central processing unit (CPU) which communicates with the graphics processing unit, said processing unit and said central processing unit each including a group of data processing cores (C1, . . . , C6, C?1, . . . C?6). The data processing cores of the graphics processing unit are each connected to a data processing core of the central processing unit via a single dedicated bus (B1, . . . , B6) in such a way as to carry out a data transfer in parallel between said graphics processing unit and said central processing unit.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: December 17, 2019
    Assignee: Zodiac Aero Electric
    Inventors: Etienne Denis Marie Zante, Rémi Andreoletti
  • Patent number: 10475149
    Abstract: Virtual reality systems and methods are described. For example, one embodiment of an apparatus comprises: a communications interface to provide frame data of a virtual reality scene to a head mounted display (HMD); at least one performance monitor coupled to at least one component of the apparatus the at least one performance monitor to monitor performance of the at least one component and to send an alert based on the performance of the at least one component; a processor to process the frame data; a controller to receive the alert based on the performance of the at least one component and to offload processing of the frame data from the processor to the HMD for processing; and a display to show the rendered view of the scene.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 12, 2019
    Assignee: INTEL CORPORATION
    Inventors: Paul S. Diefenbaugh, Karthik Veeramani, Deepak S. Vembar, Rajneesh Chowdhury, Atsuo Kuwahara
  • Patent number: 10467724
    Abstract: Techniques are disclosed relating to dispatching compute work from a compute stream. In some embodiments, workgroup batch circuitry is configured to select (e.g., in a single clock cycle) multiple workgroups to be distributed to different shader circuitry. In some embodiments, iterator circuitry is configured to determine next positions in different dimensions at least partially in parallel. For example, in some embodiments, first circuitry is configured to determine a next position in a first dimension and an increment amount for a second dimension. In some embodiments, second circuitry is configured to determine at least partially in parallel with the determination of the next position in the first dimension, next positions in the second dimension for multiple possible increment amounts in the second dimension. In some embodiments, this may facilitate a configurable number of workgroups per batch and may increase performance, e.g., by increasing the overall number of workgroups dispatched per clock cycle.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: November 5, 2019
    Assignee: Apple Inc.
    Inventors: Andrew M. Havlir, Jeffrey T. Brady
  • Patent number: 10459445
    Abstract: According to various aspects, an unmanned aerial vehicle may be described, the unmanned aerial vehicle including: one or more sensors configured to gather thermal information associated with a vicinity of the unmanned aerial vehicle; one or more processors configured to determine at least one control information based on the thermal information and to control the unmanned aerial vehicle based on the at least one control information.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 29, 2019
    Assignee: Intel IP Corporation
    Inventors: Stefan Menzel, Daniel Pohl, Thomas Seiler, Markus Achtelik
  • Patent number: 10440241
    Abstract: The present technology relates to an image processing apparatus, an image processing method, and a surgical system, by which a captured image can be displayed with low latency in almost real time. A DMA controller 51 of a CPU 31 divides image data, which is input via an IF card 34, by the number of GPU cards 35-1, 35-2 in a horizontal direction and allocates them. In each of the GPU cards 35-1, 35-2, the image data is subjected to time division processing in the vertical direction. With this, the use of the plurality of GPU cards 35-1, 35-2 increases the speed of processing associated with display for the image data. High-speed display is realized due to reduction in latency. The present technology is applicable to an endoscopic camera, a surgical microscope, and the like.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: October 8, 2019
    Assignee: SONY CORPORATION
    Inventors: Masahito Yamane, Tsuneo Hayashi
  • Patent number: 10437573
    Abstract: General-purpose distributed data-parallel computing using a high-level language is disclosed. Data parallel portions of a sequential program that is written by a developer in a high-level language are automatically translated into a distributed execution plan. The distributed execution plan is then executed on large compute clusters. Thus, the developer is allowed to write the program using familiar programming constructs in the high level language. Moreover, developers without experience with distributed compute systems are able to take advantage of such systems.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: October 8, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Yuan Yu, Dennis Fetterly, Michael Isard, Ulfar Erlingsson, Mihai Budiu
  • Patent number: 10420999
    Abstract: Systems and techniques for sensor-derived object flight performance tracking are described herein. A set of magnetometer readings may be obtained from a magnetometer included with an object. A local rotation axis of the object may be determined at a time using the set of magnetometer readings. The local rotation axis may describe rotation of the object around a local magnetic target. A global rotation axis may be calculated based on an initial orientation of the object. The global rotation axis may describe a fixed rotation axis of the object during flight in a global coordinate frame, wherein an angle between the global rotation axis and magnetic north remains constant during the flight. An orientation of the object may be determined for the time using the global rotation axis and the local rotation axis of the object at the time.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Narayan Sundararajan, Xue Yang, Suresh V. Golwalkar, Mahanth Gowda, Romit Roy Choudhury
  • Patent number: 10423625
    Abstract: An approach for distributed stream computing in non-idempotent output operations is provided. The approach assigns an eventid to a corresponding entityid. The approach determines a minibatchid and a partitionid for a partition. The approach determines whether the partition was previously processed. The approach generates a new minibatchid and a new partitionid for a new partition based upon determining the partition was not previously processed. The approach determines whether a record was previously processed based upon determining the partition was previously processed. The approach processes the record of the partition based upon determining the record was not previously processed.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: September 24, 2019
    Assignee: SAMSUNG SDS AMERICA, INC.
    Inventors: Partho Datta, Girish Kathalagiri Somashekariah
  • Patent number: 10410406
    Abstract: A method of rendering a three-dimensional point cloud in a two-dimensional display includes inputting the three-dimensional point cloud that includes three-dimensional coordinates of a set of points, creating a depth buffer for the three-dimensional point cloud that includes depth data for the set of points from a viewpoint location. The method further includes determining a foreground depth buffer by, for each respective pixel area of the two-dimensional display, determining a foreground depth by detecting a closest point to the viewpoint location among a subset of the set of points corresponding to the respective pixel area, and assigning a depth of the closest point as the foreground depth for the respective pixel area. The method further includes filtering the depth buffer to obtain a filtered depth buffer by removing points that are not in the foreground, and outputting the filtered depth buffer to the two-dimensional display.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 10, 2019
    Assignee: Trimble AB
    Inventors: Andrés Serna, Thomas Chaperon
  • Patent number: 10409571
    Abstract: Apparatus and method for optimizing shader execution. For example, one embodiment of a graphics processing apparatus comprises: a plurality of execution units to execute shader programs; optimization detection circuitry and/or logic to identify one or more portions of shader program code to be optimized including one or more reduction operations which require read/write memory operations and associated barrier operations; and optimization circuitry and/or logic to optimize the shader program code by converting a plurality of the read/write memory operations to read/write register operations and removing one or more barrier operations to generate optimized shader program code; the execution units to execute the optimized shader program code.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventor: Marek Targowski
  • Patent number: 10402415
    Abstract: An intelligently distributed stage data mining system is disclosed herein, including an intelligent central server, a first WLAN receiving and transmitting unit, a local cluster control unit, a second WLAN receiving and transmitting unit, a third WLAN receiving and transmitting unit, a self-adaptive multi-dimensional transmission processing unit, a plurality of ZigBee receiving and transmitting units and a distributed data extraction unit. The intelligent central server is used for sending data acquisition and stage correction instruction to the local cluster control unit, and for receiving the stage real-time data uploaded by the self-adaptive multi-dimensional transmission processing unit. The local cluster control unit is used for receiving the data acquisition instruction sent by the intelligent central server, and forwarding instructions to the self-adaptive multi-dimensional transmission processing unit.
    Type: Grant
    Filed: July 10, 2016
    Date of Patent: September 3, 2019
    Assignee: ZHEJIANG DAFENG INDUSTRY CO., LTD
    Inventors: Hua Feng, Qiyun Feng, Zhen Liu, Haihong Tian, Dong Wang, Lifeng Wu
  • Patent number: 10388033
    Abstract: A texture processor includes: a texture cache configured to store textures; a controller configured to determine a texture address corresponding to a requested texture among the stored textures and read a texture corresponding to the texture address from the texture cache; a format converter configured to convert a format of the read texture into another format, based on a degree of texture precision required by a graphics processing unit (GPU); and a texture filter configured to perform texture filtering using the read texture having its format converted into the another format.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeongon Cho, Seok Kang, Soojung Ryu, Jeongae Park, Woong Seo, Sangheon Lee
  • Patent number: 10380479
    Abstract: Technical solutions are described to accelerate training of a multi-layer convolutional neural network. According to one aspect, a computer implemented method is described. A convolutional layer includes input maps, convolutional kernels, and output maps. The method includes a forward pass, a backward pass, and an update pass that each include convolution calculations. The described method performs the convolutional operations involved in the forward, the backward, and the update passes based on a first, a second, and a third perforation map respectively. The perforation maps are stochastically generated, and distinct from each other. The method further includes interpolating results of the selective convolution operations to obtain remaining results. The method includes iteratively repeating the forward pass, the backward pass, and the update pass until the convolutional neural network is trained. Other aspects such as a system, apparatus, and computer program product are also described.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leland Chang, Suyog Gupta
  • Patent number: 10380064
    Abstract: A neural network unit including a register programmable with a representation of a reciprocal value of a divisor and a plurality of neural processing units (NPU). Each NPU has an ALU, an accumulator, and a reciprocal multiplier unit. The ALU performs arithmetic and logical operations on a sequence of operands to generate a sequence of results and accumulates the sequence of results as an accumulated value into the accumulator. The reciprocal multiplier unit receives the representation of the reciprocal value and the accumulated value and in response generates a result that is the quotient of the accumulated value and the divisor.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: August 13, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: 10360177
    Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: July 23, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Syed Zohaib M. Gilani, Jiasheng Chen, QingCheng Wang, YunXiao Zou, Michael Mantor, Bin He, Timour T. Paltashev
  • Patent number: 10331347
    Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 25, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jayasree Sankaranarayanan, Dipan Kumar Mandal
  • Patent number: 10296345
    Abstract: Embodiments of the present invention are operable to communicate a list of important shaders and their current best-known compilations to remote client devices over a communications network. Client devices are allowed to produce modified shader compilations by varying optimizations. If a client device produces a modified compilation that beats an important shader's current best-known compilation, embodiments of the present invention can communicate this new best-known shader compilation back to a host computer system. Furthermore, embodiments of the present invention may periodically broadcast the new best-known shader compilation back to client devices for possible further optimization or for efficient rendering operations using the best-known shader compilation.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 21, 2019
    Assignee: Nvidia Corporation
    Inventor: Jeremy Zelsnack
  • Patent number: 10291939
    Abstract: When carrying out an intra-frame prediction process to generate an intra prediction image by using an already-encoded image signal in a frame, an intra prediction part 4 selects a filter from one or more filters which are prepared in advance according to the states of various parameters associated with the encoding of a target block to be filtered, and carries out a filtering process on a prediction image by using the filter. As a result, prediction errors which occur locally can be reduced, and the image quality can be improved.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: May 14, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akira Minezawa, Shunichi Sekiguchi, Kazuo Sugimoto
  • Patent number: 10289787
    Abstract: A PLD control program causes a computer to execute process including: outputting a configuration request for configuring a logic circuit in any of a plurality of areas where logic circuits are enabled to be reconfigured in a programmable logic device (hereinafter referred to as a PLD); and selecting, when a total size or number of a plurality of first logic circuits already configured in the plurality of areas and a second logic circuit newly configured in accordance with the configuration request exceeds a size or a number of logic circuits that are enabled to be configured in the plurality of areas, a logic circuit to be replaced with the second logic circuit, as a replacement target, from among the plurality of first logic circuits, based on a save and restore time needed to save and restore state data in the first logic circuits.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: May 14, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hidetoshi Matsumura
  • Patent number: 10283089
    Abstract: A display controller comprises an input stage 20 operable to read at least one input surface, a composition stage 28 operable to compose plural input surfaces to generate a composited output surface, an output stage 30 operable to provide the composited output surface to a display for display, a scaling engine 31 operable to scale a composited output surface generated by the composition stage 28, and a write-out stage 32 operable to write a composited and/or scaled output surface to external memory.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: May 7, 2019
    Assignee: Arm Limited
    Inventors: Damian Modrzyk, Pawel Duc, Piotr Chrobak, Michal Bogusz, Daren Croxford
  • Patent number: 10275289
    Abstract: First logical cores supported on physical processor cores in a computing system can be designated for execution of message-passing workers of a plurality of message workers while at least second logical cores supported on the physical processor cores can be designated for execution of procedural code such that resources of a physical processor core supporting the first logical core and the second logical core are shared between a first logical core and a second logical core. A database object in a repository can be assigned to one message-passing worker, which can execute operations on the database object while procedurally coded operations are processed using the second logical core on one or more of the plurality of physical processor cores while the first logical core executes the message-passing worker.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 30, 2019
    Assignee: SAP SE
    Inventor: Ivan Schreter
  • Patent number: 10268596
    Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline module to bypass a memory access for the first virtual page based on the first page table entry.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Abhishek R. Appu, Kiran C. Veernapu
  • Patent number: 10249073
    Abstract: Embodiments provide for a graphics processing apparatus comprising multiple compute nodes coupled to a communication layer, a rendering system executing on the multiple compute nodes, wherein the communication layer enables a distributed object executing on one of the multiple compute nodes to communicate with the rendering system, and a distributed framebuffer logic to subdivide a logical screen space for a frame into multiple regions and subdivide ownership of the regions among the multiple compute nodes.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: April 2, 2019
    Assignee: INTEL CORPORATION
    Inventors: Ingo Wald, Gregory P. Johnson
  • Patent number: 10244264
    Abstract: When carrying out an intra-frame prediction process to generate an intra prediction image by using an already-encoded image signal in a frame, an intra prediction part 4 selects a filter from one or more filters which are prepared in advance according to the states of various parameters associated with the encoding of a target block to be filtered, and carries out a filtering process on a prediction image by using the filter. As a result, prediction errors which occur locally can be reduced, and the image quality can be improved.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 26, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akira Minezawa, Shunichi Sekiguchi, Kazuo Sugimoto
  • Patent number: 10244233
    Abstract: When carrying out an intra-frame prediction process to generate an intra prediction image by using an already-encoded image signal in a frame, an intra prediction part 4 selects a filter from one or more filters which are prepared in advance according to the states of various parameters associated with the encoding of a target block to be filtered, and carries out a filtering process on a prediction image by using the filter. As a result, prediction errors which occur locally can be reduced, and the image quality can be improved.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 26, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akira Minezawa, Shunichi Sekiguchi, Kazuo Sugimoto
  • Patent number: 10242481
    Abstract: In general, techniques are described for visibility-based state updates in graphical processing units (GPUs). A device that renders image data comprising a memory configured to store state data and a GPU may implement the techniques. The GPU may be configured to perform a multi-pass rendering process to render an image from the image data. The GPU determines visibility information for a plurality of objects defined by the image data during a first pass of the multi-pass rendering process. The visibility information indicates whether each of the plurality of objects will be visible in the image rendered from the image data during a second pass of the multi-pass rendering process. The GPU then retrieves the state data from the memory for use by the second pass of the multi-pass rendering process in rendering the plurality of objects of the image data based on the visibility information.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: March 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Gruber, Ravi Somnath Jenkal
  • Patent number: 10237550
    Abstract: When carrying out an intra-frame prediction process to generate an intra prediction image by using an already-encoded image signal in a frame, an intra prediction part 4 selects a filter from one or more filters which are prepared in advance according to the states of various parameters associated with the encoding of a target block to be filtered, and carries out a filtering process on a prediction image by using the filter. As a result, prediction errors which occur locally can be reduced, and the image quality can be improved.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 19, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akira Minezawa, Shunichi Sekiguchi, Kazuo Sugimoto