Parallel Processors (e.g., Identical Processors) Patents (Class 345/505)
  • Patent number: 10409571
    Abstract: Apparatus and method for optimizing shader execution. For example, one embodiment of a graphics processing apparatus comprises: a plurality of execution units to execute shader programs; optimization detection circuitry and/or logic to identify one or more portions of shader program code to be optimized including one or more reduction operations which require read/write memory operations and associated barrier operations; and optimization circuitry and/or logic to optimize the shader program code by converting a plurality of the read/write memory operations to read/write register operations and removing one or more barrier operations to generate optimized shader program code; the execution units to execute the optimized shader program code.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventor: Marek Targowski
  • Patent number: 10410406
    Abstract: A method of rendering a three-dimensional point cloud in a two-dimensional display includes inputting the three-dimensional point cloud that includes three-dimensional coordinates of a set of points, creating a depth buffer for the three-dimensional point cloud that includes depth data for the set of points from a viewpoint location. The method further includes determining a foreground depth buffer by, for each respective pixel area of the two-dimensional display, determining a foreground depth by detecting a closest point to the viewpoint location among a subset of the set of points corresponding to the respective pixel area, and assigning a depth of the closest point as the foreground depth for the respective pixel area. The method further includes filtering the depth buffer to obtain a filtered depth buffer by removing points that are not in the foreground, and outputting the filtered depth buffer to the two-dimensional display.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 10, 2019
    Assignee: Trimble AB
    Inventors: Andrés Serna, Thomas Chaperon
  • Patent number: 10402415
    Abstract: An intelligently distributed stage data mining system is disclosed herein, including an intelligent central server, a first WLAN receiving and transmitting unit, a local cluster control unit, a second WLAN receiving and transmitting unit, a third WLAN receiving and transmitting unit, a self-adaptive multi-dimensional transmission processing unit, a plurality of ZigBee receiving and transmitting units and a distributed data extraction unit. The intelligent central server is used for sending data acquisition and stage correction instruction to the local cluster control unit, and for receiving the stage real-time data uploaded by the self-adaptive multi-dimensional transmission processing unit. The local cluster control unit is used for receiving the data acquisition instruction sent by the intelligent central server, and forwarding instructions to the self-adaptive multi-dimensional transmission processing unit.
    Type: Grant
    Filed: July 10, 2016
    Date of Patent: September 3, 2019
    Assignee: ZHEJIANG DAFENG INDUSTRY CO., LTD
    Inventors: Hua Feng, Qiyun Feng, Zhen Liu, Haihong Tian, Dong Wang, Lifeng Wu
  • Patent number: 10388033
    Abstract: A texture processor includes: a texture cache configured to store textures; a controller configured to determine a texture address corresponding to a requested texture among the stored textures and read a texture corresponding to the texture address from the texture cache; a format converter configured to convert a format of the read texture into another format, based on a degree of texture precision required by a graphics processing unit (GPU); and a texture filter configured to perform texture filtering using the read texture having its format converted into the another format.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeongon Cho, Seok Kang, Soojung Ryu, Jeongae Park, Woong Seo, Sangheon Lee
  • Patent number: 10380479
    Abstract: Technical solutions are described to accelerate training of a multi-layer convolutional neural network. According to one aspect, a computer implemented method is described. A convolutional layer includes input maps, convolutional kernels, and output maps. The method includes a forward pass, a backward pass, and an update pass that each include convolution calculations. The described method performs the convolutional operations involved in the forward, the backward, and the update passes based on a first, a second, and a third perforation map respectively. The perforation maps are stochastically generated, and distinct from each other. The method further includes interpolating results of the selective convolution operations to obtain remaining results. The method includes iteratively repeating the forward pass, the backward pass, and the update pass until the convolutional neural network is trained. Other aspects such as a system, apparatus, and computer program product are also described.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leland Chang, Suyog Gupta
  • Patent number: 10380064
    Abstract: A neural network unit including a register programmable with a representation of a reciprocal value of a divisor and a plurality of neural processing units (NPU). Each NPU has an ALU, an accumulator, and a reciprocal multiplier unit. The ALU performs arithmetic and logical operations on a sequence of operands to generate a sequence of results and accumulates the sequence of results as an accumulated value into the accumulator. The reciprocal multiplier unit receives the representation of the reciprocal value and the accumulated value and in response generates a result that is the quotient of the accumulated value and the divisor.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: August 13, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: 10360177
    Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: July 23, 2019
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Syed Zohaib M. Gilani, Jiasheng Chen, QingCheng Wang, YunXiao Zou, Michael Mantor, Bin He, Timour T. Paltashev
  • Patent number: 10331347
    Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 25, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jayasree Sankaranarayanan, Dipan Kumar Mandal
  • Patent number: 10296345
    Abstract: Embodiments of the present invention are operable to communicate a list of important shaders and their current best-known compilations to remote client devices over a communications network. Client devices are allowed to produce modified shader compilations by varying optimizations. If a client device produces a modified compilation that beats an important shader's current best-known compilation, embodiments of the present invention can communicate this new best-known shader compilation back to a host computer system. Furthermore, embodiments of the present invention may periodically broadcast the new best-known shader compilation back to client devices for possible further optimization or for efficient rendering operations using the best-known shader compilation.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 21, 2019
    Assignee: Nvidia Corporation
    Inventor: Jeremy Zelsnack
  • Patent number: 10289787
    Abstract: A PLD control program causes a computer to execute process including: outputting a configuration request for configuring a logic circuit in any of a plurality of areas where logic circuits are enabled to be reconfigured in a programmable logic device (hereinafter referred to as a PLD); and selecting, when a total size or number of a plurality of first logic circuits already configured in the plurality of areas and a second logic circuit newly configured in accordance with the configuration request exceeds a size or a number of logic circuits that are enabled to be configured in the plurality of areas, a logic circuit to be replaced with the second logic circuit, as a replacement target, from among the plurality of first logic circuits, based on a save and restore time needed to save and restore state data in the first logic circuits.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: May 14, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Hidetoshi Matsumura
  • Patent number: 10291939
    Abstract: When carrying out an intra-frame prediction process to generate an intra prediction image by using an already-encoded image signal in a frame, an intra prediction part 4 selects a filter from one or more filters which are prepared in advance according to the states of various parameters associated with the encoding of a target block to be filtered, and carries out a filtering process on a prediction image by using the filter. As a result, prediction errors which occur locally can be reduced, and the image quality can be improved.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: May 14, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akira Minezawa, Shunichi Sekiguchi, Kazuo Sugimoto
  • Patent number: 10283089
    Abstract: A display controller comprises an input stage 20 operable to read at least one input surface, a composition stage 28 operable to compose plural input surfaces to generate a composited output surface, an output stage 30 operable to provide the composited output surface to a display for display, a scaling engine 31 operable to scale a composited output surface generated by the composition stage 28, and a write-out stage 32 operable to write a composited and/or scaled output surface to external memory.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: May 7, 2019
    Assignee: Arm Limited
    Inventors: Damian Modrzyk, Pawel Duc, Piotr Chrobak, Michal Bogusz, Daren Croxford
  • Patent number: 10275289
    Abstract: First logical cores supported on physical processor cores in a computing system can be designated for execution of message-passing workers of a plurality of message workers while at least second logical cores supported on the physical processor cores can be designated for execution of procedural code such that resources of a physical processor core supporting the first logical core and the second logical core are shared between a first logical core and a second logical core. A database object in a repository can be assigned to one message-passing worker, which can execute operations on the database object while procedurally coded operations are processed using the second logical core on one or more of the plurality of physical processor cores while the first logical core executes the message-passing worker.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: April 30, 2019
    Assignee: SAP SE
    Inventor: Ivan Schreter
  • Patent number: 10268596
    Abstract: One embodiment provides for a graphics processor comprising a translation lookaside buffer (TLB) to cache a first page table entry for a virtual to physical address mapping for use by the graphics processor, the first page table entry to indicate that a first virtual page is cleared to a clear color and a graphics pipeline module to bypass a memory access for the first virtual page based on the first page table entry.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Abhishek R. Appu, Kiran C. Veernapu
  • Patent number: 10249073
    Abstract: Embodiments provide for a graphics processing apparatus comprising multiple compute nodes coupled to a communication layer, a rendering system executing on the multiple compute nodes, wherein the communication layer enables a distributed object executing on one of the multiple compute nodes to communicate with the rendering system, and a distributed framebuffer logic to subdivide a logical screen space for a frame into multiple regions and subdivide ownership of the regions among the multiple compute nodes.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: April 2, 2019
    Assignee: INTEL CORPORATION
    Inventors: Ingo Wald, Gregory P. Johnson
  • Patent number: 10244264
    Abstract: When carrying out an intra-frame prediction process to generate an intra prediction image by using an already-encoded image signal in a frame, an intra prediction part 4 selects a filter from one or more filters which are prepared in advance according to the states of various parameters associated with the encoding of a target block to be filtered, and carries out a filtering process on a prediction image by using the filter. As a result, prediction errors which occur locally can be reduced, and the image quality can be improved.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 26, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akira Minezawa, Shunichi Sekiguchi, Kazuo Sugimoto
  • Patent number: 10244233
    Abstract: When carrying out an intra-frame prediction process to generate an intra prediction image by using an already-encoded image signal in a frame, an intra prediction part 4 selects a filter from one or more filters which are prepared in advance according to the states of various parameters associated with the encoding of a target block to be filtered, and carries out a filtering process on a prediction image by using the filter. As a result, prediction errors which occur locally can be reduced, and the image quality can be improved.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 26, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akira Minezawa, Shunichi Sekiguchi, Kazuo Sugimoto
  • Patent number: 10242481
    Abstract: In general, techniques are described for visibility-based state updates in graphical processing units (GPUs). A device that renders image data comprising a memory configured to store state data and a GPU may implement the techniques. The GPU may be configured to perform a multi-pass rendering process to render an image from the image data. The GPU determines visibility information for a plurality of objects defined by the image data during a first pass of the multi-pass rendering process. The visibility information indicates whether each of the plurality of objects will be visible in the image rendered from the image data during a second pass of the multi-pass rendering process. The GPU then retrieves the state data from the memory for use by the second pass of the multi-pass rendering process in rendering the plurality of objects of the image data based on the visibility information.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: March 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Gruber, Ravi Somnath Jenkal
  • Patent number: 10237550
    Abstract: When carrying out an intra-frame prediction process to generate an intra prediction image by using an already-encoded image signal in a frame, an intra prediction part 4 selects a filter from one or more filters which are prepared in advance according to the states of various parameters associated with the encoding of a target block to be filtered, and carries out a filtering process on a prediction image by using the filter. As a result, prediction errors which occur locally can be reduced, and the image quality can be improved.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 19, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akira Minezawa, Shunichi Sekiguchi, Kazuo Sugimoto
  • Patent number: 10237551
    Abstract: When carrying out an intra-frame prediction process to generate an intra prediction image by using an already-encoded image signal in a frame, an intra prediction part 4 selects a filter from one or more filters which are prepared in advance according to the states of various parameters associated with the encoding of a target block to be filtered, and carries out a filtering process on a prediction image by using the filter. As a result, prediction errors which occur locally can be reduced, and the image quality can be improved.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 19, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akira Minezawa, Shunichi Sekiguchi, Kazuo Sugimoto
  • Patent number: 10217185
    Abstract: Methods and apparatus for providing interactive and customized experiences to clients of a media universe (MU) system. The MU system may leverage network-based computation resources and services, for example a streaming service, and a digital asset repository or repository service to dynamically provide customized and customizable experiences to clients. Clients may create or modify digital assets (e.g., 3D models of characters, objects, etc.), which may be stored to the asset repository. The MU system may dynamically render digital media content of the media universe (e.g., movies, games, etc.) that includes the clients' custom digital assets (characters, objects, backgrounds, etc.) inserted into appropriate locations, and stream the dynamically customized content to respective client devices. Effectively, a client layer of content is overlaid on a base or canonical layer of content within digital media of the media universe.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: February 26, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Christian Robert Cabanero, Matthew James Van Gorder, Thomas Richard Leonard, Eric Stephen Nylund, Adam C. F. MacDonald
  • Patent number: 10212439
    Abstract: To achieve a reduction in circuit size without causing output leakage from a frame memory. A frame memory temporarily stores a plurality of input video signals. A plurality of encoders perform compression coding on the video signals read from the frame memory. A control unit controls the operations of writing into and reading from the frame memory. The video signals are written into the frame memory at respective frame frequencies. The video signals are read from the frame memory at a common output frame frequency. The output frame frequency is assumed to be the highest frame frequency or more of the video signals.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: February 19, 2019
    Assignee: SONY CORPORATION
    Inventors: Kentaro Kojima, Nobuhiro Chiba, Hiroaki Seto, Shusuke Ozawa, Junya Sato, Kyohei Koyabu
  • Patent number: 10210028
    Abstract: A system and method for processing an input data stream. An input connector module receives an input data streams. A job thread is operatively connected to the received input data stream and produces an output data stream. An output connector module supplies an output data stream.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: February 19, 2019
    Assignee: Open Text SA ULC
    Inventors: Dennis D. Ladd, Anders Hermansson
  • Patent number: 10163183
    Abstract: Systems and methods for improving rendering performance of graphics processors are disclosed. A graphics processor may be configured to maintain access to multiple framebuffer sets stored in a non-transitory processor-readable medium. Two or more framebuffer sets may be configured to support different numbers of samples per pixel. The graphics processor may be further configured to determine whether a performance metric of a first frame processed using a first framebuffer set exceeded a threshold. The graphics processor may select a second framebuffer set with a reduced number of samples per pixel compared to the first framebuffer set when the performance metric of the first frame exceeded the threshold and process a second frame for display to a viewer utilizing the second framebuffer set.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: December 25, 2018
    Assignee: Rockwell Collins, Inc.
    Inventor: Jeanette M. Ling
  • Patent number: 10157442
    Abstract: A system and method runs a query using a GPU and generates a visualization of the query using the same GPU.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: December 18, 2018
    Assignee: OmniSci, Inc.
    Inventors: Todd L. Mostak, Christopher Root
  • Patent number: 10114648
    Abstract: An information processing device includes: a memory that stores a program; and a processor that executes the program to perform operations, wherein the operations includes: specifying a first register which is allocated to scalar data and satisfies a condition that a survival interval of the scalar data includes a survival interval of first data to which any register is not allocated; and allocating an empty area of the first register to the first data.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 30, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Shusaku Nakashima
  • Patent number: 10091530
    Abstract: As the quality and quantity of shared video content increases, video encoding standards and techniques are being developed and improved to reduce bandwidth consumption over telecommunication and other networks. One technique to reduce bandwidth consumption is intra-prediction, which exploits spatial redundancies within video frames. Each video frame may be segmented into blocks, and intra-prediction may be applied to the blocks. However, intra-prediction of some blocks may rely upon the completion (e.g., reconstruction) of other blocks, which can make parallel processing challenging. Provided are exemplary techniques for improving the efficiency and throughput associated with the intra-prediction of multiple blocks.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: October 2, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Ashish Mishra, Arindam Mohanta
  • Patent number: 10089113
    Abstract: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a system according to one embodiment comprises: a processor includes a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among two or more of the SMT cores; and at least one of the SMT cores including at least one level 2 (L2) cache circuit to store both instructions and data and communicatively coupled to the instruction cache circuit and the data cache circuit, a communication interconnect circuit including a peripheral component interconnect express (PCIe) circuit to communicatively couple one or more of the SMT cores to an accelerator device and a memory access circuit to identify an accelerator context save/restore region in a memory responsive to a context save/restore value, the accelerator context save/restore region to share an accelerator context state.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 2, 2018
    Assignee: INTEL CORPORATION
    Inventors: Oren Ben-Kiki, Ilan Pardo, Robert Valentine, Eliezer Weissmann, Dror Markovich, Yuval Yosef
  • Patent number: 10083037
    Abstract: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among the SMT cores, and at least one L2 cache circuit to store both instructions and data. The processor further comprises a communication interconnect circuit including a PCIe circuit to communicatively couple one or more of the SMT cores to an accelerator device, the PCIe circuit to provide the accelerator device access to resources of the processor including the at least one shared cache circuit. The processor further comprises a memory access circuit to identify an accelerator context save/restore region in a memory determined by an accelerator context save/restore value, the accelerator context save/restore region to store an accelerator context state.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 25, 2018
    Assignee: INTEL CORPORATION
    Inventors: Oren Ben-Kiki, Ilan Pardo, Robert Valentine, Eliezer Weissmann, Dror Markovich, Yuval Yosef
  • Patent number: 10055877
    Abstract: A graphics processing system processes primitive fragments using a rendering space which is sub-divided into tiles. The graphics processing system comprises processing engines configured to apply texturing and/or shading to primitive fragments. The graphics processing system also comprises a cache system for storing graphics data for primitive fragments, the cache system including multiple cache subsystems. Each of the cache subsystems is coupled to a respective set of one or more processing engines. The graphics processing system also comprises a tile allocation unit which operates in one or more allocation modes to allocate tiles to processing engines. The allocation mode(s) include a spatial allocation mode in which groups of spatially adjacent tiles are allocated to the processing engines according to a spatial allocation scheme, which ensures that each of the groups of spatially adjacent tiles is allocated to a set of processing engines which are coupled to the same cache subsystem.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: August 21, 2018
    Assignee: Imagination Technologies Limited
    Inventors: Jonathan Redshaw, Yoong Chert Foo
  • Patent number: 9990335
    Abstract: A method of providing transformed target points for integrating a component into an assembly includes collecting a set of component target points, collecting a set of assembly target points, identifying target points common to the set of component target points and the set of assembly target points; performing a specified number of Monte Carlo transformations of selected ones of the common target points to yield a set of transformed target points and vectors and an associated uncertainty value for each transformed target point and vector, and using certain ones of the transformed target points for integrating the component into the assembly based on the associated uncertainty value for each of the transformed target points.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 5, 2018
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Joseph Hayden, Manal A. Khreishi, Theodore A. Hadjimichael, Raymond J. Ohl
  • Patent number: 9986018
    Abstract: Method, system, and programs for data processing. In one example, a record is received. The record is separated into multiple partitions. Each partition is submitted to an iterative pipeline, wherein the iterative pipeline comprises two or more processing stages that are run in parallel and one of the multiple partitions passes through one of the two or more processing stages in one iteration. The multiple partitions are passed through two or more processing stages. The partitions that have passed through each of the two or more processing stages are merged.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: May 29, 2018
    Assignee: EXCALIBUR IP, LLC
    Inventors: Ajitsen Surendran, Satyadeep Sridharan Musuvathy
  • Patent number: 9978171
    Abstract: A method, system, and computer program product for controlling a sample mask from a fragment shader are disclosed. The method includes the steps of generating a fragment for each pixel that is covered, at least in part, by a primitive and determining coverage information for each fragment corresponding to the primitive. Then, for each fragment, the method includes the steps of generating a sample mask by a fragment shader, replacing the coverage information for the fragment with the sample mask, and writing, based on the sample mask, a result generated by the fragment shader to a memory. The method may be implemented on a parallel processing unit configured to implement, at least in part, a graphics processing pipeline.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 22, 2018
    Assignee: NVIDIA Corporation
    Inventors: Jeffrey Alan Bolz, Eric B. Lum, Rui Manuel Bastos
  • Patent number: 9972233
    Abstract: A display device including a display panel including scan lines, data lines, and first pixels disposed thereon, an expansion detecting unit configured to determine expansion of the display panel, a control unit configured to generate a control signal to correct an image signal depending on a degree of expansion when the display panel is determined to be expanded, a scan driver connected to the scan lines and configured to apply the control signal to the scan lines connected to the corresponding pixels depending on the control signal input from the control unit, and a data driver connected to the data lines and configured to apply the control signal to the data lines connected to the corresponding pixels depending on the control signal input from the control unit.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: May 15, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Kyoung Ho Lim
  • Patent number: 9965822
    Abstract: An image processing method and electronic device are provided. The image processing method includes receiving an instruction to process an input image, determining at least one image processing unit to be used to execute the instruction based on a state of an electronic device, dividing the input image and distributing the divided input image to the determined at least one image processing unit, and processing the divided image using the at least one image processing unit and combining the processed divided image.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: May 8, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Yong Lee, Hyeon-Jae Bak, Kwang-Kyu Park, Dong-Kook Park
  • Patent number: 9960907
    Abstract: Instructions and logic provide general purpose GF(28) SIMD cryptographic arithmetic functionality. Embodiments include a processor to decode an instruction for a SIMD affine transformation specifying a source data operand, a transformation matrix operand, and a translation vector. The transformation matrix is applied to each element of the source data operand, and the translation vector is applied to each of the transformed elements. A result of the instruction is stored in a SIMD destination register. Some embodiments also decode an instruction for a SIMD binary finite field multiplicative inverse to compute an inverse in a binary finite field modulo an irreducible polynomial for each element of the source data operand. Some embodiments also decode an instruction for a SIMD binary finite field multiplication specifying first and second source data operands to multiply each corresponding pair of elements of the first and second source data operand modulo an irreducible polynomial.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: May 1, 2018
    Assignee: Intel Corporation
    Inventor: Shay Gueron
  • Patent number: 9933945
    Abstract: Techniques for shrinking a filesystem backed by a volume identify slices in the volume to be evacuated in order to reach a target size, identify a target endpoint in the volume, and evacuate identified slices to available locations prior to the target endpoint. The same data is typically not moved from slice to slice multiple times.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 3, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Qi Mao, Jean-Pierre Bono, Ahsan Rashid, Xianlong Liu, Chang Yong Yu, Ruiling Dou, Alexander Mathews, Henry Fang, Gyanesh Kumar Choudhary
  • Patent number: 9927959
    Abstract: A system for processing user input includes an input device, an input processing unit, a high-latency subsystem, a low-latency subsystem, input processing unit software for generating signals in response to user inputs, and an output device. The low-latency subsystem receives the signals and generates low-latency output and the high-latency subsystem processes the signals and generates high-latency output.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: March 27, 2018
    Assignee: Tactual Labs Co.
    Inventors: Daniel Wigdor, Steven Leonard Sanders, Ricardo Jorge Jota Costa, Clifton Forlines
  • Patent number: 9918037
    Abstract: A multi-tier color look-up table (LUT) database system is provided. A first LUT can be stored in a database. First and second users can be granted access to the first LUT. The first and second users can have access to the first LUT for first and second periods of time, respectively. A second LUT can be stored in the database. The first user's access to the first LUT can be removed while the second user's access is maintained. The first and second users can be granted access to the second LUT. The first user can be granted a second access to the first LUT, and can have second access to the first LUT for a third period of time. The third period of time beginning after the end of the first period of time, with the second period of time overlapping with the first and third periods of time.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: March 13, 2018
    Assignee: THOMSON Licensing
    Inventors: Christian Ryan Zak, Arden A. Ash, James Desmond Ryan
  • Patent number: 9875138
    Abstract: A software engine for decomposing work to be done into tasks, and distributing the tasks to multiple, independent CPUs for execution is described. The engine utilizes dynamic code generation, with run-time specialization of variables, to achieve high performance. Problems are decomposed according to methods that enhance parallel CPU operation, and provide better opportunities for specialization and optimization of dynamically generated code. A specific application of this engine, a software three dimensional (3D) graphical image renderer, is described.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: January 23, 2018
    Assignee: Google LLC
    Inventors: Gavriel State, Nicolas Capens, Luther Johnson
  • Patent number: 9875519
    Abstract: Disclosed are apparatus and methods for rendering using a graphics processing component (GPC). A computing device can receive instructions for a GPC, including an instruction IA associated with a first portion of a canvas. An insertion position in an instruction buffer for instruction IA can be determined by: determining an instruction IB in the instruction buffer that is associated with a second portion of the canvas. If the first and second portions overlap, the insertion position can be based on an overlapping-instruction position of IB in the instruction buffer. Otherwise, if instructions IA and IB are similar, then the insertion position can be based on a second position of IB in the instruction buffer. Otherwise, the insertion position can be determined based on an ending position of the instruction buffer. Instruction IA can be inserted in the instruction buffer at the insertion position.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: January 23, 2018
    Assignee: Google LLC
    Inventors: Christopher Craik, Romain Guy
  • Patent number: 9841958
    Abstract: A high level programming language provides extensible data parallel semantics. User code specifies hardware and software resources for executing data parallel code using a compute device object and a resource view object. The user code uses the objects and semantic metadata to allow execution by new and/or updated types of compute nodes and new and/or updated types of runtime libraries. The extensible data parallel semantics allow the user code to be executed by the new and/or updated types of compute nodes and runtime libraries.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: December 12, 2017
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC.
    Inventor: Paul F. Ringseth
  • Patent number: 9824632
    Abstract: Circuits for programming a circuit with decreased programming time are provided. Such circuits include a storage device such as a capacitor for storing display information and for ensuring a driving device such as a driving transistor drives a light emitting device according to the display information. To increase programming time, the pixel circuits may be pre-charged or a biasing current may be applied to charge and/or discharge a data line and/or the driving device. Aspects of the present disclosure allow for the biasing current to drain partially through the storage device to allow the portion of the biasing current applied to the driving device to remain small while the data line discharges. Furthermore, the present disclosure provides display architectures and operation schemes for display arranged in segments each including a plurality of pixel circuits.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: November 21, 2017
    Assignee: Ignis Innovation Inc.
    Inventors: Gholamreza Chaji, Yaser Azizi, Maran Ran Ma, Arokia Nathan
  • Patent number: 9805447
    Abstract: When carrying out a second, higher level of anti-aliasing such as 8×MSAA, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4×MSAA, the rasterization stage 3, early Z (depth) and stencil test stage 4, late Z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: October 31, 2017
    Assignee: Arm Limited
    Inventors: Andreas Engh-halstvedt, Jorn Nystad, Frode Heggelund, Ronny Pedersen
  • Patent number: 9785871
    Abstract: A print control device includes drawing processing units, a sending unit, and a delivery unit. The drawing processing units perform a drawing process on a print instruction written in a page description language. The sending unit sends the entirety of a print instruction constituted by plural pages, to the drawing processing units. The delivery unit sequentially delivers processing requests each specifying a page to the drawing processing units. Each drawing processing unit performs a drawing process by converting the print instruction for a page specified by a delivered processing request into image data, and again performs, when processing requests are delivered in descending order of page, processing of the sent print instruction from the first page. The delivery unit delivers a processing request to a drawing processing unit to which processing requests are deliverable in ascending order of page.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: October 10, 2017
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Takeshi Torii
  • Patent number: 9785433
    Abstract: A processor includes a decode unit to decode a three source floating point addition instruction indicating a first source operand having a first floating point data element, a second source operand having a second floating point data element, and a third source operand having a third floating point data element. An execution unit is coupled with the decode unit. The execution unit, in response to the instruction, stores a result in a destination operand indicated by the instruction. The result includes a result floating point data element that includes a first floating point rounded sum. The first floating point rounded sum represents an additive combination of a second floating point rounded sum and the third floating point data element. The second floating point rounded sum represents an additive combination of the first floating point data element and the second floating point data element.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Roger Espasa, Guillem Sole, Manel Fernandez
  • Patent number: 9772852
    Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: September 26, 2017
    Assignee: Google Inc.
    Inventors: Albert Meixner, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein, Qiuling Zhu
  • Patent number: 9762919
    Abstract: Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: September 12, 2017
    Assignee: Apple Inc.
    Inventors: Guy Cote, Joseph P. Bratt, Timothy J. Millet, Shing I. Kong, Joseph J. Cheng
  • Patent number: 9754344
    Abstract: A graphics processing operation may include a set of render target operations, in which render targets are read and one or more intermediate computations are performed before generating final render target output. A method of performing graphics processing includes determining a dependency between render targets and defining a scheduling of tiles to reduce or eliminate a need to write intermediate computations to external memory. An interleaved order may be determined to maintain intermediate computations of dependent render target operations in an on-chip cache hierarchy.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: John W. Brothers, Santosh Abraham
  • Patent number: 9715864
    Abstract: A method for content displaying implemented by a mobile device that comprises a display, the method comprising detecting a user touch on the display via a graphical user interface, generating a lens animation effect in a region of content based on the user touch, wherein the lens animation effect at least magnifies the region of content shown on the display, and displaying the lens animation effect on the display adjacent to a location of the user touch.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: July 25, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventor: Anthony J. Mazzola