Abstract: A method for generating a distributed data scalable adaptive map-reduce framework for at least one multi-core cluster. The method includes partitioning a cluster into at least one computational group, determining at least one key-group leader within each computational group, performing a local combine operation at each computational group, performing a global combine operation at each of the at least one key-group leader within each computational group based on a result from the local combine operation, and performing a global map-reduce operation across the at least one key-group leader within each computational group.

Abstract: A parallel multicolor ILU factorization preconditioner processor and a method of computing an ILU preconditioning matrix. One embodiment of the preconditioning processor having parallel computing pipelines includes: (1) a graph coloring circuit operable to identify parallelisms in a sparse linear system, (2) an ILU computer configured to employ the parallel computing pipelines according to the parallelisms to: (2a) determine a sparsity pattern for an ILU preconditioning matrix, and (2b) compute non-zero elements of the ILU preconditioning matrix according to the sparsity pattern, and (3) a memory communicably couplable to the parallel computing pipelines and configured to store the ILU preconditioning matrix.

Abstract: Graphics processing units (GPUs) deployed in general purpose GPU (GPGPU) units are combined into a GPGPU cluster. Access to the GPGPU cluster is then offered as a service to users who can use their own computers to communicate with the GPGPU cluster. The users develop applications to be run on the cluster and a profiling module tracks the applications' resource utilization and can report it to the user and to a subscription server. The user can examine the report to thereby optimize the application or the cluster's configuration. The subscription server can interpret the report to thereby invoice the user or otherwise govern the users' access to the cluster.

Abstract: A new hardware architecture defines an indexing and encoding method for accelerating incoherent ray traversal. Accelerating multiple ray traversal may be accomplished by organizing the rays for minimal movement of data, hiding latency due to external memory access, and performing adaptive binning. Rays may be binned into coarse grain and fine grain spatial bins, independent of direction.

Abstract: A rendering processing apparatus and method using multiprocessing are disclosed. The rendering processing method includes dividing an application execution window into frames and generating a rendering processing command for rendering processing of an image on a frame basis by a pre-rendering manager, generating a rendering image on a frame basis according to the rendering processing command by a rendering manager, and storing the generated rendering image in a memory. The generation of a rendering processing command and the generation of a rendering image are performed in a plurality of threads.

Abstract: A SIMD parallel processor is described comprising an array comprising processing elements, associated data storage components and access means configured to enable access to at least one of the data storage components associated with at least one of the processing elements; a control processor; memory control means configured to enable addressing of at least one of the access means for the control processor; and connecting means configured to connect the memory control means to the access means.

Abstract: A rendering processing apparatus and method using multiprocessing are disclosed. The rendering processing method includes dividing an application execution window into frames and generating a rendering processing command for rendering processing of an image on a frame basis by a pre-rendering manager, generating a rendering image for a frame according to the generated rendering processing command by a rendering manager, and storing the generated rendering image in a memory. A task for generating a rendering processing command is divided into at least one task, a task for generating a rendering image is divided into at least one task, and the divided tasks can be processed simultaneously in a plurality of threads.

Abstract: A method includes providing an input port and/or an output port directly interfaced with a Graphics Processing Unit (GPU) of a data processing device further including a Central Processing Unit (CPU) to enable a corresponding reception of input data and/or rendering of output data therethrough. The method also includes implementing a voice/audio processing engine in the data processing device. Further, the method includes performing voice/audio related processing of the input data received through the input port and/or voice/audio related processing of data in the data processing device to realize the output data based on executing the voice/audio processing engine solely through the GPU.

Abstract: Techniques are disclosed relating to a multithreaded execution pipeline. In some embodiments, an apparatus is configured to assign a number of threads to an execution pipeline that is an integer multiple of a minimum number of cycles that an execution unit is configured to use to generate an execution result from a given set of input operands. In one embodiment, the apparatus is configured to require strict ordering of the threads. In one embodiment, the apparatus is configured so that the same thread access (e.g., reads and writes) a register file in a given cycle. In one embodiment, the apparatus is configured so that the same thread does not write back an operand and a result to an operand cache in a given cycle.

Abstract: A parallax representation unit in a displayed image processing unit uses a height map containing information on a height of an object for each pixel to represent different views caused by the height of the object. A color representation unit uses, for example, texture coordinate values derived by the parallax representation unit to render the image, shifting the pixel defined in the color map. The color representation unit uses the normal map that maintains normals to the surface of the object for each pixel to change the way that light impinges on the surface and represent the roughness accordingly. A shadow representation unit uses a horizon map, which maintains information for each pixel to indicate whether a shadow is cast depending on the angle relative to the light source, so as to shadow the image rendered by the color representation unit.

Abstract: A quality display is disclosed. Embodiments of the invention provide for the display of an indication of quality of a geographic survey. In some example embodiments, a survey grid corresponding to the geographic boundaries of a dynamically created survey area is displayed, where the displayed survey grid expands based on the geographic movement of survey participants. In additional embodiments, data representing the survey grid, cells of the survey grid, and a plurality of sub-cells into which each cell of the survey grid is divided is stored. In other embodiments, a numerical index corresponding to the quality of the survey in each cell of the survey grid is determined based on positioning information. In still other embodiments, a display attribute associated with each cell of the survey grid is adjusted in accordance with the numerical index.

Abstract: Frames are rendered by multiple graphics processors (GPUs), which may be heterogeneous. Graphics processors split the execution of the command in a push buffer of a frame. One GPU begins rendering a frame, and a second GPU takes over rendering that frame after the second GPU is done rendering a previous frame. The second GPU may then begin rendering a subsequent frame.

Abstract: A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.

Abstract: A technique to promote load balancing in parallel graphics rendering. In one embodiment, one or more threads are associated with one or more rendering tiles and scheduled in a balanced manner on one or more graphics processing resources.

Abstract: A system may include a memory that stores instructions and a processor to execute the instructions to create a first set of objects, describing a graphical scene, in a first data structure based on data relating to the graphical scene. The processor may create a second set of objects in a second data structure based on the first set of objects in the first data structure, where at least one object of the first set of objects is associated with at least one object of the second set of objects and one or more properties for an object of the second set of objects is based on information associated with the first data structure. The processor may modify the second set of objects and provide the modified second set of objects to a browser for rendering the graphical scene.

Abstract: An improved external controller with dual microcontrollers useable with an implantable medical device is disclosed. The external controller comprises a low speed (low frequency) microcontroller and a high speed (high frequency) microcontroller. The low speed microcontroller receives telemetry data from the medical device, converts data into graphical commands, and transmits commands to the high speed microcontroller. The high speed microcontroller interprets the graphical commands, retrieves images indicative of the commands from a storage device, and renders the images onto a display screen. The high speed microcontroller may also process more complicated data sent from the low speed microcontroller, and return the results to the low speed microcontroller to allow it to form the graphics command for the high speed microcontroller to execute.

Abstract: An apparatus for providing graphics processing. The apparatus includes a dual CPU socket architecture comprising a first CPU socket and a second CPU socket. The apparatus includes a plurality of GPU boards providing a plurality of GPU processors coupled to the first CPU socket and the second CPU socket, wherein each GPU board comprises two or more of the plurality of GPU processors. The apparatus includes a communication interface coupling the first CPU socket to a first subset of one or more GPU boards and the second CPU socket to a second subset of one or more GPU boards.

Abstract: In a raster stage of a graphics processor, a method for parallel fine rasterization. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level to generate a plurality of tiles of pixels. The titles are subsequently rasterized at a second level by allocating the tiles to an array of parallel second-level rasterization units to generate covered pixels. The covered pixels are then output for rendering operations in a subsequent stage of the graphics processor.

Abstract: One embodiment of the present invention sets forth a technique for performing low latency computation on a parallel processing subsystem. A low latency functional node is exposed to an operating system. The low latency functional node and a generic functional node are configured to target the same underlying processor resource within the parallel processing subsystem. The operating system stores low latency tasks generated by a user application within a low latency command buffer associated with the low latency functional node. The parallel processing subsystem advantageously executes tasks from the low latency command buffer prior to completing execution of tasks in the generic command buffer, thereby reducing completion latency for the low latency tasks.

Abstract: Provided herein is a method for implementing antialiasing including independently operating different portions of a graphics pipeline at different sampling rates in accordance with pixel color details.

Abstract: A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.

Abstract: A system, method and apparatus are disclosed, in which a processing unit is configured to perform secondary processing on graphics pipeline data outside the graphics pipeline, with the output from the secondary processing being integrated into the graphics pipeline so that it is made available to the graphics pipeline. A determination is made whether to use secondary processing, and in a case that secondary processing is to be used, a command stream, which can comprise one or more commands, is provided to the secondary processing unit, so that the unit can locate and operate on buffered graphics pipeline data. Secondary processing is managed and monitored so as to synchronize data access by the secondary processing unit with the graphics pipeline processing modules.

Abstract: A client-server computing system includes a server with a virtual display driver that marshals and transmits graphics application programming interface (API) functions to a client via a network. The virtual display driver includes a translation module that classifies graphics commands according to graphics library type and, if necessary, translates commands from one type to another such that the original command can be executed on the client. The translation module enables the server and the client to utilize different types of graphics libraries, such as the Direct3D API and the OpenGL API.

Abstract: A method for measuring shapes in thick multi-planar reformatted (MPR) digital images, including identifying a shape in a digital MPR image, scan-converting points corresponding to the identified shape on a starting plane of an MPR slab in an image volume from which the MPR was obtained to generate a plurality of starting points for the identified shape, calculating an end point in the MPR slab corresponding to each starting point, propagating a ray from each starting point to each corresponding end point, accumulating samples along each ray, and computing a desired measurement value from the accumulated samples after reaching the end point for all rays.

Abstract: Techniques for coalescing graphics operations are described. In at least some embodiments, multiple graphics operations can be generated to be applied to a graphical element, such as a graphical user interface (GUI). The graphics operations can be coalesced into a single renderable graphics operation that can be processed and rendered.

Abstract: An operating system that includes an image processing framework as well as a job management layer is provided. The image processing framework is for performing image processing operations and the job management layer is for assigning the image processing operations to multiple concurrent computing resources. The computing resources include several processing units and one or more direct memory access (DMA) channels for concurrently rendering image data and transferring image data between the processing units.

Abstract: Concurrent display of graphic content on multiple displays is described. A frame of graphic content to be displayed on multiple displays can be written to a single memory location. Previously written graphic content can be read to multiple displays having misaligned synchronization signals and new graphic content can be written to a different memory location concurrently.

Abstract: A multi core graphic processing device includes a first graphic core that processes a first segment of a graphic frame divided into a plurality of segments and generates a first local decision that defines a scene property of the first segment, a second graphic core that processes a second segment of the graphic frame different from the first segment and generates a second local decision that defines a scene property of the second segment, and a global decision unit that receives the first local decision and the second local decision from the first graphic core and the second graphic core, and selects one of the received first local decision and second local decision as a global decision.

Abstract: Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software interface which collectively allow for both data-based and task-based parallelism in executing a flood-fill process. The hardware primitive is defined to do the flood-fill function and is scalable and may be implemented with a bitwise definition that can be tuned to meet power/performance targets, in some embodiments. In executing a flood-fill operation, and in accordance with an example embodiment, the software interface produces parallel threads and issues them to processing elements, such that each of the threads can run independently until done. Each processing element in turn accesses a flood-fill hardware primitive, each of which is configured to flood a seed inside an N×M image block. In some cases, processing element commands to the flood-fill hardware primitive(s) can be queued and acted upon pursuant to an arbitration scheme.

Abstract: There are provided a method of generating a terrain model and a device using the same. The method of generating a terrain model includes dividing a primitive terrain model into a plurality of partial terrain sections based on a predetermined criterion, assigning the plurality of partial terrain sections to a multiprocessor, and generating a final terrain model by performing a terrain transformation simulation of the plurality of partial terrain sections through parallel processing based on the multiprocessor. Therefore, it is possible to rapidly generate a realistic terrain model.

Abstract: A measuring device for measuring a response speed of a display panel is provided. The measuring device includes a microcontroller and at least one photo sensor. The microcontroller provides a control command, according to which a display controller of the display panel provides test pattern to the display panel. The photo sensor senses a test frame displayed corresponding to the test pattern by the display panel, and provides a corresponding sensing signal associated with brightness and a response signal. According to the response signal, the response speed of the display panel is calculated.

Abstract: The disclosed embodiments provide a system that facilitates seamlessly switching between graphics-processing units (GPUs) to drive a display. In one embodiment, the system receives a request to switch from using a first GPU to using a second GPU to drive the display. In response to this request, the system uses a kernel thread which operates in the background to configure the second GPU to prepare the second GPU to drive the display. While the kernel thread is configuring the second GPU, the system continues to drive the display with the first GPU and a user thread continues to execute a window manager which performs operations associated with servicing user requests. When configuration of the second GPU is complete, the system switches the signal source for the display from the first GPU to the second GPU.

Abstract: An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols.

Abstract: A method and an apparatus for notifying a display driver to update a display with a graphics frame including multiple graphics data rendered separately by multiple graphics processing units (GPUs) substantially concurrently are described. Graphics commands may be received to dispatch to each GPU for rendering corresponding graphics data. The display driver may be notified when each graphics data has been completely rendered respectively by the corresponding GPU.

Abstract: A graphical processing unit having an implementation of a hierarchical hash table thereon, a method of establishing a hierarchical hash table in a graphics processing unit and GPU computing system are disclosed herein. In one embodiment, the graphics processing unit includes: (1) a plurality of parallel processors, wherein each of the plurality of parallel processors includes parallel processing cores, a shared memory coupled to each of the parallel processing cores, and registers, wherein each one of the registers is uniquely associated with one of the parallel processing cores and (2) a controller configured to employ at least one of the registers to establish a hierarchical hash table for a key-value pair of a thread processing on one of the parallel processing cores.

Abstract: Methods and apparatuses to reduce the number of IO requests to memory when executing a program that iteratively processes contiguous data are provided. A first set of data elements may be loaded in a first register and a second set of data elements may be loaded in a second register. The first set of data elements and the second set of data elements can be used during the execution of a program to iteratively process the data elements. For each of a plurality of iterations, a corresponding set of data elements to be used during the execution of an operation for the iteration may be selected from the first set of data elements stored in the first register and the second set of data elements stored in the second register. In this way, the same data elements are not re-loaded from memory during each iteration.

Abstract: In some aspects, systems and methods provide for forming groupings of a plurality of independently-specified computation workloads, such as graphics processing workloads, and in a specific example, ray tracing workloads. The workloads include a scheduling key, which is one basis on which the groupings can be formed. Workloads grouped together can all execute from the same source of instructions, on one or more different private data elements. Such workloads can recursively instantiate other workloads that reference the same private data elements. In some examples, the scheduling key can be used to identify a data element to be used by all the workloads of a grouping. Memory conflicts to private data elements are handled through scheduling of non-conflicted workloads or specific instructions and/or deferring conflicted workloads instead of locking memory locations.

Abstract: Embodiments of the present invention provide graphic processing techniques and configurations including an apparatus comprising a storage medium having stored therein a table comprising information about respective positions and sizes of a number of rectangular blocks, the rectangular blocks to substantially form at least one plane having an arbitrary shape object, and at least one overlay engine operatively coupled with the table and associated with the at least one plane to request the information about the respective positions and the sizes of the number of rectangular blocks to provide graphics overlay of the arbitrary shape object. Other embodiments may be described and/or claimed.

Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors, including if the die has a defective component. An indication of the defective functional component identification is received. A determination is made if the defective functional component is one of a plurality of similar functional components that can provide the same functionality. The other similar components can be examined to determine if they are parallel components to the defective functional component. The defective functional component is disabled if it is one of the plurality of similar functional components and another component can handle the workflow that would otherwise be assigned to the defective component. Workflow is diverted from the disabled component to other similar functional components.

Abstract: Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes physical memory, at least two distinct graphics-processing devices, and a bus coupled to the physical memory and the at least two graphics-processing devices. A virtual graphics processing component enables each of at least two graphics-processing operations to be executed, in parallel, by a corresponding one of the at least two distinct graphics-processing devices, which operate in the same memory surface at the same time.

Abstract: An apparatus includes a plurality of image processing circuits. Each image processing circuit generates an image frame corresponding to a single large surface. The first image processing circuit provides a portion of the generated image frame for a first display or plurality of displays and provides a remaining portion of the image frame to the remaining image processing circuits. The next image processing circuits provides the remaining portion of the image frame for the next plurality of displays.

Abstract: A print image processing system includes plural logical page interpretation units, a dual interpretation unit, a cache memory, an assignment unit, and a print image data generation unit. The logical page interpretation units interpret assigned logical pages in input print data in parallel. The dual interpretation unit interprets an assigned logical page in the print data or an element to be cached which is included in the logical page. The cache memory stores interpretation results of elements to be cached. The assignment unit assigns logical pages to the dual interpretation unit and the logical page interpretation units. The print image data generation unit generates print image data for the logical pages using the interpretation results output from the logical page interpretation units or the dual interpretation unit and the interpretation results stored in the cache memory. The print image data generation unit supplies the print image data to a printer.

Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

Abstract: A control method for bi-stable displaying is provided, using queues for storing coordinates to achieve pipeline parallel processing on display data, thereby increasing display speed. In a preceding stage of the display process, because a plurality of queues may be used for temporarily storing part of the display data which is then reconstructed into complete display data to update a current frame buffer, comparing pixel data and generating driving data can be simultaneously preformed upon a plurality of line segments. Moreover, in a succeeding stage of the display process, a similar process may be performed to update a previous frame buffer, so access time can be reduced and errors caused by overlapping image blocks can also be avoided. Furthermore, the method may be also applied to a timing controller and a bi-stable display device.

Abstract: The present disclosure relates to a system for routing data across a multicore processing network. The system includes a multicore processing array having a plurality of processing cores, a memory for storing data relating to an object being modeled, the data being associated with coordinate information relating to the object within a coordinate system, and a controller for routing the data from the memory to one or more of the plurality of processing cores of the multicore processing array based on the coordinate information associated with the data. The present disclosure also relates to a method for routing data across a multicore processing network and a computer accessible medium having stored thereon computer executable instructions for performing a procedure for routing data across a multicore processing network.

Abstract: In a graphics processing device, a plurality of processors write fragment shading results for order-dependent data to a buffer, according to the order in which the data is received. Fragment shading results for order-neutral data is written to the buffer one batch at a time. The order-dependent data comprises spatially overlapping data. Order-neutral data may not overlap. A scheduler controls the order of reception of one batch of data at a time by the processors. The order for receiving the order-dependent data may be determined. The plurality of processors may process the data in parallel. A writing order for writing results to a buffer from the processing in parallel, may be enforced. A portion of the processors may be instructed to wait before writing results to the buffer in a specified order. Processors signal when writing results to the buffer is complete.

Abstract: A processing unit that includes a plurality of virtual engines and a shader core. The plurality of virtual engines is configured to (i) receive, from an operating system (OS), a plurality of tasks substantially in parallel with each other and (ii) load a set of state data associated with each of the plurality of tasks. The shader core is configured to execute the plurality of tasks substantially in parallel based on the set of state data associated with each of the plurality of tasks. The processing unit may also include a scheduling module that schedules the plurality of tasks to be issued to the shader core.

Abstract: A method for rendering parametric surface patches on a display screen includes receiving, at a processing unit, a computer-implemented representation of a first parametric surface patch, wherein the first parametric surface patch is a portion of a three-dimensional computer-implemented model that is desirably displayed at a first viewing perspective on the display screen. The first parametric patch is subdivided in the parameter domain to generate a plurality of subpatches, which are stored as quadtree coordinates in a memory. Thereafter, at least one pixel on the display screen is rendered based at least in part upon the quadtree coordinates in the memory.

Abstract: A graphics processing chip includes multiple graphics pipeline cores and multi-pipeline core logic circuitry to process graphic data streams received from a processor and to drive multiple GPUs on the multiple graphics pipeline cores.

Abstract: A processing system, a method of carrying out sample-based rendering (such as true or quasi-Monte Carlo rendering) in a multi- or many-core processor processing system and a graphics processing unit (GPU) incorporating the processing system or the method. In one embodiment, the processing system includes: (1) a sample-space distributor operable to distribute a first subset of samples for a pixel of an image to a first compute core for sample-based rendering therewith and a second subset of samples for the pixel to a second compute core for the sample-based rendering therewith, the second subset differing from the first subset and (2) a sample-space combiner associated with the sample-space distributor and operable to combine results of the sample-based rendering.