Graphic Command Processing Patents (Class 345/522)
  • Patent number: 10699367
    Abstract: Methods, systems, and computer-readable media for placement optimization for virtualized graphics processing are disclosed. A provider network comprises a plurality of instance locations for physical compute instances and a plurality of graphics processing unit (GPU) locations for physical GPUs. A GPU location for a physical GPU or an instance location for a physical compute instance is selected in the provider network. The GPU location or instance location is selected based at least in part on one or more placement criteria. A virtual compute instance with attached virtual GPU is provisioned. The virtual compute instance is implemented using the physical compute instance in the instance location, and the virtual GPU is implemented using the physical GPU in the GPU location. The physical GPU is accessible to the physical compute instance over a network. An application is executed using the virtual GPU on the virtual compute instance.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 30, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Nicholas Patrick Wilt, Ashutosh Tambe
  • Patent number: 10699463
    Abstract: In response to movement of an underlying structure, motion of complex objects connected to that structure may be simulated relatively quickly and without requiring extensive processing capabilities. A skeleton extraction method is used to simplify the complex object. Tracking is used to track the motion of the underlying structure, such as the user's head in a case where motion of hair is being simulated. Thus, the simulated motion is driven in response to the extent and direction of head or facial movement. A mass-spring model may be used to accelerate the simulation in some embodiments.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Shaohui Jiao, Qiang Li, Wenlong Li
  • Patent number: 10672368
    Abstract: Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: June 2, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Ryan Scott Haraden, Tolga Ozguner, Adam James Muff, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung, Miguel Comparan
  • Patent number: 10649956
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: May 12, 2020
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Guei-Yuan Lueh, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Tomer Bar-On, Andrew T. Lauritzen, Hugues Labbe, John G. Gierach, Gabor Liktor
  • Patent number: 10649864
    Abstract: Various systems and methods are provided for capturing and storing state information and other data being used by a web application. For example, one method involves capturing the data and state information from a web application either on demand, on schedule, or on the occurrence of an event; storing the captured information in a persistent memory; subsequent to a closing of the web application, receiving an indication that the web application has been re-opened; presenting one or more options to a user, whereby the user can select a previous version to which the web application should be restored; and using the captured information to restore the web application data and user interface to a state indicated by the selected version.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 12, 2020
    Assignee: Veritas Technologies LLC
    Inventors: Mirang Dipak Parikh, Rashmi Vijayvargiya
  • Patent number: 10643656
    Abstract: A printing apparatus includes a printer configured to print a character on a printing medium, a display including multiple individual display areas arranged in a particular order, and a controller. The controller is configured to display one of a character image and an icon on each of the multiple individual display areas, the character image being an image indicating the character, the icon corresponding to a control code indicating a process related to a print control of the character, and control printing performed by the printer based on a target code and a target character, the target code being a control code corresponding to the icons displayed in the individual display areas, the target characters being characters indicated by the character images displayed in the individual display areas.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 5, 2020
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Minako Ishida
  • Patent number: 10621088
    Abstract: An apparatus, method and machine-readable storage medium to improve memory access performance between shared local memory and system global memory are described. The method comprises grouping two or more work groups to form a super workgroup, and positioning a portion of a memory space into one or more super shared local memories (Super SLMs), wherein the memory space which is shared within the super workgroup forms at least one Super SLM of the one or more Super SLMs. The apparatus comprises: a plurality of execution units; a cache memory having a portion which operates as a shared local memory (SLM), which is shared with the plurality of execution units, at least one of which operates on a work group of a sub-slice, wherein the SLM is shared within the work group; and at least one Super-SLM for providing shared memory accessible by different work groups in the sub-slice, wherein the at least one of the execution units operates on the different work groups.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Jianghong Du, Yong Jiang, Lei Shen, Yuanyuan Li
  • Patent number: 10617955
    Abstract: A method for testing game design assets in a service provider environment may include receiving from a client computing device, a request for testing at least one game design asset. The at least one game design asset associated with the received request may be acquired. The at least one game design asset may be tested in a plurality of available test pipelines. The plurality of available test pipelines are implemented on at least one server computer within the service provider environment. Compliance of the at least one game design asset with one or more game engines associated with the plurality of available test pipelines may be determining during the testing. Compatibility information is generated based on the determined compliance, and the test report is communicated to the client computing device.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: April 14, 2020
    Assignee: Amazon Technologies, Inc.
    Inventor: Kevin Kalima Ashman
  • Patent number: 10614542
    Abstract: The present invention provides a GPU resource allocation method. A to-be-distributed kernel program in a kernel status register table is identified by using a global logic controller (201). The global logic controller searches in an SM status register table for an SM that can run at least one complete block, and the SM status register table is configured to store a quantity of available resources in each SM (202). When the global logic controller does not find the SM that can run at least one complete block, the SM status register table is searched for a first SM, and the first SM is an SM that can run at least one warp (203). When the global logic controller finds the first SM, a block in the to-be-distributed kernel program is distributed to the first SM (204).
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 7, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xusheng Zhan, Cong Wang, YunGang Bao
  • Patent number: 10606572
    Abstract: A flow preparation assisting apparatus calculates a difference between one or more flow data sets and a template flow data set having been a base of the one or more flow data sets, and calculates a dependency relation between node attributes for a template flow indicated by the template flow data set, from the calculated difference. The flow preparation assisting apparatus issues a notification according to the calculated dependency relation.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 31, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Naganuma, Hideki Nakamura, Toshio Nishida
  • Patent number: 10589171
    Abstract: Systems and methods for conservation of bandwidth and improved user experience via enhanced streaming of video games. An example method includes receiving a request to remotely play a video game, the video game being executed by the system and streamed to a user device for presentation. The video game is executed, and rendered image frames are generated. Geometry data associated with the rendered image frames is generated, with the geometry data representing locations of geometric elements that form geometry utilized, by the video game, to generate the rendered image frames. The rendered image frames are encoded into a gameplay stream. A first stream comprising the encoded gameplay stream and a second stream comprising the geometry data are provided to the user device. The user device is configured to perform post-processing effects on the rendered image frames encoded in the gameplay stream prior to display on the user device.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 17, 2020
    Assignee: Electronic Arts Inc.
    Inventor: Max Burke
  • Patent number: 10586304
    Abstract: Systems, methods, and computer readable media to promote a graphics context when rendering a digital image content with dynamic ranges and/or color gamut outside the current graphics context. Various embodiments render digital image content based on a graphics context that corresponds to an initial image rendering format. During the rendering process a determination is made that indicates the quality of the digital image content exceeds the graphics context's initial capabilities. The various embodiments can select an updated image rendering format based on the quality of the digital image and expand the graphic context's capabilties to correspond with the updated image rendering format.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: March 10, 2020
    Assignee: Apple Inc.
    Inventors: Luke S. Wallis, Ian C. Hendry, Hans Werner Neubrand
  • Patent number: 10567788
    Abstract: Systems and methods for integrated graphics rendering are disclosed. In certain embodiments, the systems and methods utilize a graphics engine, a video encoding engine, and remote client coding engine to render graphics over a network. The systems and methods involve the generation of per-pixel motion vectors, which are converted to per-block motion vectors at the graphics engine. The graphics engine injects these per-block motion vectors into a video encoding engine, such that the video encoding engine may convert those vectors into encoded video data for transmission to the remote client coding engine.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 18, 2020
    Assignee: ZeniMax Media Inc.
    Inventor: Michael Kopietz
  • Patent number: 10559125
    Abstract: A method and apparatus to construct a bounding volume hierarchy (BVH) tree includes: generating 2-dimensional (2D) tiles including primitives; converting the 2D tiles into 3-dimensional (3D) tiles; and constructing the BVH tree based on the 3D tiles.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ankur Deshwal, Vikash Kumar, Keshavan Varadarajan, Parikshit Kolipaka, Soma Kohli
  • Patent number: 10552959
    Abstract: A method and system is provided for storing and analyzing clinical imaging data. The method includes obtaining patient images from two or more modalities, registering the images, determining position information of a voxel, calculating and assigning a quality metric for the voxel, storing the voxel information and at least one searchable header as imaging data in a computer memory, and modifying or maintaining treatment based on the imaging data. The system includes a memory and a processor, the processor configured to obtain images from two or more modalities, register and store the image set in memory, calculate a quality metric for a voxel in the image set, store the voxel quality metric with the image set in the memory, and modify or maintain treatment based on the calculated qualitative metric.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 4, 2020
    Inventors: Cameron Anthony Piron, Murugathas Yuwaraj
  • Patent number: 10549203
    Abstract: Systems and methods for synchronizing game play of a video game include detecting selection of a video game for game play at a game server. In response, an instance of the video game is executed at the game server. The execution causes the game play to be provided to a game client for rendering on a main portion of a display screen of the game client. A pre-recorded video associated with the video game is provided for rendering in a second portion of the display screen while the game play is being rendered on the main portion of the display screen. The pre-recorded video rendering in the second portion is dynamically synchronized with the game play of the video game rendering in the main portion so that a game scene rendering in the pre-recorded video matches to a game scene of the game play rendering in the main portion of the display screen.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: February 4, 2020
    Assignee: Sony Interactive Entertainment America LLC
    Inventor: David Perry
  • Patent number: 10537799
    Abstract: Systems and methods for conservation of bandwidth and improved user experience via enhanced streaming of video games. An example method includes receiving a request to remotely play a video game, the video game being executed by the system and streamed to a user device for presentation. The video game is executed, and rendered image frames are generated. Geometry data associated with the rendered image frames is generated, with the geometry data representing locations of geometric elements that form geometry utilized, by the video game, to generate the rendered image frames. The rendered image frames are encoded into a gameplay stream. A first stream comprising the encoded gameplay stream and a second stream comprising the geometry data are provided to the user device. The user device is configured to perform post-processing effects on the rendered image frames encoded in the gameplay stream prior to display on the user device.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 21, 2020
    Assignee: Electronic Arts Inc.
    Inventor: Max Burke
  • Patent number: 10540280
    Abstract: Techniques for performing cache invalidates and write-backs in an accelerated processing device (e.g., a graphics processing device that renders three-dimensional graphics) are disclosed. The techniques involve receiving requests from a “master” (e.g., the central processing unit). The techniques involve invalidating virtual-to-physical address translations in an address translation request. The techniques include splitting up the requests based on whether the requests target virtually or physically tagged caches. Addresses for the portions of a request that target physically tagged caches are translated using invalidated virtual-to-physical address translations for speed. The split up request is processed to generate micro-transactions for individual caches targeted by the request. Micro-transactions for physically and virtually tagged caches are processed in parallel. Once all micro-transactions for a request have been processed, the unit that made the request is notified.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 21, 2020
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Mark Fowler, Jimshed Mirza, Anthony Asaro
  • Patent number: 10521874
    Abstract: An apparatus and method are described for executing workloads without host intervention. For example, one embodiment of an apparatus comprises: a host processor; and a graphics processor unit (GPU) to execute a hierarchical workload responsive to one or more commands issued by the host processor, the hierarchical workload comprising a parent workload and a plurality of child workloads interconnected in a logical graph structure; and a scheduler kernel implemented by the GPU to schedule execution of the plurality of child workloads without host intervention, the scheduler kernel to evaluate conditions required for execution of the child workloads and determine an order in which to execute the child workloads on the GPU based on the evaluated conditions; the GPU to execute the child workloads in the order determined by the scheduler kernel and to provide results of parent and child workloads to the host processor following execution of all of the child workloads.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Jayanth N. Rao, Pavan K. Lanka, Michal Mrozek
  • Patent number: 10522114
    Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Jeffery S. Boles, Hema C. Nalluri, Balaji Vembu, Michael Apodaca, Altug Koker, Lalit K. Saptarshi
  • Patent number: 10515118
    Abstract: Processing a data flow graph of a hybrid flow can include a data structure to store metadata for each of a plurality of nodes of a data flow graph of a hybrid flow, processing the data flow graph of the hybrid flow, and defining metadata in the data structure for a particular node affected during processing of the data flow graph of the hybrid flow.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: December 24, 2019
    Assignee: MICRO FOCUS LLC
    Inventors: Alkiviadis Simitsis, William Kevin Wilkinson, Petar Jovanovic
  • Patent number: 10496548
    Abstract: One embodiment facilitates a user-space storage I/O stack. During operation, the system generates, by a file system in the user-space, a logical block address associated with an I/O request which indicates data to be read or written. The system generates, by a flash translation layer module in the user-space, a physical block address corresponding to the logical block address, wherein the flash translation layer module is located between the file system and a block device driver in the user-space. The system estimates a latency associated with executing the I/O request. In response to determining that the estimated latency is greater than or equal to a predetermined threshold, and that the I/O request is a read request, the system reads the requested data from a location other than the physical block address.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: December 3, 2019
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 10475152
    Abstract: Techniques are disclosed relating to managing dependencies in a compute control stream that specifies operations to be performed on a programmable shader (e.g., of a graphics unit). In some embodiments, the compute control stream includes commands and kernels. In some embodiments, dependency circuitry is configured to maintain dependencies such that younger kernels are allowed to execute ahead of a type of cache-related command (e.g., a command that signals a cache flush and/or invalidate). Disclosed circuitry may include separate buffers for commands and kernels, command dependency circuitry, and kernel dependency circuitry. In various embodiments, the disclosed architecture may improve performance in a highly scalable manner.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: November 12, 2019
    Assignee: Apple Inc.
    Inventors: Andrew M. Havlir, Jeffrey T. Brady
  • Patent number: 10467723
    Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Brendon Lewis Johnson, Andrew Evan Gruber, Jay Chunsup Yun, Rahul Gulati, Donghyun Kim, Alex Kwang Ho Jong
  • Patent number: 10453429
    Abstract: Methods, apparatus, and articles of manufacture to provide extended graphics processing capabilities are disclosed. A disclosed example method involves sending a display panel parameter to a shared library module. The display panel parameter is sent by a programmable driver interface in communication between the shared library module and a graphics hardware device driver. The shared library module includes a first graphics processing capability. The graphics hardware device driver includes a second graphics processing capability different from the first graphics processing capability. The example method also involves performing a render operation via the programmable driver interface on a frame buffer based on the first graphics processing capability. The first graphics processing capability is received at the programmable driver interface from the shared library module based on the display panel parameter. The frame buffer is output to a display.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Sameer Kp, Selvakumar Panneer, Susanta Bhattacharjee, Mrinalini Attaluri
  • Patent number: 10446071
    Abstract: An electronic device includes a processor configured to generate a slice update map indicating a location of at least one updated slice having a data change in frame data including a plurality of slices; and a display controller configured to extract frame data of the at least one updated slice from a memory based on the slice update map and transfer the frame data to a display driver.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hoon Lee, Jong-Ho Roh, Sang-Hoon Ha, Sung-Hoo Choi, Hoon-Mo Yang, Seong-Woon Kim, Jong-Hyup Lee, Ha-Na Yang
  • Patent number: 10437541
    Abstract: This disclosure pertains to the operation of graphics systems and to a variety of architectures for design and/or operation of a graphics system spanning from the output of an application program and extending to the presentation of visual content in the form of pixels or otherwise. In general, many embodiments of the invention contemplate a high level graphics framework to receive graphic requests from an application. The graphics request is analyzed by the high-level framework and sorted into groups of command statements for execution. The command statements are sorted to cause the most efficient processing by the underlying hardware and the groups are submitted separately to a GPU using a low-level standard library that facilitates close control of the hardware functionality.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: October 8, 2019
    Assignee: Apple Inc.
    Inventors: Nathaniel C. Begeman, Sean M. Gies, Andrew M. Pangborn
  • Patent number: 10430915
    Abstract: One or more copy commands are scheduled for locating one or more pages of data in a local memory of a graphics processing unit (GPU) for more efficient access to the pages of data during rendering. A first processing unit that is coupled to a first GPU receives a notification that an access request count has reached a specified threshold. The first processing unit schedules a copy command to copy the first page of data to a first memory circuit of the first GPU from a second memory circuit of the second GPU. The copy command is included within a GPU command stream.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: October 1, 2019
    Assignee: NVIDIA Corporation
    Inventors: Andrei Khodakovsky, Kirill A. Dmitriev, Rouslan L. Dimitrov, Tzyywei Hwang, Wishwesh Anil Gandhi, Lacky Vasant Shah
  • Patent number: 10417134
    Abstract: A cache memory may be configured to store a plurality of lines, where each line includes data and metadata. A circuit may be configured to determine a respective number of edges associated with each vertex of a plurality of vertices included in a graph data structure, and sort the graph data structure using the respective number of edges. The circuit may be further configured to determine a reuse value for a particular vertex of the plurality of vertices using a respective address associated with the particular vertex in the sorted graph, and store data and metadata associated with the particular vertex in a particular line of the plurality of lines in the cache memory.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: September 17, 2019
    Assignee: Oracle International Corporation
    Inventors: Priyank Faldu, Jeffrey Diamond, Avadh Patel
  • Patent number: 10417023
    Abstract: A GPU simulation method. An instruction sequence of a client GPU is intercepted in a kernel state simulator based on system virtualization and GPU using principle, and a mechanism is selected according to user configuration to accomplish simulation of the client GPU. In first mechanism, instruction translation is accomplished on low-level semantics based on a binary translation technology, and instructions are executed on a host GPU; in second mechanism, instruction conversion is accomplished using an existing GPU software stack, and instructions are executed on host GPU. The method provides an efficient simulated GPU for a virtual machine based on a host machine physical GPU, and solves the problem of slow GPU simulation. Based on a system virtualization technology and by virtue of a convenient condition provided by an existing GPU software stack, the GPU simulation speed is improved, and the implementation difficulty and complexity of the method are effectively controlled.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: September 17, 2019
    Assignee: MASSCLOUDS INNOVATION RESEARCH INSTITUTE (BEIJING) OF INFORMATION TECHNOLOGY
    Inventors: Lei Shi, Hui Zhang, Dong Cheng, Wenqiang Niu
  • Patent number: 10403024
    Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 3, 2019
    Assignee: INTEL CORPORATION
    Inventors: Bimal Poddar, Prasoonkumar Surti, Rahul P. Sathe
  • Patent number: 10380039
    Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Niranjan L. Cooray, Satyeshwar Singh, Sameer KP, Ankur N. Shah, Kun Tian, Abhishek R. Appu, Altug Koker, Joydeep Ray, Balaji Vembu, Pattabhiraman K, David Puffer, David J. Cowperthwaite, Rajesh M. Sankaran
  • Patent number: 10350485
    Abstract: Aspects of the present disclosure describe methods and apparatuses for improving efficiency in emulation. An emulated CPU receives inputs and generates a first set of frames. The frames are stored in a buffer on the emulator. Once all of the frames in the first set of frames have been produced, the contents of the buffer may be delivered to an emulated GPU. Each frame is then rendered by the emulated GPU. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 16, 2019
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Jacob P. Stine, Victor Octav Suba Mirua
  • Patent number: 10347040
    Abstract: The invention notably relates to a computer-implemented method for displaying a 3D assembly of modeled objects. The method comprises streaming from a first computer to a second computer at least one raster image of a first 3D modeled object, and rendering on the second computer the 3D assembly of modeled objects by merging a second 3D modeled object with the streamed at least one raster image.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: July 9, 2019
    Assignee: DASSAULT SYSTEMES
    Inventors: Malika Boulkenafed, Jean Julien Tuffreau
  • Patent number: 10346018
    Abstract: The present invention provides a method, an apparatus and a storage medium for processing an HTML5 Canvas application, said method comprising: in the first thread: CPU executes codes of a graphic drawing application to draw each frame of canvas, when it is detected that rendering is needed, all canvas drawing commands of said frame of canvas are cached without executing the corresponding rendering, and when the drawing of said frame of canvas is completed, all the cached canvas drawing commands of said frame of canvas are sent to a second thread; in the second thread, CPU calls GPU to execute all canvas drawing commands of each frame of canvas sent by the first thread, and GPU performs rendering on each frame of canvas according to the canvas drawing commands. The present invention realizes concurrent thread processing by means of caching drawing commands such that JavaScript codes and rendering can be executed simultaneously.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: July 9, 2019
    Assignee: GUANGZHOU UCWEB COMPUTER TECHNOLOGY CO., LTD.
    Inventor: Xuxin Yi
  • Patent number: 10332230
    Abstract: A method of graphics processing comprising receiving, at a graphics processing unit (GPU), a command stream, the command stream including one or more commands to be performed by the GPU and at least one command stream hint, the at least one command stream hint providing a characterization of a workload of the command stream, performing, by the GPU, a power management process based on the at least one command stream hint prior to executing the command stream, and executing, by the GPU, the command stream.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Eduardus Antonius Metz, Song Zhao, Navid Farazmand, Qiao Shen
  • Patent number: 10324748
    Abstract: Apparatuses, methods and storage medium associated with live migration of virtual machines (VMs) from/to host computers with graphics virtualization are disclosed herein. In embodiments, an apparatus may include a virtual machine monitor (VMM) having a memory manager to manage accesses of system memory of the apparatus, including tracking of modified memory pages of the system memory. Additionally, the VMM may include a graphics command parser to analyze graphics commands issued to a graphics processor (GPU) of the apparatus to detect writes to the system memory caused by the graphics commands, and augment the tracking of modified memory pages. Further, the VMM may include a live migration function to live migrate a VM to another apparatus, including provision of current memory content of the VM, utilizing modified memory pages tracked by the memory manager, as augmented by the graphics command parser.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Yao Zu Dong, Zhiyuan Lv
  • Patent number: 10324726
    Abstract: Techniques are disclosed relating to scheduling graphics instructions for execution on different types of execution units based on characteristics of decoded and cached graphics instruction. In some embodiments, a graphics unit includes multiple different types of execution units that are configured to execute different types of instructions (e.g., different units for datapath, sample, load/store, etc.). In some embodiments, the graphics unit stores decoded instructions in an instruction cache in at least one cache level, along with information specifying characteristics of the instructions. The characteristics may be stored at clause granularity and may indicate the type of instructions in each clause (e.g., corresponding to which type of execution unit is configured to execute the instructions).
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: June 18, 2019
    Assignee: Apple Inc.
    Inventors: Michael A. Geary, Brian K. Reynolds, Terence M. Potter
  • Patent number: 10319138
    Abstract: An embodiment of graphics apparatus may include a coarse depth tester to perform a coarse depth test on a block of pixels, and a stencil tester to perform a stencil test on the block of pixels. The stencil tester may be further configured to perform the stencil test in parallel with the coarse depth test. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Vasanth Ranganathan, Saikat Mandal, Prasoonkumar Surti, Abhishek R. Appu, Andrew S. Downsworth, Vamsee Vardhan Chivukula, Akshay Chada, Karol A. Szerszen, Joydeep Ray, Bryon T. Rogers
  • Patent number: 10310895
    Abstract: A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 4, 2019
    Assignee: INTEL CORPORATION
    Inventors: Altug Koker, Joydeep Ray, Balaji Vembu, James A. Valerio, Abhishek R. Appu
  • Patent number: 10296592
    Abstract: Implementations disclose methods and systems for rendering, by a browser, a content item projected on a mesh. A method includes providing, by a browser executing on a user device, an application programming interface (API) to communicate with a web application that includes a user interface to present a content item on the user device; receiving, by the browser from the web application via the API, an instruction to project the content item on a mesh, where the instruction identifies the content item and the mesh; rendering, by the browser and without involvement of the web application, a first frame of the content item projected on the mesh in a first orientation; and causing, by the browser, the rendered first frame to be displayed on the user device.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: May 21, 2019
    Assignee: GOOGLE LLC
    Inventors: Andrew Top, Anjali Wheeler
  • Patent number: 10289393
    Abstract: According to one embodiment of the present disclosure, a computing system is provided, including a graphical processing unit (GPU) and a processor. The processor may be configured to execute a run-time executable cross-compiler to receive a GPU-executed program of a plurality of GPU-executed programs. The processor may be further configured to receive summary data associated with the GPU-executed program. The summary data may include a sequence in which the plurality of GPU-executed programs are configured to be executed. Based at least in part on the GPU-executed program and the summary data, the processor may be further configured to generate a translated GPU-executed program.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 14, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Matthew Gordon, Aaron Blake Stover
  • Patent number: 10282804
    Abstract: A mechanism is described for facilitating configuration of computing engines based on runtime workload measurements at computing devices. A method of embodiments, as described herein, includes detecting a work unit corresponding to a workload, and collecting metrics relating to the work unit, where the metrics to indicate one or more characteristics of the work unit. The method may further include evaluating the one or more characteristics based on one or more configuration parameters relating to computing resources, and generating, based on evaluating of the one or more characteristics, a configuration plan specific to the work unit and applicable to one or more subsequent work units that are similar to the work unit. The method may further include applying and executing the configuration plan at a computing device upon execution of the one or more subsequent work units.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: May 7, 2019
    Assignee: INTEL CORPORATION
    Inventors: Travis T. Schluessler, John G. Gierach
  • Patent number: 10275853
    Abstract: The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: April 30, 2019
    Assignee: Intel Corporation
    Inventors: Ramanathan Sethuraman, Arojit Roychowdhury, Ajaya V. Durg, Rajeev D. Muralidhar
  • Patent number: 10255106
    Abstract: A device for processing data includes a processing unit configured to predict an execution time of a compute kernel on a secondary processing unit and, based on the predicted execution time, make a power management decision for the secondary processing unit.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Navid Farazmand, Eduardus Antonius Metz, David Rigel Garcia Garcia
  • Patent number: 10248751
    Abstract: Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: April 2, 2019
    Assignee: Synopsys, Inc.
    Inventors: Glenn B. Graham, Ajay Guleria, Jeffrey J. Loescher
  • Patent number: 10242115
    Abstract: The present invention relates to a computer-implemented method for handling a set of data containers of a file structure, which method is performed by one or more processors of a computing device. The method comprises determining a first set of coordinates on a digital boundary for each data container, and storing the first set of coordinates associated with each data container in a memory. Furthermore, each data container is arranged in a parent data container, and each first set of coordinates associated with a data container is representative of a default position of that data container on the digital boundary. The present invention also relates to a computing device and to a computer-readable medium.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: March 26, 2019
    Assignee: ContentMap Aktiebolag
    Inventor: Tomas Hultgren
  • Patent number: 10241766
    Abstract: A computing device for just-in-time cross-compiling compiled binaries of application programs that utilize graphics processing unit (GPU) executed programs configured to be executed on a first GPU having a first application binary interface (ABI) including a second GPU having a second ABI different from the first ABI of the first GPU, and a processor configured to execute an application program that utilizes a plurality of GPU-executed programs configured to be executed for the first ABI of the first GPU, execute a run-time executable cross-compiler configured to, while the application program is being executed, emulate the first ABI using hardware resources of the second GPU by translating between the first ABI and the second ABI, and execute the plurality of GPU-executed programs on the second GPU with the emulated first ABI, and pass output of the plurality of GPU-executed programs for the emulated first ABI through the second ABI.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: March 26, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Matthew Gordon, Roger John Perkins
  • Patent number: 10226700
    Abstract: A video server is configured to provide streaming video to players of computer games over a computing network. The video server can provided video of different games to different players simultaneously. This is accomplished by rendering several video streams in parallel using a single GPU (Graphics Processing Unit). The output of the GPU is provided to graphics processing pipelines that are each associated with a specific client/player and are dynamically allocated as needed. A client qualifier may be used to assure that only clients capable of presenting the streaming video to a player at a minimum level of quality receive the video stream. Video frames provided by the video server optionally include overlays added to the output of the GPU. These overlays can include voice data received from another game player. These overlays may be used to prevent presentation of non-allowed input controls.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: March 12, 2019
    Assignee: Sony Interactive Entertainment America LLC
    Inventors: Andrew Buchanan Gault, Rui Filipe Andrade Pereira, David Perry, Brian K. F. Lau, Kelvin Michael Yong, Claes Christian Rickeby, Ryan Hamilton Breed, Eleazar T. Galano, III, Austin English
  • Patent number: 10229471
    Abstract: Power management techniques include a graphics processing unit (GPU) in which the GPU determines whether it is operating outside an operational limit and, when the GPU is operating outside the operational limit, the GPU alters performance of an operation to be performed texture processor within the GPU to reduce complexity of the operation. Otherwise, the GPU may perform the texture processing operation at its default complexity. These techniques provide a degree of power control not available in other techniques.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 12, 2019
    Assignee: Apple Inc.
    Inventors: Gokhan Avkarogullari, Jason P. Jane, Alex Kan