Graphic Command Processing Patents (Class 345/522)
  • Patent number: 11348197
    Abstract: A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. Cost indication logic obtains a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing rendered image values for a region of the rendered image corresponding to the set of one or more tiles. The image processing logic processes rendered image values for regions of the rendered image. The computing system causes the image processing logic to process rendered image values for regions of the rendered image in dependence on the cost indications for the corresponding sets of one or more tiles.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: May 31, 2022
    Assignee: Imagination Technologies Limited
    Inventors: John W. Howson, Richard Broadhurst, Steven Fishwick
  • Patent number: 11327640
    Abstract: Systems, methods, and devices can allow applications to provide complication data to be displayed in display of an electronic device. A client application can create a data object according to a template to efficiently select how the data object is to be displayed. For example, a complication controller on the electronic device can receive new data and determine which template to use. The data object can be sent to a display manager that can identify the selected template and display the data according to the template.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: May 10, 2022
    Assignee: APPLE INC.
    Inventors: Eliza C. Block, David A. Schimon, Eric Lance Wilson, Joshua H. Shaffer, Paul W. Salzman, Christopher C. Jensen, Timothy C. Lee, Daniel B. Pollack, Alexander Ledwith, Kevin Will Chen, Lawrence Y. Yang, Alan C. Dye
  • Patent number: 11327947
    Abstract: Systems, computer program products, and methods are described herein for identifying, tagging, and monitoring data flow in a system environment. The present invention may be configured to receive data sets generated by applications for storage in data structures, generate unique identifiers for the data sets, and add the unique identifiers to the data sets. The present invention may be further configured to monitor, based on the unique identifiers, access to and movement of the data sets, generate, based on monitoring the access to and the movement of the data sets, flow data, and generate, based on the flow data, a data flow model. The present invention may be further configured to provide, to a user device, a graphical user interface for display by the user device, where the graphical user interface includes information based on the data flow model.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: May 10, 2022
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Mark Earl Brubaker, Elisabeth Loeber Shore
  • Patent number: 11322119
    Abstract: A semiconductor device includes a processor configured to perform a rendering operation of an image frame to acquire rendering data, and write the acquired rendering data on a memory device, and a display controller configured to perform a read operation of the memory device on which the rendering data is written, to acquire image data. The semiconductor device further includes a micro-sequencing circuit configured to transmit a start signal to the display controller, based on a degree of execution of the rendering operation. The display controller is further configured to, based on the transmitted start signal, start the read operation.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Chul Yoon, Seong Woon Kim, Hyeong-Seok Kim, Kil Whan Lee
  • Patent number: 11321907
    Abstract: A system and a method are disclosed that optimizes a graphics driver. The system may be embodied as a computing device that includes a storage that is internal to the computing device, a graphic processing unit that includes a driver and a controller. The controller may be configured to run a daemon process that optimizes a shader and/or a shader pipeline for an application that is resident on the computing device when the computing device is not running the application and stores at least one optimization for the shader in the storage. The at least one optimization may be based on the application. The daemon process may further receive a request from the driver of the GPU for an optimization for the shader/shader pipeline during a runtime compilation of the shader and provide the at least one optimization to the driver of the GPU from the storage.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: May 3, 2022
    Inventors: Gabriel T. Dagani, Raun M. Krisch, Zachary Neyland, Robert Metzger, David C. Tannenbaum
  • Patent number: 11295425
    Abstract: A multi-layer low-pass filter is used to filter a first frame of video data representing at least a portion of an environment of an individual. A first layer of the filter has a first filtering resolution setting for a first subset of the first frame, while a second layer of the filter has a second filtering resolution setting for a second subset. The first subset includes a data element positioned along a direction of a gaze of the individual, and the second subset of the frame surrounds the first subset. A result of the filtering is compressed and transmitted via a network to a video processing engine configured to generate a modified visual representation of the environment.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: April 5, 2022
    Assignee: Apple Inc.
    Inventors: Can Jin, Nicolas Pierre Marie Frederic Bonnier, Hao Pan
  • Patent number: 11282162
    Abstract: A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the plurality of primitives. For each of a plurality of tiles, an object list is derived including data identifying the primitive from which each modified primitive located at least partially within that tile is derived. Alternatively, the object list may include data identifying each modified primitive located at least partially within that tile. Each tile is then shaded for display using its respective object list.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: March 22, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Steven J. Fishwick, John W. Howson
  • Patent number: 11282160
    Abstract: A server that includes a graphics processing unit (GPU) may receive, from a first application that is remote from the server, a first request to reserve a first number of cores of the GPU for a first amount of time. The server may also receive, from a second application that is also remote from the server, a second request to reserve a second number of cores of the GPU for a second amount of time that at least partly overlaps the first amount of time. The server may determine that the first request is associated with a higher priority than the second request and, in response, may reserve the first number of cores for the first amount of time for the first application. The server may send, to the first application, an indication that the first number of cores have been reserved as requested by the first application.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: March 22, 2022
    Assignee: Cisco Technology, Inc.
    Inventors: Robert Edgar Barton, Jerome Henry, Russell Paul Gyurek, Frank Brockners
  • Patent number: 11276137
    Abstract: There is provided a graphics processor comprising a programmable execution unit operable to execute programs for respective execution thread groups. An eviction checking circuit is provided that is configured to check instructions as they are being fetched for execution from an instruction cache to determine whether the instruction includes any conditional eviction conditions that if not met indicate that the program to which the instruction relates should not continue to be executed for the group of execution threads. The eviction checking circuit is then configured to check whether any conditional eviction conditions are satisfied at this point and either allow the execution unit to continue program execution or cause the thread group to be evicted.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: March 15, 2022
    Assignee: Arm Limited
    Inventors: Isidoros Sideris, Stephane Forey, William Robert Stoye, John David Robson
  • Patent number: 11263798
    Abstract: A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: March 1, 2022
    Assignee: Imagination Technologies Limited
    Inventors: John Howson, Steven Fishwick
  • Patent number: 11257179
    Abstract: Techniques are disclosed relating to using cost estimates for portions of a graphics frame to schedule graphics rendering tasks. In some embodiments, a processor generates a first set of cost estimates for respective different portions of a frame for a first render and a second set of cost estimates for respective different portions of a frame for a second render. In some embodiments, the processor compares the first set of cost estimates with the second set of cost estimates. In response to an output of the comparison meeting a first threshold level of similarity, the graphics processor may use one or more portions of the frame generated by the first render for the second render instead of performing the second render for the one or more portions.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: February 22, 2022
    Assignee: Apple Inc.
    Inventor: Steven Fishwick
  • Patent number: 11249765
    Abstract: Techniques for improving performance of accelerated processing devices (“APDs”) when exceptions occur are provided. In APDs, the very large number of parallel processing execution units, and the complexity of the hardware used to execute a large number of work-items in parallel, means that APDs typically stall when an exception occurs (unlike in central processing units (“CPUs”), which are able to execute speculatively and out-of-order). However, the techniques provided herein allow at least some execution to occur past exceptions. Execution past an exception generating instruction occurs by executing instructions that would not lead to a corruption while skipping those that would lead to a corruption. After the exception has been satisfied, execution occurs in a replay mode in which the potentially exception-generating instruction is executed and in which instructions that did not execute in the exception-wait mode are executed. A mask and counter are used to control execution in replay mode.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 15, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Anthony T. Gutierrez
  • Patent number: 11243802
    Abstract: A device configured to execute a plurality of operating systems, including a display configured to display a screen corresponding to an active operating system among the plurality of operating systems; and a controller configured to control the display to display an operation screen of the active operating system on the display when the active operating system is activated and to display an operation screen of a secondary operating system on the display when the device receives a user input according to a predetermined interface for switching from the active operating system to the secondary operating system.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-yong Yoo, Chan-ju Park, Sung-min Lee, Bok-deuk Jeong
  • Patent number: 11227358
    Abstract: Apparatuses including general-purpose graphics processing units and graphics multiprocessors that exploit queues or transitional buffers for improved low-latency high-bandwidth on-die data retrieval are disclosed. In one embodiment, a graphics multiprocessor includes at least one compute engine to provide a request, a queue or transitional buffer, and logic coupled to the queue or transitional buffer. The logic is configured to cause a request to be transferred to a queue or transitional buffer for temporary storage without processing the request and to determine whether the queue or transitional buffer has a predetermined amount of storage capacity.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Aravindh Anantaraman, Altug Koker, Varghese George, Subramaniam Maiyuran, SungYe Kim, Valentin Andrei
  • Patent number: 11227529
    Abstract: A data conversion method, a display method, a data conversion device and a display device. The data conversion method includes: performing data reorganization on original pixel data corresponding to at least one row of pixels in a display panel to obtain reorganized pixel data. In any data channel, the performing data reorganization on original pixel data corresponding to at least one row of pixels in a display panel to obtain reorganized pixel data includes: a first reorganized part in the n-th reorganized pixel data set consists of a first original part in the (n-1)-th original pixel data set, and a second reorganized part in the n-th reorganized pixel data set consists of a second original part in the n-th original pixel data set, wherein n is an integer satisfying 1<n?N, and N is an integer greater than 1.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 18, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Junbo Hu
  • Patent number: 11228703
    Abstract: The disclosure provides a method for controlling a camera module. The camera module is removable between a first position received in a body of the electronic device and a second position exposed from the body. The method includes: driving the camera module to slide to the second position based on a call request on the camera module sent by a camera application, in response to the camera application running in a system foreground; determining whether a current application is a preset application, in response to an application in the system foreground switching from the camera application to the current application; determining whether receiving a call request on the camera module sent by the current application in response to the current application being the preset application; and maintaining the camera module in the second position within a preset duration, in response to not receiving the call request.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 18, 2022
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Peng Zhong
  • Patent number: 11210847
    Abstract: When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions for rendering, each region comprising a respective area of the render output. It is determined for which of the plurality of regions of the render output a primitive should be rendered for. Associated state data for rendering the primitive is stored in a “state data” data structure in memory. For each region of the render output it is determined the primitive should be rendered for, a reference to the associated state data for rendering the primitive is stored in a respective, different data structure for each different region of the render output it is determined the primitive should be rendered for.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: December 28, 2021
    Assignee: Arm Limited
    Inventors: Alexander Eugene Chalfin, Andreas Due Engh-Halstvedt, Olof Henrik Uhrenholt
  • Patent number: 11204765
    Abstract: A graphics processing unit (GPU) utilizes block general purpose registers (bGPRs) to load multiple waves of samples for an instruction group into a processing pipeline and receive processed samples from the pipeline. The GPU acquires a credit for the bGPR for execution of the instruction group for a first wave using a persistent GPR and the bGPR. The GPU refunds the credit upon loading the first wave into the pipeline. The GPU executes a subsequent wave for the instruction group to load samples to the pipeline when at least one credit is available and the pipeline is processing the first wave. The GPU stores an indication of each wave that has been loaded into the pipeline in a queue. The GPU returns samples for a next wave in the queue from the pipeline to the bGPR for further processing when the physical slot of the bGPR is available.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: December 21, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Yun Du, Fei Wei, Gang Zhong, Minjie Huang, Jian Jiang, Zilin Ying, Baoguang Yang, Yang Xia, Jing Han, Liangxiao Hu, Chihong Zhang, Chun Yu, Andrew Evan Gruber, Eric Demers
  • Patent number: 11204767
    Abstract: Generating context switching locations for compiler-assisted context switching. A set of possible locations is determined for preferred preemption points in a set of threads based on (i) an identification of a set of candidate markers for preferred preemption points and (ii) a type of characteristic that is associated with a possible location included in the set of possible locations. A modified set of possible locations is generated in a data structure based on the type of characteristic, wherein the modified set of possible locations indicate one or more preferred preemption points in the set of threads.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventor: Kelvin Don Nilsen
  • Patent number: 11182222
    Abstract: Apparatus and methods related to software architectures in a multiprocessor-based access device used in a content delivery and/or service provider network. In one embodiment, a software architecture is provided for a cable modem using a first type of digital processor (e.g., RISC core or similar), and a second type of digital processor (e.g., multi-core CPU). In one variant, the RISC processor is used as a cable modem stack processor, and the CPU processor is used as an application processor. A Linux (e.g., OpenWrt)-based software architecture is used wherein software components placed on both processors can communicate to effectuate, e.g., configuration changes to the device (including the cable modem stack). A mechanism to establish communications between the two different processor domains and retrieve the requested information based on existing (e.g., RPC) protocols is also disclosed.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: November 23, 2021
    Assignee: Charter Communications Operating, LLC
    Inventors: Shlomo Ovadia, Michael Kloberdans
  • Patent number: 11182159
    Abstract: Methods, systems, and apparatus, including computer-readable media, are described for performing vector reductions using a shared scratchpad memory of a hardware circuit having processor cores that communicate with the shared memory. For each of the processor cores, a respective vector of values is generated based on computations performed at the processor core. The shared memory receives the respective vectors of values from respective resources of the processor cores using a direct memory access (DMA) data path of the shared memory. The shared memory performs an accumulation operation on the respective vectors of values using an operator unit coupled to the shared memory. The operator unit is configured to accumulate values based on arithmetic operations encoded at the operator unit. A result vector is generated based on performing the accumulation operation using the respective vectors of values.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 23, 2021
    Assignee: Google LLC
    Inventors: Thomas Norrie, Gurushankar Rajamani, Andrew Everett Phelps, Matthew Leever Hedlund, Norman Paul Jouppi
  • Patent number: 11170462
    Abstract: Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 9, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hans Fernlund, Mitchell H. Singer, Manu Rastogi
  • Patent number: 11164373
    Abstract: A graphics processing apparatus includes a tessellation circuit and a post-processing circuit. The tessellation circuit performs tessellation processing to subdivide a patch in an image frame into a plurality of triangles. The tessellation circuit further performs triangle striping processing to convert data of the plurality of triangles into data of a triangle strip. The post-processing circuit performs subsequent processing on the data of the triangle strip.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: November 2, 2021
    Assignee: GlenFly Technology Co., Ltd.
    Inventors: Huaisheng Zhang, Maoxin Sun, Juding Zheng
  • Patent number: 11158023
    Abstract: A graphics processing system having a rendering space divided into a plurality of tiles. The system comprises geometry processing logic and rasterization logic. The geometry processing logic is configured to generate transformed position data for each of a plurality of untransformed primitives based on untransformed geometry data associated therewith; group the plurality of untransformed primitives into a plurality of primitive blocks; and generate an untransformed display list for each tile based on the transformed position data. Each untransformed display list comprises: (i) information identifying each untransformed primitive block that comprises at least one untransformed primitive that, when transformed, falls at least partially with the tile; and (ii) for each identified untransformed primitive bock, information identifying the untransformed primitives or transformed primitives related to that untransformed primitive block relevant for rendering the tile.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: October 26, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, Xile Yang, John W. Howson
  • Patent number: 11145271
    Abstract: Methods, systems, and computer-readable media for virtualizing graphics processing in a provider network are disclosed. A virtual compute instance is provisioned from a provider network. The provider network comprises a plurality of computing devices configured to implement a plurality of virtual compute instances with multi-tenancy. A virtual GPU is attached to the virtual compute instance. The virtual GPU is implemented using a physical GPU, and the physical GPU is accessible to the virtual compute instance over a network. An application is executed using the virtual GPU on the virtual compute instance. Executing the application generates virtual GPU output that is provided to a client device.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: October 12, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Nicholas Patrick Wilt, Ashutosh Tambe, Nathan Lee Burns, Nafea Bshara
  • Patent number: 11145024
    Abstract: Methods, systems, and devices for processing are described. A device may parse a set of layers of a deep neural network. The set of layers may be associated with a set of machine learning operations of the deep neural network. The device may determine one or more layer parameters based on the determined set of layers. In some aspects, the device may determine an execution time associated with executing a shader dispatch based on the one or more layer parameters. The device may batch the shader dispatch to a command buffer based on the execution time and process the command buffer based on the batching. The device may determine a target execution time based on an assembly time associated with the command buffer, a processing time associated with the command buffer, a frequency level associated with processing the command buffer, the one or more layer parameters, or some combination thereof.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: October 12, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Balaji Calidas, Joshua Walter Kelly, Avinash Seetharamaiah, Jonnala Gadda Nagendra Kumar, Hitendra Mohan Gangani
  • Patent number: 11126411
    Abstract: Disclosed herein are system, method, and computer program product embodiments for providing a dashboard user interface design and integration system. An embodiment operates by receiving a request to generate an interface associated with a data source and establishing a connection with the data source to receive data from the data source. An indication of a component to be displayed on the interface is received and the interface is generated. The interface includes the component and is coupled to the data source.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 21, 2021
    Assignee: SAP SE
    Inventors: Joachim Fitzer, Eduardo Berlitz, Eduardo Carvalho, Alexandre Faltz, Reinhold Kautzleben, Willian Mendes
  • Patent number: 11113782
    Abstract: Various examples are disclosed for dynamic kernel slicing for virtual graphics processing unit (vGPU) sharing in serverless computing systems. A computing device is configured to provide a serverless computing service, receive a request for execution of program code in the serverless computing service in which a plurality of virtual graphics processing units (vGPUs) are used in the execution of the program code, determine a slice size to partition a compute kernel of the program code into a plurality of sub-kernels for concurrent execution by the vGPUs, the slice size being determined for individual ones of the sub-kernels based on an optimization function that considers a load on a GPU, determine an execution schedule for executing the individual ones of the sub-kernels on the vGPUs in accordance with a scheduling policy, and execute the sub-kernels on the vGPUs as partitioned in accordance with the execution schedule.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: September 7, 2021
    Assignee: VMware, Inc.
    Inventors: Chandra Prakash, Anshuj Garg, Uday Pundalik Kurkure, Hari Sivaraman, Lan Vu, Sairam Veeraswamy
  • Patent number: 11082547
    Abstract: A terminal, comprising at least two front cameras located behind a display panel, wherein an area corresponding to a position of the at least one camera on the display panel is a first area, and other than the first area on the display panel is a second area, wherein each pixel unit of the first area and the second area respectively comprises a transparent portion and a non-transparent portion and a proportion of the transparent portion in the first area is greater than that of the second area. The terminal further comprises a processor configured to obtain N pictures taken by the at least two cameras, and process the N pictures by complementing the occluded areas based on pictures taken by the at least two cameras to obtain a picture in which the occluded area is completely or partially recovered.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: August 3, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Gang Xu, Tuo Sun, Hung-yuan Jau, Chiaching Chu, Kangchung Liu, Hsienchang Hou, Xin Li
  • Patent number: 11077363
    Abstract: A video server is configured to provide streaming video to players of computer games over a computing network. The video server can provided video of different games to different players simultaneously. This is accomplished by rendering several video streams in parallel using a single GPU (Graphics Processing Unit). The output of the GPU is provided to graphics processing pipelines that are each associated with a specific client/player and are dynamically allocated as needed. A client qualifier may be used to assure that only clients capable of presenting the streaming video to a player at a minimum level of quality receive the video stream. Video frames provided by the video server optionally include overlays added to the output of the GPU. These overlays can include voice data received from another game player.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 3, 2021
    Assignee: Sony Interactive Entertainment LLC
    Inventors: Andrew Buchanan Gault, David Perry, Rui Filipe Andrade Pereira
  • Patent number: 11075972
    Abstract: The disclosure is directed to systems and methods for local rendering of 3D models which are then accessed by remote computers. The advantage of the system is that extensive hardware needed for rendering complex 3D models is centralized and can be accessed by smaller remote computers without and special hardware or software installation. The system also provides enhanced security as model data can be restricted to a limited number of servers instead of stored on individual computers.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: July 27, 2021
    Assignee: AVEVA Software, LLC
    Inventors: David Matthew Stevenson, Paul Antony Burton, Mira Witczak
  • Patent number: 11055809
    Abstract: An apparatus and method for provisioning virtualized tile-based graphics processing circuitry. For example, one embodiment of an apparatus comprises: processing resources to process commands including graphics commands and generate results; resource partitioning circuitry to partition the processing resources into a plurality of tiles in accordance with a specified tile-based resource allocation policy; and graphics virtualization circuitry to perform tile-based allocation of the processing resources to a plurality of virtual machines in accordance with a specified virtualization policy, the virtual machines to be executed in a virtualized execution environment.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Ankur N. Shah, Nishanth Reddy Pendluru, Joseph Koston, Murali Ramadoss
  • Patent number: 11055812
    Abstract: A method comprises obtaining a first plurality of render commands comprising at least a geometry stage and a fragment stage. An identification may be made as to which of the geometry stages of the first plurality of render commands are idempotent. Dependency information is determined for the first plurality of render commands, e.g., identifying and labeling both “true” and “artificial” dependencies between the stages of the commands. The first plurality of render commands may be encoded and executed by a graphics processing unit (GPU) according to a labeled execution graph generated based on the dependency information. During execution, the GPU may attempt to “opportunistically” launch at least one identified idempotent geometry stage command for which at least one artificial barrier still remains. If the opportunistically-launched geometry stage work fails, the work may be discarded, and the method may wait until all barriers have been met before attempting to relaunch it.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 6, 2021
    Assignee: Apple Inc.
    Inventor: Subodh Asthana
  • Patent number: 11037365
    Abstract: A method, an apparatus, a medium, a terminal, and a device for processing multi-angle free-perspective data are disclosed. The method includes: acquiring a data header file; determining a defined format of a data file according to a parsing result of the data header file; reading and obtaining a data combination from the data file based on the defined format, where the data combination includes pixel data and depth data of multiple synchronized images, and the multiple synchronized images have different perspectives with respect a to-be-viewed area, and pixel data and depth data of each image of the multiple synchronized images has an association relationship; and performing image or video reconstruction of a virtual viewpoint according to the read data combination, where the virtual viewpoint is selected from a multi-angle free-perspective range, and the multi-angle free-perspective range is a range supporting virtual viewpoint switching viewing of the to-be-viewed area.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 15, 2021
    Inventor: Xiaojie Sheng
  • Patent number: 11036308
    Abstract: Methods and systems for performing automated keyboard mapping for virtual desktops are described herein. A system may generate a keyboard mapping table containing a plurality of keyboard inputs. The system may simulate a keyboard input locally at the system and using a virtual desktop hosted by a remote desktop platform to generate keyboard simulation outputs in response to a first keyboard input. In response to determining a discrepancy between the keyboard simulation outputs, the system may modify a key value in the keyboard mapping table resulting in a corrected keyboard mapping table, where the key value corresponds to the first keyboard input. In response to receiving a second keyboard input, the system may apply the corrected keyboard mapping table to display a keyboard output at the virtual desktop hosted by the remote desktop platform, where the second keyboard input has the same key value as the first keyboard input.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 15, 2021
    Assignee: Citrix Systems, Inc.
    Inventors: Wenping Xu, Junying Gao
  • Patent number: 11029866
    Abstract: A method comprises: determining whether an event triggering processing of data at a storage device occurs, the data being predetermined to be processed at a computing device associated with the storage device; in response to determining that the event occurs, determining available resources of the storage device; and in response to an amount of the available resources exceeding a first predetermined threshold, causing the storage device to process the data and provide the processed data to the computing device. As such, operations to be performed to data may be adaptively allocated, deployed and adjusted on the storage device and the computing device, so that computing capabilities of both the storage device and the computing device may be fully leveraged, and further the computing efficiency of the entire data processing system may be improved.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 8, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Junping Zhao, Andrew Anzhou Hou
  • Patent number: 11017773
    Abstract: Aspects of the disclosure relate to voice-based time-sensitive task processing over a high generation cellular network. A computing platform may establish a communication channel with a computing device. The computing platform may authenticate a user of the computing device, where the user is authorized to access the enterprise server. Then, the computing platform may detect, via the communication interface, a voice-based interaction from the authenticated user. The computing platform may cause the voice-based interaction to be captured as audio data. Subsequently, the computing platform may transform the audio data to textual data. The computing platform may analyze the textual data to identify a time-sensitive task related to an entity. Then, the computing platform may generate, based on the identified time-sensitive task, one or more instructions to execute the time-sensitive task.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 25, 2021
    Assignee: Bank of America Corporation
    Inventors: Prabhat Ranjan, Kevin A. Delson
  • Patent number: 11010866
    Abstract: A circuit device (100) includes a coordinate transform circuit (20) and a mapping processing circuit (30). The coordinate transform circuit (20) performs coordinate transformation from an input coordinate (IXY1) to an output coordinate (QXY1). The mapping processing circuit (30) generates a second image (IMG2) to be displayed in a display panel for displaying an image in a curved screen display by performing mapping processing on a first image (IMG1) that is input based on the output coordinate (QXY1). The coordinate transform circuit (20) performs the coordinate transformation from the input coordinate (IXY1) to the output coordinate (QXY1) by performing computation processing using a second or more order polynomial representing the coordinate transformation.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: May 18, 2021
    Inventors: Jeffrey Eric, Kumar Anandabairavasamy Anand, Yasutoshi Akiba
  • Patent number: 10991065
    Abstract: Method, system, and computer readable medium for processing graphics using an OpenGL Embedded Systems Application Programming Interface (Open GLES API) include: decoding a source graphic to generate a graphic object, where the graphic object includes a set of index values and a color palette; providing the graphic object to a Graphical Processing Unit (GPU) through the Open GLES API, including providing the set of index values in a first acceptable graphic format of the Open GLES API to the GPU, and providing the color palette in a second acceptable graphic format of the Open GLES API to the GPU; and triggering the GPU to render the source graphic according to the set of index values received in the first acceptable graphic format of Open GLES API and the palette received in the second acceptable graphic format of Open GLES API.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: April 27, 2021
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventor: Xiaodong Jin
  • Patent number: 10986372
    Abstract: The present invention relates to a method for decoding a video signal, comprising the steps of: acquiring a transform size flag of the current macroblock from a video signal; checking the number of non-zero transform coefficients at each pixel position in a first transform block which corresponds to the transform size flag; changing a scan order of the first transform block by prioritizing the position of the pixel having the greatest number of the non-zero transform coefficients in the first transform block; determining the number of the non-zero transform coefficients at each pixel position in a second transform block, and setting the changed scan order of the first transform block as an initialized scan order of the second transform block; adding the number of the non-zero transform coefficients at each pixel position in the first transform block and the number of the non-zero transform coefficients at each pixel position in the second transform block, and changing the scan order of the second transform bl
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: April 20, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Jung Sun Kim, Seung Wook Park, Young Hee Choi, Jaewon Sung, Byeong Moon Jeon, Joon Young Park
  • Patent number: 10972738
    Abstract: A video encoding apparatus includes a data buffer and a video encoding circuit. Encoding of a first frame includes: deriving reference pixels of a reference frame from reconstructed pixels of the first frame, respectively, and storing reference pixel data into the data buffer for inter prediction, wherein the reference pixel data include information of pixel values of the reference pixels. Encoding of a second frame includes performing prediction upon a coding unit in the second frame to determine a target predictor for the coding unit. The prediction performed upon the coding unit includes: checking if a search range on the reference frame for finding a predictor of the coding unit under an inter prediction mode includes at least one reference pixel of the reference frame that is not accessible to the video encoding circuit, and determining the target predictor for the coding unit according to a checking result.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 6, 2021
    Assignee: MEDIATEK INC.
    Inventors: Li-Heng Chen, Tung-Hsing Wu, Yi-Hsin Huang, Lien-Fei Chen, Ting-An Lin, Han-Liang Chou
  • Patent number: 10964293
    Abstract: Embodiments are directed to managing display hardware for visualizing data a network computer. A modeling engine may provide a data model includes a plurality of data objects and a display model that includes a plurality of display objects that may be based on the plurality of data objects. Action objects may be associated with display objects in the display model. A display engine may display the display model on a hardware display based on context information that includes performance characteristics of the hardware display. In response to a trigger events, action objects may be displayed on the hardware display based on the context information. In response to detecting input signals associated with the action objects the display model may be modified based on the action objects. The modified display model may be displayed on the hardware display based on the context information.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 30, 2021
    Assignee: Tableau Software, LLC
    Inventors: Vasily Khudyakov, Jewel Loree, Felipe Luis Naranjo
  • Patent number: 10963299
    Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 30, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Anthony Gutierrez, Sooraj Puthoor
  • Patent number: 10942983
    Abstract: An interactive device comprises a user interface arranged to define at least one display request comprising at least location data and display data, a network interface arranged to transmit a request for web page data corresponding to a display request, and a memory for receiving corresponding web page data and customisation data, the web page data comprising map data and/or object data. A web interpreter is arranged to allow the display of a web page and comprising a 3D engine arranged to calculate three-dimensional display data. The web interpreter also comprises a manager operating by an execution cycle and arranged to determine a list comprising at least one operation which can be a request for object data and/or map data or the processing of received data by the 3D engine or the display engine.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: March 9, 2021
    Assignee: F4
    Inventors: Gauthier Hellot, Charly Koza, Cécile Giorla, Alexis Galley, Jean-Marc Oury, Bruno Heintz
  • Patent number: 10929946
    Abstract: Multiple-buffered display rendering without the use of hardware or software interrupts. Five buffers can be used: two designated as front buffers and three designated as back buffers. Initially, all five buffers may be targeted for rendering in round robin fashion. As frames are rendered and processed by the graphics device, a frame index counter may be updated to track the ordinal number of each frame rendered by the GPU.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: February 23, 2021
    Assignee: Channel One Holdings Inc.
    Inventors: Gregory Szober, Stephen Viggers, Aidan Fabius
  • Patent number: 10929944
    Abstract: Systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor are disclosed. The GPU coprocessor includes a SIMD unit with the ability to self-schedule sub-wave procedures based on input data flow events. A host processor sends messages targeting the GPU coprocessor to a queue. In response to detecting a first message in the queue, the GPU coprocessor schedules a first sub-task for execution. The GPU coprocessor includes an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file. The VGPR file is split into two files. The first VGPR file is a larger register file with one read port and one write port. The second VGPR file is a smaller register file with multiple read ports and one write port. The second VGPR introduces the ability to co-issue more than one instruction per clock cycle.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: February 23, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jiasheng Chen, Timour Paltashev, Alexander Lyashevsky, Carl Kittredge Wakeland, Michael J. Mantor
  • Patent number: 10929212
    Abstract: A method of running a network application based on a Point-of-Sale (POS) terminal is provided. The method includes: receiving an operation on a network application; calling a first interface of a JAVASCRIPT layer according to the operation; parsing the first interface and acquiring an object corresponding to the first interface; transmitting a corresponding signal through the object and executing a slot function associated with the signal; calling a second interface of a plug-in layer through the slot function, and calling a hardware module corresponding to the second interface to perform the operation. The POS payment terminal traverses and accesses nodes in an object tree through an embedded graphical user interface system according to a node hierarchy relationship in the object tree, and renders various tag objects contained in the object tree one by one to display a network application page on a display screen of the POS payment terminal.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: February 23, 2021
    Assignee: PAX COMPUTER TECHNOLOGY (SHENZHEN) CO., LTD
    Inventors: Lei Huang, Sining Ye, Lihong Xie
  • Patent number: 10915507
    Abstract: A method and apparatus for data conversion in a run-time execution environment are provided. In the method and apparatus, a data request specifying a second schema for requested data is received. A data portion is retrieved from a data store, whereby the retrieved data has a first schema. On a condition that the first schema and the second schema are determined to be different, the data portion is converted to the second schema to produce a converted data portion, whereby the conversion is performed based at least in part on data conversion information. The converted data portion is then provided to the run-time execution environment for use in a run-time execution of the computer program.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: February 9, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Pablo Puo Hen Cheng, Rosen Ognyanov Baklov
  • Patent number: 10909654
    Abstract: A graphics rendering system is provided for controlling the rendering of images to manage expected errors. The graphics rendering system receives a specification of a render task to be performed to render an image of a graphics scene and then identifies computing devices that each have a graphics processing unit. The graphics rendering system directs each of the identified computing devices to render the image specified by the render task such that each identified computing device renders the same image. When the graphics rendering system detects that a computing device has completed the render task successfully, it provides the image rendered by that computing device as the rendered image of the render task such that any other image rendered by another of the computing devices is not needed.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: February 2, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Ashish Consul, Huy Hoang, Bryan W. Tuttle
  • Patent number: 10902550
    Abstract: A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. Cost indication logic obtains a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing rendered image values for a region of the rendered image corresponding to the set of one or more tiles. The image processing logic processes rendered image values for regions of the rendered image. The computing system causes the image processing logic to process rendered image values for regions of the rendered image in dependence on the cost indications for the corresponding sets of one or more tiles.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: January 26, 2021
    Assignee: Imagination Technologies Limited
    Inventors: John W. Howson, Richard Broadhurst, Steven Fishwick