Abstract: An electronic gaming device provides a rendering pipeline for an electronic game. The rendering pipeline includes a client component and a native component of the rendering pipeline, where the client component is configured to: initiate a rendering operations pipe between the client component and the native component; convert display commands from a source language of the electronic game into rendering operations of an intermediate rendering language; and transmit the rendering operations through the rendering operations pipe to the native component. The native component is configured to: receive the rendering operations via the rendering operations pipe; translate the rendering operations from the intermediate rendering language into rendering operations of the native component; and perform the rendering operations of the native component on the display device.

Abstract: A display apparatus, according to one or more embodiments, includes a timing controller configured to generate a timing control signal, and a plurality of display modules, each display module of the plurality of display modules including a plurality of pixels and a plurality of micro pixel controllers electrically connected to a plurality of inorganic light-emitting elements constituting two or more pixels, wherein each display module of the plurality of display modules is configured to switch the plurality of inorganic light-emitting elements based on the timing control signal, and wherein each of the plurality of micro pixel controllers switches the plurality of inorganic light-emitting elements causing a blanking period to be periodically generated in response to a frame rate being changed.

Abstract: Disclosed is technology for generating an accurate and lossless static object model of a dynamic webpage as it is rendered by a browser, including webpages that include a shadow DOM. A method includes receiving, at a computer system, a webpage, instantiating a headless web browser application to render the webpage by creating a document object model (“DOM”) and a cascading style sheet object model (“CSSOM”) in browser memory, the DOM and CSSOM representing dynamic rendered webpage content, injecting a probe script into the headless browser to retrieve the dynamic rendered content, traversing, by the probe script, the DOM, including traversing regular nodes of the DOM and shadow nodes of a shadow DOM, retrieving dynamic information for the regular and shadow nodes, and building a static object model based on the dynamic information.

Abstract: Disclosed herein are system, method, and computer program product embodiments for modifying graphics rendering by transcoding a serialized command stream. An embodiment operates by receiving a command configured to instruct an API to render a graphics element. The embodiment further operates by generating, based on the command, a transcoded command configured to instruct the API to render a modified graphics element by applying a set of modification factors to a portion of the command. Subsequently, the embodiment operates by transmitting the transcoded command to the API.

Abstract: A first processor processes an instruction configured to perform a plurality of functions. The plurality of functions includes one or more functions to operate on one or more tensors. A determination is made of a function of the plurality of functions to be performed. The first processor provides to a second processor information related to the function. The second processor is to perform the function. The first processor and the second processor share memory providing memory coherence.

Abstract: It is disclosed a system comprising a display characteristics evaluation unit configured to evaluate display characteristics of a display of an electronic device, a media access unit configured to receive a source media file from a media storage, and a display-dependent processing unit configured to perform, based on the display characteristics, a display-dependent processing of the source media file to obtain a display-dependent media file.

Abstract: A graphics processing system for generating a rendering output includes geometry processing logic and rasterization logic. The geometry processing logic includes first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to: divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one of the one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block that are to be used in generating the rendering output.

Abstract: Incompatible graphics frameworks present a barrier to emulating applications of one operating system (guest OS) upon a computer system employing a different operating system (host OS) such as occurs with virtual machines. Accordingly, in order to address limitations of emulating guest OS graphic pipelines upon the host OS the inventors have established methodologies for cross-platform graphics pipeline emulation, thus enabling efficient implementations of cross-platform virtualization solutions, through the establishment of emulation keys to support generic and specific graphics pipelines together with caching sets of graphical pipelines for subsequent retrieval and execution.

Abstract: A method of operating a computing system includes receiving, by a GPU driver included in a CPU of the computing system, a plurality of commands associated with a plurality of rendering targets included in a frame buffer of the computing system, storing the plurality of commands in a command buffer included in the GPU driver, setting, by a command manager included in the GPU driver, at least one unused rendering target among the plurality of rendering targets to a delayed submission mode, and selectively deleting, by the command manager, a command associated with the at least one unused rendering target set to the delayed submission mode from the command buffer based on whether the command includes an instruction to invalidate a rendering result associated with the at least one unused rendering target.

Abstract: Systems, apparatuses, and methods for implementing a depth buffer pre-pass are disclosed. A rendering application uses a binning approach to render primitives of a virtual scene on a tile-by-tile basis, with each tile corresponding to a portion of the screen. The application causes a depth buffer pre-pass to be performed for the primitives of the tile before a pixel shader is invoked. During the depth buffer pre-pass, only the depth part of the virtual scene is rendered to determine which pixel samples are visible and which pixel samples are hidden. Then, the scene is redrawn, but the pixel samples that are hidden are not sent to the pixel shader. In cases where a relatively large percentage of primitives overlap, this technique increases the efficiency of the rendering application since pixel shading can be avoided for the pixel samples that are hidden.

Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.

Abstract: A video server is configured to provide streaming video to players of computer games over a computing network. The video server can provided video of different games to different players simultaneously. This is accomplished by rendering several video streams in parallel using a single GPU (Graphics Processing Unit). The output of the GPU is provided to graphics processing pipelines that are each associated with a specific client/player and are dynamically allocated as needed. A client qualifier may be used to assure that only clients capable of presenting the streaming video to a player at a minimum level of quality receive the video stream. Video frames provided by the video server optionally include overlays added to the output of the GPU. These overlays can include voice data received from another game player.

Abstract: A system for rendering 6 degree-of-freedom virtual reality according to an embodiment of the present disclosure includes a visibility test module performing a visibility test for determining whether a current point of interest where a main viewpoint is directed is visible for each of a plurality of reference viewpoints and generating visibility information by identifying the number of invisible fragments of each reference viewpoint according to the performance result, a reference viewpoint selection module selecting a final reference viewpoint for a rendering process for a current frame based on the visibility information for each of the plurality of reference viewpoints and a preset selection criterion, and a rendering process module performing an image-based rendering process by using a color image and a depth image corresponding to the final reference viewpoint.

Abstract: A method of rendering image frames for a videogame includes the steps of, for one or more predetermined features of a virtual environment of a videogame, setting a respective per-frame movement distance threshold; calculating a respective minimum frame rate at which movement of the or each predetermined features of the virtual environment of the videogame between successive image frames remains within the respective movement distance threshold; detecting whether the current frame rate is below one or more of the respective minimum frame rates; and if so, reducing a rendering resolution used during rendering of one or more subsequent image frames to increase the frame rate above one or more of the minimum frame rates.

Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

Abstract: Techniques are provided for vectorizing Heapsort. A K-heap is used as the underlying data structure for indexing values being sorted. The K-heap is vectorized by storing values in a contiguous memory array containing a beginning-most side and end-most side. The vectorized Heapsort utilizes horizontal aggregation SIMD instructions for comparisons, shuffling, and moving data. Thus, the number of comparisons required in order to find the maximum or minimum key value within a single node of the K-heap is reduced resulting in faster retrieval operations.

Abstract: The present disclosure relates to linking processing codes between platforms, and more particularly, to automatically record linking processing codes between platforms and methods of use. The method includes: obtaining a legacy processing code from a legacy system; obtaining a virtual code from a virtual entry table (VET) which corresponds with the legacy processing code; and mapping the legacy processing code to a target processing code using the virtual code from the VET.

Abstract: A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.

Abstract: The disclosed systems and methods relate to archiving communications. Information associated with one or more documents can be received. The documents can be captured from one or more communication modalities. The information can be normalized into a single information structure. A transcript of an interaction between participants can be generated for the communication modalities using the normalized information. The transcript can be stored in an archiving system.

Abstract: A first processing unit such as a graphics processing unit (GPU) pipelines that execute commands and a scheduler to schedule one or more first commands for execution by one or more of the pipelines. The one or more first commands are received from a user mode driver in a second processing unit such as a central processing unit (CPU). The scheduler schedules one or more second commands for execution in response to completing execution of the one or more first commands and without notifying the second processing unit. In some cases, the first processing unit includes a direct memory access (DMA) engine that writes blocks of information from the first processing unit to a memory. The one or more second commands program the DMA engine to write a block of information including results generated by executing the one or more first commands.

Abstract: A method is described for processing commands for a client computing device using a remote graphics processing unit server. The method includes receiving, by a display driver of the client computing device, a command from an application operating on the client computing device and compressing, by the display driver, the command to generate a compressed command. Compressing the command includes determining whether a resource associated with the command is available in a cache of the remote graphics processing unit server and replacing the resource with a reference to the resource, when the resource is available. The display driver transmits the compressed command to the remote graphics processing unit server for processing by a remote graphics processing unit (GPU) and receives data generated by the remote GPU based on processing the compressed command.

Abstract: A method for generating a graphic display of frame images comprises collecting one or more graphic objects to be rendered into a frame image, the one or more graphic objects being represented as a mesh in object space; determining one or more shadels to be computed for the frame image based at least on the one or more input attributes for each of the one or more graphic objects, each shadel being a shaded portion of the mesh; allocating space in a shadel storage buffer for the one or more shadels; populating a work queue buffer, the work queue buffer containing a list of commands to be executed to compute each of the one or more shadels; computing the determined one or more shadels to generate a shaded mesh; and rasterizing the shaded mesh into the frame image. The method can be implemented using a graphics processing unit (GPU).

Abstract: A method includes determining that a new draw call is received; comparing a state identity (ID) of a graphics state stored in the ring storage with a state ID of a graphics state associated with the new draw call; determining if the ring storage has available space to store the graphics state associated with the new draw call; storing the graphics state associated with the new draw call in the ring storage, based on determining that the ring storage has available space; determining a location of a first valid and non-default entry and a last valid and non-default entry of the graphics state associated with the new draw call stored in the ring storage; and collecting data from one or more valid entries of the graphics state associated with the new draw call stored in the ring storage to complete a task associated with the new draw call.

Abstract: The present disclosure provides an image acquisition and processing method. The method includes acquiring an invoking event being configured to invoke an image acquisition device located under a display screen, an acquisition window of the image acquisition device corresponding to a first area of the display screen; activating the image acquisition device based on the invoking event; determining a display state of the first area; acquiring an image by using the image acquisition device based on the display state of the first area; and displaying the acquired image.

Abstract: An apparatus such as a graphics processing unit (GPU) includes shader engines and front end (FE) circuits. Subsets of the FE circuits are configured to schedule commands for execution on corresponding subsets of the shader engines. The apparatus also includes a set of physical paths configured to convey information from the FE circuits to a memory via the shader engines. Subsets of the physical paths are allocated to the subsets of the FE circuits and the corresponding subsets of the shader engines. The apparatus further includes a scheduler configured to receive a reconfiguration request and modify the set of physical paths based on the reconfiguration request. In some cases, the reconfiguration request is provided by a central processing unit (CPU) that requests the modification based on characteristics of applications generating the commands.

Abstract: An apparatus includes at least one processor; and at least one non-transitory memory including computer program code; wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to perform: receive a scene description comprising data associated with a scene; place the data associated with the scene into data buffers and create command buffers; adapt the data placed within the data buffers and synchronize the data within the data buffers with information provided from local media or network media; signal information about the adaptation to update the command buffers that command a renderer; and render the scene using the data within the data buffers and the command buffers.

Abstract: Methods, systems and apparatuses for graph stream processing are disclosed. One apparatus includes a cascade of graph streaming processors, wherein each of the graph streaming processor includes a processor array, and a graph streaming processor scheduler. The cascade of graph streaming processors further includes a plurality of shared command buffers, wherein each shared command buffer includes a buffer address, a write pointer, and a read pointer, wherein for each of the plurality of shared command buffers a first graph streaming processor writes commands to the shared command buffer as indicated by the write pointer of the shared command buffer and a second graph streaming processor reads commands from the shared command buffer as indicated by the read pointer, wherein at least one graph streaming processor scheduler operates to manage the write pointer and the read pointer to avoid overwriting unused commands of the shared command buffer.

Abstract: A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. Cost indication logic obtains a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing rendered image values for a region of the rendered image corresponding to the set of one or more tiles. The image processing logic processes rendered image values for regions of the rendered image. The computing system causes the image processing logic to process rendered image values for regions of the rendered image in dependence on the cost indications for the corresponding sets of one or more tiles.

Abstract: Systems, computer program products, and methods are described herein for identifying, tagging, and monitoring data flow in a system environment. The present invention may be configured to receive data sets generated by applications for storage in data structures, generate unique identifiers for the data sets, and add the unique identifiers to the data sets. The present invention may be further configured to monitor, based on the unique identifiers, access to and movement of the data sets, generate, based on monitoring the access to and the movement of the data sets, flow data, and generate, based on the flow data, a data flow model. The present invention may be further configured to provide, to a user device, a graphical user interface for display by the user device, where the graphical user interface includes information based on the data flow model.

Abstract: Systems, methods, and devices can allow applications to provide complication data to be displayed in display of an electronic device. A client application can create a data object according to a template to efficiently select how the data object is to be displayed. For example, a complication controller on the electronic device can receive new data and determine which template to use. The data object can be sent to a display manager that can identify the selected template and display the data according to the template.

Abstract: A system and a method are disclosed that optimizes a graphics driver. The system may be embodied as a computing device that includes a storage that is internal to the computing device, a graphic processing unit that includes a driver and a controller. The controller may be configured to run a daemon process that optimizes a shader and/or a shader pipeline for an application that is resident on the computing device when the computing device is not running the application and stores at least one optimization for the shader in the storage. The at least one optimization may be based on the application. The daemon process may further receive a request from the driver of the GPU for an optimization for the shader/shader pipeline during a runtime compilation of the shader and provide the at least one optimization to the driver of the GPU from the storage.

Abstract: A semiconductor device includes a processor configured to perform a rendering operation of an image frame to acquire rendering data, and write the acquired rendering data on a memory device, and a display controller configured to perform a read operation of the memory device on which the rendering data is written, to acquire image data. The semiconductor device further includes a micro-sequencing circuit configured to transmit a start signal to the display controller, based on a degree of execution of the rendering operation. The display controller is further configured to, based on the transmitted start signal, start the read operation.

Abstract: A multi-layer low-pass filter is used to filter a first frame of video data representing at least a portion of an environment of an individual. A first layer of the filter has a first filtering resolution setting for a first subset of the first frame, while a second layer of the filter has a second filtering resolution setting for a second subset. The first subset includes a data element positioned along a direction of a gaze of the individual, and the second subset of the frame surrounds the first subset. A result of the filtering is compressed and transmitted via a network to a video processing engine configured to generate a modified visual representation of the environment.

Abstract: A server that includes a graphics processing unit (GPU) may receive, from a first application that is remote from the server, a first request to reserve a first number of cores of the GPU for a first amount of time. The server may also receive, from a second application that is also remote from the server, a second request to reserve a second number of cores of the GPU for a second amount of time that at least partly overlaps the first amount of time. The server may determine that the first request is associated with a higher priority than the second request and, in response, may reserve the first number of cores for the first amount of time for the first application. The server may send, to the first application, an indication that the first number of cores have been reserved as requested by the first application.

Abstract: A method and system for generating and shading a computer graphics image in a tile based computer graphics system is provided. Geometry data is supplied and a plurality of primitives are derived from the geometry data. One or more modified primitives are then derived from at least one of the plurality of primitives. For each of a plurality of tiles, an object list is derived including data identifying the primitive from which each modified primitive located at least partially within that tile is derived. Alternatively, the object list may include data identifying each modified primitive located at least partially within that tile. Each tile is then shaded for display using its respective object list.

Abstract: There is provided a graphics processor comprising a programmable execution unit operable to execute programs for respective execution thread groups. An eviction checking circuit is provided that is configured to check instructions as they are being fetched for execution from an instruction cache to determine whether the instruction includes any conditional eviction conditions that if not met indicate that the program to which the instruction relates should not continue to be executed for the group of execution threads. The eviction checking circuit is then configured to check whether any conditional eviction conditions are satisfied at this point and either allow the execution unit to continue program execution or cause the thread group to be evicted.

Abstract: A graphics processing unit having multiple groups of processor cores for rendering graphics data for allocated tiles and outputting the processed data to regions of a memory resource. Scheduling logic allocates sets of tiles to the groups of processor cores to perform a first render, and at a time when at least one of the groups has not completed processing its allocated sets of one or more tiles as part of the first render, allocates at least one set of tiles for a second render to one of the other groups of processor cores for processing. Progress indication logic indicates progress of the first render, indicating regions of the memory resource for which processing for the first render has been completed. Progress check logic checks the progress indication in response to a request for access to a region of the memory resource as part of the second render and enables access that region of the resource in response to an indication that processing for the first render has been completed for that region.

Abstract: Techniques are disclosed relating to using cost estimates for portions of a graphics frame to schedule graphics rendering tasks. In some embodiments, a processor generates a first set of cost estimates for respective different portions of a frame for a first render and a second set of cost estimates for respective different portions of a frame for a second render. In some embodiments, the processor compares the first set of cost estimates with the second set of cost estimates. In response to an output of the comparison meeting a first threshold level of similarity, the graphics processor may use one or more portions of the frame generated by the first render for the second render instead of performing the second render for the one or more portions.

Abstract: Techniques for improving performance of accelerated processing devices (“APDs”) when exceptions occur are provided. In APDs, the very large number of parallel processing execution units, and the complexity of the hardware used to execute a large number of work-items in parallel, means that APDs typically stall when an exception occurs (unlike in central processing units (“CPUs”), which are able to execute speculatively and out-of-order). However, the techniques provided herein allow at least some execution to occur past exceptions. Execution past an exception generating instruction occurs by executing instructions that would not lead to a corruption while skipping those that would lead to a corruption. After the exception has been satisfied, execution occurs in a replay mode in which the potentially exception-generating instruction is executed and in which instructions that did not execute in the exception-wait mode are executed. A mask and counter are used to control execution in replay mode.

Abstract: A device configured to execute a plurality of operating systems, including a display configured to display a screen corresponding to an active operating system among the plurality of operating systems; and a controller configured to control the display to display an operation screen of the active operating system on the display when the active operating system is activated and to display an operation screen of a secondary operating system on the display when the device receives a user input according to a predetermined interface for switching from the active operating system to the secondary operating system.

Abstract: A data conversion method, a display method, a data conversion device and a display device. The data conversion method includes: performing data reorganization on original pixel data corresponding to at least one row of pixels in a display panel to obtain reorganized pixel data. In any data channel, the performing data reorganization on original pixel data corresponding to at least one row of pixels in a display panel to obtain reorganized pixel data includes: a first reorganized part in the n-th reorganized pixel data set consists of a first original part in the (n-1)-th original pixel data set, and a second reorganized part in the n-th reorganized pixel data set consists of a second original part in the n-th original pixel data set, wherein n is an integer satisfying 1<n?N, and N is an integer greater than 1.

Abstract: The disclosure provides a method for controlling a camera module. The camera module is removable between a first position received in a body of the electronic device and a second position exposed from the body. The method includes: driving the camera module to slide to the second position based on a call request on the camera module sent by a camera application, in response to the camera application running in a system foreground; determining whether a current application is a preset application, in response to an application in the system foreground switching from the camera application to the current application; determining whether receiving a call request on the camera module sent by the current application in response to the current application being the preset application; and maintaining the camera module in the second position within a preset duration, in response to not receiving the call request.

Abstract: Apparatuses including general-purpose graphics processing units and graphics multiprocessors that exploit queues or transitional buffers for improved low-latency high-bandwidth on-die data retrieval are disclosed. In one embodiment, a graphics multiprocessor includes at least one compute engine to provide a request, a queue or transitional buffer, and logic coupled to the queue or transitional buffer. The logic is configured to cause a request to be transferred to a queue or transitional buffer for temporary storage without processing the request and to determine whether the queue or transitional buffer has a predetermined amount of storage capacity.

Abstract: When processing graphics primitives in a graphics processing system, the render output is divided into a plurality of regions for rendering, each region comprising a respective area of the render output. It is determined for which of the plurality of regions of the render output a primitive should be rendered for. Associated state data for rendering the primitive is stored in a “state data” data structure in memory. For each region of the render output it is determined the primitive should be rendered for, a reference to the associated state data for rendering the primitive is stored in a respective, different data structure for each different region of the render output it is determined the primitive should be rendered for.

Abstract: Generating context switching locations for compiler-assisted context switching. A set of possible locations is determined for preferred preemption points in a set of threads based on (i) an identification of a set of candidate markers for preferred preemption points and (ii) a type of characteristic that is associated with a possible location included in the set of possible locations. A modified set of possible locations is generated in a data structure based on the type of characteristic, wherein the modified set of possible locations indicate one or more preferred preemption points in the set of threads.

Abstract: A graphics processing unit (GPU) utilizes block general purpose registers (bGPRs) to load multiple waves of samples for an instruction group into a processing pipeline and receive processed samples from the pipeline. The GPU acquires a credit for the bGPR for execution of the instruction group for a first wave using a persistent GPR and the bGPR. The GPU refunds the credit upon loading the first wave into the pipeline. The GPU executes a subsequent wave for the instruction group to load samples to the pipeline when at least one credit is available and the pipeline is processing the first wave. The GPU stores an indication of each wave that has been loaded into the pipeline in a queue. The GPU returns samples for a next wave in the queue from the pipeline to the bGPR for further processing when the physical slot of the bGPR is available.

Abstract: Apparatus and methods related to software architectures in a multiprocessor-based access device used in a content delivery and/or service provider network. In one embodiment, a software architecture is provided for a cable modem using a first type of digital processor (e.g., RISC core or similar), and a second type of digital processor (e.g., multi-core CPU). In one variant, the RISC processor is used as a cable modem stack processor, and the CPU processor is used as an application processor. A Linux (e.g., OpenWrt)-based software architecture is used wherein software components placed on both processors can communicate to effectuate, e.g., configuration changes to the device (including the cable modem stack). A mechanism to establish communications between the two different processor domains and retrieve the requested information based on existing (e.g., RPC) protocols is also disclosed.

Abstract: Methods, systems, and apparatus, including computer-readable media, are described for performing vector reductions using a shared scratchpad memory of a hardware circuit having processor cores that communicate with the shared memory. For each of the processor cores, a respective vector of values is generated based on computations performed at the processor core. The shared memory receives the respective vectors of values from respective resources of the processor cores using a direct memory access (DMA) data path of the shared memory. The shared memory performs an accumulation operation on the respective vectors of values using an operator unit coupled to the shared memory. The operator unit is configured to accumulate values based on arithmetic operations encoded at the operator unit. A result vector is generated based on performing the accumulation operation using the respective vectors of values.

Abstract: Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.

Abstract: A graphics processing apparatus includes a tessellation circuit and a post-processing circuit. The tessellation circuit performs tessellation processing to subdivide a patch in an image frame into a plurality of triangles. The tessellation circuit further performs triangle striping processing to convert data of the plurality of triangles into data of a triangle strip. The post-processing circuit performs subsequent processing on the data of the triangle strip.