Graphic Command Processing Patents (Class 345/522)
  • Patent number: 11822960
    Abstract: Methods, systems, and apparatuses for graph stream processing are disclosed. One apparatus includes a cascade of graph streaming processors, wherein each of the graph streaming processor includes a processor array, and a graph streaming processor scheduler. The cascade of graph streaming processors further includes a plurality of shared command buffers, wherein each shared command buffer includes a buffer address, a write pointer, and a read pointer, wherein for each of the plurality of shared command buffers a first graph streaming processor writes commands to the shared command buffer as indicated by the write pointer of the shared command buffer and a second graph streaming processor reads commands from the shared command buffer as indicated by the read pointer, wherein at least one graph streaming processor scheduler operates to manage the write pointer and the read pointer to avoid overwriting unused commands of the shared command buffer.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: November 21, 2023
    Assignee: Blaize, Inc.
    Inventors: Venkata Ganapathi Puppala, Sarvendra Govindammagari, Lokesh Agarwal, Satyaki Koneru
  • Patent number: 11816790
    Abstract: A rule set or scene grammar can be used to generate a scene graph that represents the structure and visual parameters of objects in a scene. A renderer can take this scene graph as input and, with a library of content for assets identified in the scene graph, can generate a synthetic image of a scene that has the desired scene structure without the need for manual placement of any of the objects in the scene. Images or environments synthesized in this way can be used to, for example, generate training data for real world navigational applications, as well as to generate virtual worlds for games or virtual reality experiences.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: November 14, 2023
    Assignee: Nvidia Corporation
    Inventors: Jeevan Devaranjan, Sanja Fidler, Amlan Kar
  • Patent number: 11816820
    Abstract: A multi-layer low-pass filter is used to filter a first frame of video data representing at least a portion of an environment of an individual. A first layer of the filter has a first filtering resolution setting for a first subset of the first frame, while a second layer of the filter has a second filtering resolution setting for a second subset. The first subset includes a data element positioned along a direction of a gaze of the individual, and the second subset of the frame surrounds the first subset. A result of the filtering is compressed and transmitted via a network to a video processing engine configured to generate a modified visual representation of the environment.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: November 14, 2023
    Assignee: Apple Inc.
    Inventors: Can Jin, Nicolas Peirre Marie Frederic Bonnier, Hao Pan
  • Patent number: 11816161
    Abstract: In a search and database system, a graph generator builds a graph, comprising nodes and edges, and stores that graph in a database or other data structure and uses a repeated extending and culling process to build the graph. From that storage, the graph can be used to generate displays for users interested in learning about the graph and/or for performing queries and the like on that graph data.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: November 14, 2023
    Assignee: Bit Discovery Inc.
    Inventors: Jeremiah Jacob Grossman, Robert Stephen Hansen
  • Patent number: 11810505
    Abstract: An electronic device may include a display panel, a display driver IC (integrated circuit) and a processor, wherein the display driver IC may set an output time (horizontal time) of one of lines constituting the display panel to a first time period, set a number of vertical blank lines for the display panel to a first number, drive the display panel at a first refresh rate corresponding to the first time period and the first number of the vertical blank lines, receive a control signal for changing from the first refresh rate to a second refresh rate from the processor, and set the output time to a second time period or set the number of the vertical blank lines to a second number and drive the display panel based on the control signal, and wherein the display panel may be driven at a second refresh rate while the second time period and the second number of vertical blank lines are being set.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: November 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minwoo Lee, Seoyoung Lee, Juseok Lee, Youngdo Kim, Sungha Park, Woonbo Yeo
  • Patent number: 11809902
    Abstract: Techniques for executing workgroups are provided. The techniques include executing, for a first workgroup of a first kernel dispatch, a workgroup dependency instruction that includes an indication to prioritize execution of a second workgroup of a second kernel dispatch, and in response to the workgroup dependency instruction, dispatching the second workgroup of the second kernel dispatch prior to dispatching a third workgroup of the second kernel dispatch, wherein no workgroup dependency instruction including an indication to prioritize execution of the third workgroup has been executed.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 7, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexandru Dutu, Marcus Nathaniel Chow, Matthew D. Sinclair, Bradford M. Beckmann, David A. Wood
  • Patent number: 11789711
    Abstract: Systems and methods are described that implement a tool chain which receives original software source code, analyzes the code and divides the code into modules that run optimally on the available heterogeneous resources. For example, the toolchain system segments original source code into code segments, and determine the specialized processor resource, such as a digital signal processing (DSP) processor, Field Programming Gate Array (FPGA), Graphical Processing Unit (GPU), and the like, that most optimally performs computations of the particular code segment. A parsing engine determines the processor of the heterogenous resources, based on a set of rules and/or a trained classifier (e.g., a trained machine learning model). New code segments can be generated that can be executed on the determined type of processor. Further, the system enables application programming interfaces (APIs) that can interface the new code segment with other generated code segments and/or some portions of the original code.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: October 17, 2023
    Assignee: MERCURY MISSION SYSTEMS, LLC
    Inventors: Omar Facory, Andrew Kostrzewski
  • Patent number: 11782568
    Abstract: According to aspects of the present disclosure, when a PC and a MFP are remotely connected through an network IF, a CPU of the MFP selects still images, which constitutes an animation, one by one and display the animation on a panel of the MFP by displaying the selected one image with sequentially switching the selected one image. Then, in a case where the same animation is continuously displayed on the panel of the MFP, after generating a plurality of pieces of screen data, which constitute the animation, to be displayed on the PC, the CPU of the MFP stops to repeatedly generate screen data same as the plurality of pieces of screen data.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: October 10, 2023
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Yutaka Urakawa
  • Patent number: 11782580
    Abstract: The invention is directed to an electronic device. The electronic device generates for presentation on a display a user interface including a plurality of groups of icons. A plurality of the icons have been grouped based at least in part on metadata of applications associated with the icons. The electronic device receives input selecting a respective icon. In response to receiving the input selecting a respective icon, the electronic device invokes an instance of an application associated with the respective icon.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: October 10, 2023
    Assignee: Apple Inc.
    Inventors: Elbert D. Chen, Joe Howard, Joshua McGlinn, Jonathan Lochhead, Benjamin W. Keighran, Marcel Van Os, William M. Bachman, Jeffrey L. Robbin, Jennifer L. C. Folse, Lynne Kress
  • Patent number: 11775810
    Abstract: Systems, apparatus, and methods for thread-based scheduling within a multicore processor. Neural networking uses a network of connected nodes (aka neurons) to loosely model the neuro-biological functionality found in the human brain. Various embodiments of the present disclosure use thread dependency graphs analysis to decouple scheduling across many distributed cores. Rather than using thread dependency graphs to generate a sequential ordering for a centralized scheduler, the individual thread dependencies define a count value for each thread at compile-time. Threads and their thread dependency count are distributed to each core at run-time. Thereafter, each core can dynamically determine which threads to execute based on fulfilled thread dependencies without requiring a centralized scheduler.
    Type: Grant
    Filed: January 2, 2023
    Date of Patent: October 3, 2023
    Assignee: Femtosense, Inc.
    Inventors: Sam Brian Fok, Alexander Smith Neckar
  • Patent number: 11755299
    Abstract: There is provided methods and apparatus to improve runtime by computer programs at compilation time. A compiler analyzes code to be translated into machine executable instructions to identify overloaded functional units of the target processor, and replaces instructions scheduled on the overloaded functional unit to an idle unit using functionally equivalent operations on the idle unit. The replacement instructions may be taken from an instruction replacement library comprising function calls that implement functionality of a functional unit of the target processor on another functional unit of the target processor.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: September 12, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Tomasz S. Czajkowski, Ehsan Amiri
  • Patent number: 11740898
    Abstract: The present disclosure provides a computation device. The computation device is configured to perform a machine learning computation, and includes an operation unit, a controller unit, and a conversion unit. The storage unit is configured to obtain input data and a computation instruction. The controller unit is configured to extract and parse the computation instruction from the storage unit to obtain one or more operation instructions, and to send the one or more operation instructions and the input data to the operation unit. The operation unit is configured to perform operations on the input data according to one or more operation instructions to obtain a computation result of the computation instruction. In the examples of the present disclosure, the input data involved in machine learning computations is represented by fixed-point data, thereby improving the processing speed and efficiency of training operations.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: August 29, 2023
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD
    Inventors: Yao Zhang, Bingrui Wang
  • Patent number: 11741653
    Abstract: A method of tiled rendering of an image for display is provided which comprises receiving an image comprising one or more three dimensional (3D) objects and executing a visibility pass for determining locations of primitives of the image. The method also comprises executing, concurrently with the executing of the visibility pass, front end geometry processing of one of the primitives determined, from the visibility pass, to be in a first one of a plurality of tiles of the image and executing, concurrently with the executing of the visibility pass, back end processing of the one primitive in the first tile.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: August 29, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mika Tuomi, Ruijin Wu, Anirudh R. Acharya, Kiia Kallio
  • Patent number: 11734079
    Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Toby Opferman, Eliezer Weissmann, Robert Valentine, Russell Cameron Arnold
  • Patent number: 11734011
    Abstract: A processor core executes a first process. The first process is associated with a first context tag that is generated based on context information controlled by an operating system or hypervisor of the processing system. A branch prediction structure selectively provides the processor core with access to an entry in the branch prediction structure based on the first context tag and a second context tag associated with the entry. The branch prediction structure selectively provides the processor core with access to the entry in response to the first process executing a branch instruction. Tagging entries in the branch prediction structure reduces, or eliminates, aliasing between information used to predict branches taken by different processes at a branch instruction.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 22, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marius Evers, David Kaplan
  • Patent number: 11725949
    Abstract: An object of the present invention is to provide a method for determining an update area, an information processing device, and a program that appropriately determines an area for updating map information. The method for determining the update area is implemented by an update area determination system, and the update area determination system includes a point identification unit and a target area determination unit. The point identification unit executes a point identification procedure for identifying two points on a map, and the target area determination unit executes a target area determination procedure for determining a target area that is a target for an update when map information is updated using a distance between the two points and position information of a representative point preset for each of a plurality of areas formed by dividing the map.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 15, 2023
    Assignee: Faurecia Clarion Electronics Co., Ltd.
    Inventors: Katsuya Asada, Yuichiro Nakagawa
  • Patent number: 11709574
    Abstract: An electronic device includes a display and a processor. The processor is electrically coupled to the display. The processor is configured to execute a plurality of program instructions to perform the following steps: defining a window display region and an interface display region on the display when the electronic device is operated in a one-hand operation mode; displaying a desktop display interface corresponding to the one-hand operation mode in the interface display region; and displaying a plugin in the window display region.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: July 25, 2023
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Yun-Ju Chen, Yu-Chi Huang, Chen-Yu Hsu, Chih-Hsien Yang, I-Hsi Wu, Hsin-Yi Pu
  • Patent number: 11709531
    Abstract: The systems and methods manage thermal states of a device through user configuration of a client application on the device. The systems and methods set thermal thresholds associated with the device. The systems and methods infer the thermal thresholds from information gathered by a client application running on the device. The systems and methods implement a stored policy associated with a violation of one of the thermal thresholds by one of the monitored thermal states.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: July 25, 2023
    Assignee: Snap Inc.
    Inventors: Michael Cieslak, Jiayao Yu, Kai Chen, Farnaz Azmoodeh, Michael David Marr, Jun Huang, Zahra Ferdowsi
  • Patent number: 11687613
    Abstract: Disclosed is technology for generating an accurate and lossless static object model of a dynamic webpage as it is rendered by a browser, including webpages that include a shadow DOM. A method includes receiving, at a computer system, a webpage, instantiating a headless web browser application to render the webpage by creating a document object model (“DOM”) and a cascading style sheet object model (“CSSOM”) in browser memory, the DOM and CSSOM representing dynamic rendered webpage content, injecting a probe script into the headless browser to retrieve the dynamic rendered content, traversing, by the probe script, the DOM, including traversing regular nodes of the DOM and shadow nodes of a shadow DOM, retrieving dynamic information for the regular and shadow nodes, and building a static object model based on the dynamic information.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: June 27, 2023
    Assignee: SITEIMPROVE A/S
    Inventors: Mads Jacobsen, Per Jakobsen
  • Patent number: 11688334
    Abstract: A display apparatus, according to one or more embodiments, includes a timing controller configured to generate a timing control signal, and a plurality of display modules, each display module of the plurality of display modules including a plurality of pixels and a plurality of micro pixel controllers electrically connected to a plurality of inorganic light-emitting elements constituting two or more pixels, wherein each display module of the plurality of display modules is configured to switch the plurality of inorganic light-emitting elements based on the timing control signal, and wherein each of the plurality of micro pixel controllers switches the plurality of inorganic light-emitting elements causing a blanking period to be periodically generated in response to a frame rate being changed.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: June 27, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangyoung Park, Hoseop Lee, Tetsuya Shigeta
  • Patent number: 11688226
    Abstract: An electronic gaming device provides a rendering pipeline for an electronic game. The rendering pipeline includes a client component and a native component of the rendering pipeline, where the client component is configured to: initiate a rendering operations pipe between the client component and the native component; convert display commands from a source language of the electronic game into rendering operations of an intermediate rendering language; and transmit the rendering operations through the rendering operations pipe to the native component. The native component is configured to: receive the rendering operations via the rendering operations pipe; translate the rendering operations from the intermediate rendering language into rendering operations of the native component; and perform the rendering operations of the native component on the display device.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: June 27, 2023
    Assignee: Aristocrat Technologies, Inc.
    Inventors: Jody Brown, Joseph Bibbo
  • Patent number: 11682102
    Abstract: Disclosed herein are system, method, and computer program product embodiments for modifying graphics rendering by transcoding a serialized command stream. An embodiment operates by receiving a command configured to instruct an API to render a graphics element. The embodiment further operates by generating, based on the command, a transcoded command configured to instruct the API to render a modified graphics element by applying a set of modification factors to a portion of the command. Subsequently, the embodiment operates by transmitting the transcoded command to the API.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: June 20, 2023
    Assignee: ROKU, INC.
    Inventor: Matthew James Sottek
  • Patent number: 11669331
    Abstract: A first processor processes an instruction configured to perform a plurality of functions. The plurality of functions includes one or more functions to operate on one or more tensors. A determination is made of a function of the plurality of functions to be performed. The first processor provides to a second processor information related to the function. The second processor is to perform the function. The first processor and the second processor share memory providing memory coherence.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: June 6, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Laith M. AlBarakat, Jonathan D. Bradbury, Timothy Slegel, Cedric Lichtenau, Simon Weishaupt, Anthony Saporito
  • Patent number: 11659223
    Abstract: It is disclosed a system comprising a display characteristics evaluation unit configured to evaluate display characteristics of a display of an electronic device, a media access unit configured to receive a source media file from a media storage, and a display-dependent processing unit configured to perform, based on the display characteristics, a display-dependent processing of the source media file to obtain a display-dependent media file.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: May 23, 2023
    Assignee: SONY CORPORATION
    Inventors: Piergiorgio Sartor, Klaus Zimmermann
  • Patent number: 11640689
    Abstract: Incompatible graphics frameworks present a barrier to emulating applications of one operating system (guest OS) upon a computer system employing a different operating system (host OS) such as occurs with virtual machines. Accordingly, in order to address limitations of emulating guest OS graphic pipelines upon the host OS the inventors have established methodologies for cross-platform graphics pipeline emulation, thus enabling efficient implementations of cross-platform virtualization solutions, through the establishment of emulation keys to support generic and specific graphics pipelines together with caching sets of graphical pipelines for subsequent retrieval and execution.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: May 2, 2023
    Assignee: Parallels International GmbH
    Inventor: Evgeny Nikitenko
  • Patent number: 11640648
    Abstract: A graphics processing system for generating a rendering output includes geometry processing logic and rasterization logic. The geometry processing logic includes first transformation logic configured to transform a plurality of untransformed primitives into a plurality of transformed primitives, the first transformation logic configured to implement one or more expansion transformation stages which generate one or more sub-primitives; a primitive block generator configured to: divide the plurality of transformed primitives into a plurality of groups; and generate an untransformed primitive block for each group comprising (i) information identifying the untransformed primitives related to the transformed primitives in the group; and (ii) an expansion transformation stage mask for at least one of the one or more expansion transformation stages that indicates the sub-primitives generated for the untransformed primitives in that untransformed primitive block that are to be used in generating the rendering output.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: May 2, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John Howson, Xile Yang
  • Patent number: 11636566
    Abstract: A method of operating a computing system includes receiving, by a GPU driver included in a CPU of the computing system, a plurality of commands associated with a plurality of rendering targets included in a frame buffer of the computing system, storing the plurality of commands in a command buffer included in the GPU driver, setting, by a command manager included in the GPU driver, at least one unused rendering target among the plurality of rendering targets to a delayed submission mode, and selectively deleting, by the command manager, a command associated with the at least one unused rendering target set to the delayed submission mode from the command buffer based on whether the command includes an instruction to invalidate a rendering result associated with the at least one unused rendering target.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: April 25, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Younggwan Kim, Taekhyun Kim
  • Patent number: 11631187
    Abstract: Systems, apparatuses, and methods for implementing a depth buffer pre-pass are disclosed. A rendering application uses a binning approach to render primitives of a virtual scene on a tile-by-tile basis, with each tile corresponding to a portion of the screen. The application causes a depth buffer pre-pass to be performed for the primitives of the tile before a pixel shader is invoked. During the depth buffer pre-pass, only the depth part of the virtual scene is rendered to determine which pixel samples are visible and which pixel samples are hidden. Then, the scene is redrawn, but the pixel samples that are hidden are not sent to the pixel shader. In cases where a relatively large percentage of primitives overlap, this technique increases the efficiency of the rendering application since pixel shading can be avoided for the pixel samples that are hidden.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: April 18, 2023
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Jan Henrik Achrenius, Mika Tuomi, Kiia Kallio, Pazhani Pillai, Laurent Lefebvre
  • Patent number: 11619987
    Abstract: When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Ravindra A. Babu, Sashank Ms, Satyanantha R. Musunuri, Sagar C. Pawar, Kalyan K. Kaipa, Vijayakumar Balakrishnan, Sameer Kp
  • Patent number: 11617947
    Abstract: A video server is configured to provide streaming video to players of computer games over a computing network. The video server can provided video of different games to different players simultaneously. This is accomplished by rendering several video streams in parallel using a single GPU (Graphics Processing Unit). The output of the GPU is provided to graphics processing pipelines that are each associated with a specific client/player and are dynamically allocated as needed. A client qualifier may be used to assure that only clients capable of presenting the streaming video to a player at a minimum level of quality receive the video stream. Video frames provided by the video server optionally include overlays added to the output of the GPU. These overlays can include voice data received from another game player.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 4, 2023
    Assignee: Sony Interactive Entertainment LLC
    Inventors: Andrew Buchanan Gault, David Perry, Rui Filipe Andrade Pereira
  • Patent number: 11615574
    Abstract: A system for rendering 6 degree-of-freedom virtual reality according to an embodiment of the present disclosure includes a visibility test module performing a visibility test for determining whether a current point of interest where a main viewpoint is directed is visible for each of a plurality of reference viewpoints and generating visibility information by identifying the number of invisible fragments of each reference viewpoint according to the performance result, a reference viewpoint selection module selecting a final reference viewpoint for a rendering process for a current frame based on the visibility information for each of the plurality of reference viewpoints and a preset selection criterion, and a rendering process module performing an image-based rendering process by using a color image and a depth image corresponding to the final reference viewpoint.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: March 28, 2023
    Assignee: MAXST CO., LTD.
    Inventors: Tae Hong Jeong, Kyu Sung Cho, Tae Yun Son, Jae Wan Park
  • Patent number: 11583769
    Abstract: A method of rendering image frames for a videogame includes the steps of, for one or more predetermined features of a virtual environment of a videogame, setting a respective per-frame movement distance threshold; calculating a respective minimum frame rate at which movement of the or each predetermined features of the virtual environment of the videogame between successive image frames remains within the respective movement distance threshold; detecting whether the current frame rate is below one or more of the respective minimum frame rates; and if so, reducing a rendering resolution used during rendering of one or more subsequent image frames to increase the frame rate above one or more of the minimum frame rates.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: February 21, 2023
    Assignee: Sony Interactive Entertainment Inc.
    Inventor: Philip Cockram
  • Patent number: 11550627
    Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 10, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony Gutierrez, Sooraj Puthoor
  • Patent number: 11513806
    Abstract: Techniques are provided for vectorizing Heapsort. A K-heap is used as the underlying data structure for indexing values being sorted. The K-heap is vectorized by storing values in a contiguous memory array containing a beginning-most side and end-most side. The vectorized Heapsort utilizes horizontal aggregation SIMD instructions for comparisons, shuffling, and moving data. Thus, the number of comparisons required in order to find the maximum or minimum key value within a single node of the K-heap is reduced resulting in faster retrieval operations.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: November 29, 2022
    Assignee: Oracle International Corporation
    Inventors: Benjamin Schlegel, Pit Fender, Harshad Kasture, Matthias Brantner, Hassan Chafi
  • Patent number: 11494201
    Abstract: The present disclosure relates to linking processing codes between platforms, and more particularly, to automatically record linking processing codes between platforms and methods of use. The method includes: obtaining a legacy processing code from a legacy system; obtaining a virtual code from a virtual entry table (VET) which corresponds with the legacy processing code; and mapping the legacy processing code to a target processing code using the virtual code from the VET.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: November 8, 2022
    Assignee: ADP, INC.
    Inventors: Eitan Klein, Jessica Anne Tatz, Mohammed Balal Ahmed, Jonathan Baier
  • Patent number: 11494232
    Abstract: A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 8, 2022
    Assignee: Intel Corporation
    Inventors: Altug Koker, Joydeep Ray, Balaji Vembu, James A. Valerio, Abhishek R. Appu
  • Patent number: 11481409
    Abstract: The disclosed systems and methods relate to archiving communications. Information associated with one or more documents can be received. The documents can be captured from one or more communication modalities. The information can be normalized into a single information structure. A transcript of an interaction between participants can be generated for the communication modalities using the normalized information. The transcript can be stored in an archiving system.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: October 25, 2022
    Assignee: Actiance, Inc.
    Inventor: John Onusko
  • Patent number: 11461137
    Abstract: A first processing unit such as a graphics processing unit (GPU) pipelines that execute commands and a scheduler to schedule one or more first commands for execution by one or more of the pipelines. The one or more first commands are received from a user mode driver in a second processing unit such as a central processing unit (CPU). The scheduler schedules one or more second commands for execution in response to completing execution of the one or more first commands and without notifying the second processing unit. In some cases, the first processing unit includes a direct memory access (DMA) engine that writes blocks of information from the first processing unit to a memory. The one or more second commands program the DMA engine to write a block of information including results generated by executing the one or more first commands.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 4, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Rex Eldon McCrary
  • Patent number: 11449963
    Abstract: A method is described for processing commands for a client computing device using a remote graphics processing unit server. The method includes receiving, by a display driver of the client computing device, a command from an application operating on the client computing device and compressing, by the display driver, the command to generate a compressed command. Compressing the command includes determining whether a resource associated with the command is available in a cache of the remote graphics processing unit server and replacing the resource with a reference to the resource, when the resource is available. The display driver transmits the compressed command to the remote graphics processing unit server for processing by a remote graphics processing unit (GPU) and receives data generated by the remote GPU based on processing the compressed command.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 20, 2022
    Assignee: Juice Technologies, Inc.
    Inventors: Dean J. Beeler, David A. McCloskey
  • Patent number: 11436783
    Abstract: A method for generating a graphic display of frame images comprises collecting one or more graphic objects to be rendered into a frame image, the one or more graphic objects being represented as a mesh in object space; determining one or more shadels to be computed for the frame image based at least on the one or more input attributes for each of the one or more graphic objects, each shadel being a shaded portion of the mesh; allocating space in a shadel storage buffer for the one or more shadels; populating a work queue buffer, the work queue buffer containing a list of commands to be executed to compute each of the one or more shadels; computing the determined one or more shadels to generate a shaded mesh; and rasterizing the shaded mesh into the frame image. The method can be implemented using a graphics processing unit (GPU).
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: September 6, 2022
    Assignee: Oxide Interactive, Inc.
    Inventors: Daniel Kurt Baker, Timothy James Kipp, Nathan Heazlett, Gregory Osefo
  • Patent number: 11416961
    Abstract: A method includes determining that a new draw call is received; comparing a state identity (ID) of a graphics state stored in the ring storage with a state ID of a graphics state associated with the new draw call; determining if the ring storage has available space to store the graphics state associated with the new draw call; storing the graphics state associated with the new draw call in the ring storage, based on determining that the ring storage has available space; determining a location of a first valid and non-default entry and a last valid and non-default entry of the graphics state associated with the new draw call stored in the ring storage; and collecting data from one or more valid entries of the graphics state associated with the new draw call stored in the ring storage to complete a task associated with the new draw call.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sushant Kondguli, Santosh Abraham
  • Patent number: 11412146
    Abstract: The present disclosure provides an image acquisition and processing method. The method includes acquiring an invoking event being configured to invoke an image acquisition device located under a display screen, an acquisition window of the image acquisition device corresponding to a first area of the display screen; activating the image acquisition device based on the invoking event; determining a display state of the first area; acquiring an image by using the image acquisition device based on the display state of the first area; and displaying the acquired image.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 9, 2022
    Assignee: LENOVO (BEIJING) CO., LTD.
    Inventor: Tao Miao
  • Patent number: 11403804
    Abstract: An apparatus includes at least one processor; and at least one non-transitory memory including computer program code; wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to perform: receive a scene description comprising data associated with a scene; place the data associated with the scene into data buffers and create command buffers; adapt the data placed within the data buffers and synchronize the data within the data buffers with information provided from local media or network media; signal information about the adaptation to update the command buffers that command a renderer; and render the scene using the data within the data buffers and the command buffers.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 2, 2022
    Assignee: Nokia Technologies Oy
    Inventors: Lauri Ilola, Lukasz Kondrad, Emre Aksu, Miska Matias Hannuksela, Sebastian Schwarz
  • Patent number: 11403729
    Abstract: An apparatus such as a graphics processing unit (GPU) includes shader engines and front end (FE) circuits. Subsets of the FE circuits are configured to schedule commands for execution on corresponding subsets of the shader engines. The apparatus also includes a set of physical paths configured to convey information from the FE circuits to a memory via the shader engines. Subsets of the physical paths are allocated to the subsets of the FE circuits and the corresponding subsets of the shader engines. The apparatus further includes a scheduler configured to receive a reconfiguration request and modify the set of physical paths based on the reconfiguration request. In some cases, the reconfiguration request is provided by a central processing unit (CPU) that requests the modification based on characteristics of applications generating the commands.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: August 2, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Rex Eldon McCrary
  • Patent number: 11379262
    Abstract: Methods, systems and apparatuses for graph stream processing are disclosed. One apparatus includes a cascade of graph streaming processors, wherein each of the graph streaming processor includes a processor array, and a graph streaming processor scheduler. The cascade of graph streaming processors further includes a plurality of shared command buffers, wherein each shared command buffer includes a buffer address, a write pointer, and a read pointer, wherein for each of the plurality of shared command buffers a first graph streaming processor writes commands to the shared command buffer as indicated by the write pointer of the shared command buffer and a second graph streaming processor reads commands from the shared command buffer as indicated by the read pointer, wherein at least one graph streaming processor scheduler operates to manage the write pointer and the read pointer to avoid overwriting unused commands of the shared command buffer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: July 5, 2022
    Assignee: Blaize, Inc.
    Inventors: Venkata Ganapathi Puppala, Sarvendra Govindammagari, Lokesh Agarwal, Satyaki Koneru
  • Patent number: 11348197
    Abstract: A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. Cost indication logic obtains a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing rendered image values for a region of the rendered image corresponding to the set of one or more tiles. The image processing logic processes rendered image values for regions of the rendered image. The computing system causes the image processing logic to process rendered image values for regions of the rendered image in dependence on the cost indications for the corresponding sets of one or more tiles.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: May 31, 2022
    Assignee: Imagination Technologies Limited
    Inventors: John W. Howson, Richard Broadhurst, Steven Fishwick
  • Patent number: 11327947
    Abstract: Systems, computer program products, and methods are described herein for identifying, tagging, and monitoring data flow in a system environment. The present invention may be configured to receive data sets generated by applications for storage in data structures, generate unique identifiers for the data sets, and add the unique identifiers to the data sets. The present invention may be further configured to monitor, based on the unique identifiers, access to and movement of the data sets, generate, based on monitoring the access to and the movement of the data sets, flow data, and generate, based on the flow data, a data flow model. The present invention may be further configured to provide, to a user device, a graphical user interface for display by the user device, where the graphical user interface includes information based on the data flow model.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: May 10, 2022
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Mark Earl Brubaker, Elisabeth Loeber Shore
  • Patent number: 11327640
    Abstract: Systems, methods, and devices can allow applications to provide complication data to be displayed in display of an electronic device. A client application can create a data object according to a template to efficiently select how the data object is to be displayed. For example, a complication controller on the electronic device can receive new data and determine which template to use. The data object can be sent to a display manager that can identify the selected template and display the data according to the template.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: May 10, 2022
    Assignee: APPLE INC.
    Inventors: Eliza C. Block, David A. Schimon, Eric Lance Wilson, Joshua H. Shaffer, Paul W. Salzman, Christopher C. Jensen, Timothy C. Lee, Daniel B. Pollack, Alexander Ledwith, Kevin Will Chen, Lawrence Y. Yang, Alan C. Dye
  • Patent number: 11322119
    Abstract: A semiconductor device includes a processor configured to perform a rendering operation of an image frame to acquire rendering data, and write the acquired rendering data on a memory device, and a display controller configured to perform a read operation of the memory device on which the rendering data is written, to acquire image data. The semiconductor device further includes a micro-sequencing circuit configured to transmit a start signal to the display controller, based on a degree of execution of the rendering operation. The display controller is further configured to, based on the transmitted start signal, start the read operation.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Chul Yoon, Seong Woon Kim, Hyeong-Seok Kim, Kil Whan Lee
  • Patent number: 11321907
    Abstract: A system and a method are disclosed that optimizes a graphics driver. The system may be embodied as a computing device that includes a storage that is internal to the computing device, a graphic processing unit that includes a driver and a controller. The controller may be configured to run a daemon process that optimizes a shader and/or a shader pipeline for an application that is resident on the computing device when the computing device is not running the application and stores at least one optimization for the shader in the storage. The at least one optimization may be based on the application. The daemon process may further receive a request from the driver of the GPU for an optimization for the shader/shader pipeline during a runtime compilation of the shader and provide the at least one optimization to the driver of the GPU from the storage.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: May 3, 2022
    Inventors: Gabriel T. Dagani, Raun M. Krisch, Zachary Neyland, Robert Metzger, David C. Tannenbaum