Abstract: Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the redundant memory interface may be individually enabled and disabled. If a line in the additional interface is enabled, it and its corresponding line in the first interface drive a reduced load and may operate at the higher 1T data rate. If a line in the additional interface is disabled, then its corresponding line in the first interface drives a higher load and may operate at the slower 2T data rate. In either case, the operating speed of the interface may also be considered in determining whether each line operates with 1T or 2T timing.

Abstract: An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: A method and apparatus for generating hierarchical depth culling characteristics includes determining a first minimum depth value and a first maximum depth value for a first graphical element. The graphical element may be a primitive. The first minimum depth value may be a minimum Z-plane depth of a pixel within the primitive and a first maximum depth value is a maximum Z-plane value for a pixel within the primitive. The method and apparatus further includes determining a second minimum depth value and a second maximum depth value for a second graphical element, which may be a tile. The method and apparatus further includes calculating an intersection depth range having an intersection minimum depth value and an intersection maximum depth value based on the intersection of the first minimum depth value and the first maximum depth value and the second minimum depth value and the second maximum depth value.

Abstract: The present invention aims at, as to a drawing apparatus that stores an image in the frame memory via the cache memory, shortening the time period required for storing an entire image data in the frame memory. In the case where the frame memory is sectionalized in increments of the unit of pixels burst-transferred from the cache memory to the frame memory when partial data pieces of the image data to be eventually stored in the frame memory are stored in the cache memory, the drawing apparatus stores pixel data pieces for each sectionalized area in the cache memory in a manner that the cache memory needs to access the frame memory only once for each sectionalized area.

Abstract: Technologies are described herein for emitting raster and vector content from a single software component. An application program maintains an in-memory representation of a document in an intermediate format. When the application program needs to render the document, it determines whether the target device is a raster or a vector device. The application program then utilizes a single software component to render the document for the target device. The application program provides an instruction to the software component as to whether the in-memory representation should be rendered as vector content or as raster content. In response to receiving the instruction, the software component retrieves the in-memory representation and renders it according to the instruction received from the application program. The rendered content is then provided to the target device.

Abstract: The present invention provides a data processing apparatus and method for merging secure and non-secure data. The apparatus comprises at least one processor operable to execute a non-secure process to produce non-secure data to be included in an output data stream, and to execute a secure process to produce secure data to be included in the output data stream. A non-secure buffer is provided for receiving the non-secure data produced by the non-secure process, and in addition a secure buffer is provided for receiving the secure data produced by the secure process, the secure buffer not being accessible by the non-secure process. An output controller is then arranged to read the non-secure data from the non-secure buffer and the secure data from the secure buffer, and to merge the non-secure data and the secure data in order to produce a combined data stream, the output data stream then being derivable from the combined data stream.

Abstract: A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub.

Abstract: An image rendering method includes the following steps. Firstly, a source image is provided. Then, raster operations (ROPs) are performed on the source image by a first bit operating engine to obtain ROP values, and the source image are divided into at least one first region and at least one second region. Then, a first operation is performed on the first region by the first bit operating engine and a render process is executed, thereby generating first bit image data. Then, a second operation is performed on the second region by a second bit operating engine and a render process is executed, thereby generating second bit image data. Afterwards, the second bit image data of the second region are converted into first bit image data of the second region according to a screening table between the first bit operating engine and the second bit operating engine.

Abstract: A rasterizing device is provided with a first storage area capable of storing a downloaded DL object, and a rasterizer that creates bit-mapped data in band units by rasterizing data.

Abstract: A method for reading atoms positioned within a memory having a first memory portion and a second memory portions, comprising the steps of (a) positioning the atoms having memory addresses across the memory, (b) defining a strip across a portion of the atoms, (c) designating a first atom within the strip, (d) locating one or more second atoms to be paired with the first atom, (e) determining whether the one or more second atoms when paired with the first atom forms a legitimate pair, and (f) reading the legitimate pair from the first memory portion and the second memory portion.

Abstract: To provide an inexpensive display panel driver unit with a built-in memory, which is capable of achieving the same operation as that obtained in using a dual port memory by employing a single port RAM without reduction in an operation speed. A reservation buffer 14 for storing an address and data in a memory writing is provided. When a display reading and a memory writing occurs simultaneously and row addresses of the memory writing and the display reading agree with each other, the memory writing is executed and also read data from addresses except a write address together with write data into the write address are used as data of the display reading. Also, when the row addresses of the memory writing and the display reading are different from each other, the write address and data are stored in the reservation buffer and also the display reading is executed. The similar mediation is applied in executing the reserved writing.

Abstract: A multimedia presentation apparatus and method by which a presenter is freed from the requirement of having or providing or transporting a supporting computer system such as the notebook or laptop system by the incorporation of computing capability and an accessible data port into the housing of the apparatus through which an executable data file may be delivered to cause generation of the desired presentation.

Abstract: Image data storage areas of a plurality of pages are allocated for each of a plurality of display planes capable of superimposed display, and display output processing is performed while switching between the image data storage areas is being performed for each display plane. In such a display system, versatile switching between image data storage areas is enabled without heavily loading a central processing unit. Attribute bits of a TRAP command indicating the termination of drawing of one display plane are provided with display switching enable bits indicating whether to perform switching between image data storage areas for each display plane. For display planes corresponding to the display switching enable bits of “1”, switching to an image data storage area from which image data is read is performed at timing synchronous with a next vertical synchronous signal.

Abstract: A computer display apparatus includes first and second display units operatively coupled to a display controller. The display controller receives imaging instructions for images and display mode instructions for displaying the images, and causes the display units to independently generate images from the imaging instructions according to the display mode instructions. The display controller may include a display processor programmed to generate pixel data according to the imaging instructions, and first and second refresh outputs programmed to independently generate image displays from the manipulated pixel data on the first and second display units in first and second display modes, respectively. A display re-mapper may manipulate the pixel data according to display mode instructions. A display memory fetcher may manipulate pixel data according to display mode instructions in response to a request for pixel data from the first and second refresh outputs independently.

Abstract: When a contention is detected between a memory write address and a display read address in a memory circuit which stores display data, a host retry pulse generating circuit generates a display read signal and a display line data transfer signal based on a memory write clock, and supplies these to the memory circuit while supplying the display line data transfer signal to a line latch circuit. Alternatively, upon detection of the contention above, a same line re-display read processing circuit performs same line re-display read processing without moving to the next line, and supplies a display read signal and a display line data transfer signal to the memory circuit while supplying the display line data transfer signal to the line latch circuit.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: A method for accessing a frame memory integrated within a display panel driver driving a display panel is composed of serially performing write operations for writing sub-field data of a pixel line within the display panel for a plurality of sub-fields into the frame memory, and serially performing read operations for reading sub-field data of a plurality of pixel lines for a sub-field from the frame memory. At least two of the write operations are allowed to be performed between adjacent two of the read operations.

Abstract: A display driver, electro-optical device and electronic appliance are provided that make unnecessary processing that calculates positions in a RAM where display data is to be written according to a mounting state thereof. A display driver includes a mounting state setting register in which mounting state setting data showing a mounting state of the display driver is set, a RAM that stores display data, a row scanning flag generation circuit that generates a row scanning flag showing a scanning direction of row addresses based on the mounting state setting data, a row address decoder that decodes row addresses in accordance with the scanning direction designated by the row scanning flag, a column address decoder that decodes column addresses, a display address decoder that decodes display addresses, and a driving circuit that drives a display section based on display data read from the RAM in accordance with a decoding result of the display address decoder.

Abstract: In a passive pixel data handling system, pixel data may be transferred to a transfer function, at a given address range. The transfer function may perform a transformation and readdress the pixel data. For example, the data may be received through a media port target which transfers the pixel data to a transfer function located at an address range in virtual memory. Each transfer function may readdress the pixel data and forward it to a media port write back engine or to the memory address range of another transfer function.

Abstract: The picture drawing method is in a graphics computer, a special effect device or a video game machine. Data required for picture drawing is generated by pre-processing by a pre-processor 32 based on a drawing command for drawing a picture model defined by the combination of unit figures, and pixel data is generated on the unit figure basis by texture mapping based on the generated data for drawing a picture on a frame buffer 18. The texture data required by a drawing engine 33 is transferred in the pre-processing stage from a texture area on the frame buffer 18 to a texture cache 33F, and the pre-processor 32 and the drawing engine 33 are operated in pipelining. This enables texture mapping or MIP mapping without halting picture drawing, while reducing the number of times texture memory accessing and the accessed time for raising the overall picture drawing speed.

Abstract: An image data processing system with a memory performing burst read/write operations. The memory includes a memory cell array provided with memory cells arranged in a plurality of rows and a plurality of columns. The image data processing system further includes a controller for controlling an operation of reading/writing the image data from/to the memory. The controller divides the image data into a plurality of segments when a horizontal size of the image data is larger than a column width of the memory. An (I+1)-th (where I is a positive integer) segment includes a last burst data of an I-th segment, or the I-th segment includes a first burst data of the (I+1)-th segment. The respective segments correspond to the plurality of rows of the memory.

Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

Abstract: A visual display is provided on a data processing apparatus by storing and retrieving display information. The display information is stored by receiving write access addresses (33), translating the write access addresses into write memory addresses (15) and using the write memory addresses to store the display information (11). The read operation includes providing read access addresses (37), translating the read access addresses into memory read addresses (19) and using the memory read addresses to retrieve the display information (11).

Abstract: A dual-mode dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM). An exemplary DDR SDRAM/SGRAM comprises a single memory device, which itself comprises a memory array including a quad-bank DRAM and a logic circuitry. The logic circuitry is coupled to the memory array and is configurable to operate the single memory device in a first mode and a second mode. The first mode may include a delayed lock loop (DLL) capability while the second mode may include a non-DLL capability.

Abstract: A dynamically configurable portion of a cache shared between central processing and graphics units in a highly integrated multimedia processor is engaged as a secondary level in a hierarchical texture cache architecture. The graphics unit includes a small multi-ported L1 texture cache local to its 2D/3D pipeline that is backed by the relatively large, single ported portion of the shared cache. Leveraging the shared cache as a secondary level texture cache reduces system memory bandwidth and die size without significant sacrifice in performance.

Abstract: A circuit for outputting area pattern bits from an area pattern array. The circuit includes a first stage, second stage and third stage. The first stage is configured to output N adjacent scan lines from a 2N×2N area pattern array based on a first address. N is a positive integer. The second stage is configured to receive the N adjacent scanlines and to select an N×N block from the N adjacent scanlines based on a second address. The third stage is configured to (a) select an (N/2)×N region of bits from the N×N block and load bits of the (N/2)×N region into a set of pixel tag outputs in a first mode, and (b) select an N×(N/2) region of bits from the N×N block and load bits of the N×(N/2) region into the set of pixel tag outputs in a second mode.

Abstract: A graphics controller for preparing data to be presented on a display through an interlaced scan is provided. The graphics controller includes a memory and a line buffer adapted to receive video data. Data arrangement circuitry in communication with the line buffer is included. The data arrangement circuitry is configured to process the received video data in order to store the received data in the memory as an even segment and a corresponding odd segment, the even segment associated with data from a line of an even field, the odd segment associated with data from a line of an odd field, the even segment and the corresponding odd segment defining a pixel of data. A single pipe buffer configured to retrieve the even segment and the corresponding odd segment in a single memory access to the memory is included. A system using the graphics controller and a method of storing and retrieving pixel data from memory are also provided.

Abstract: A graphics system may include a frame buffer, a processing device coupled to output data, a multipurpose memory device that includes a plurality of storage locations and is coupled to store data output from the processing device, and a multipurpose memory controller coupled to the multipurpose memory device. The multipurpose memory controller may be configured to allocate a first plurality of the storage locations to a first image buffer configured to store image data, a second plurality of the storage locations to a first texture buffer configured to store texture data, and a third plurality of the storage locations to a first accumulation buffer configured to store accumulation buffer data. The multipurpose memory device may be configured to include a first image buffer, a first texture buffer, and a first accumulation buffer at the same time.

Abstract: A system is provided for storing pixel data associated with a predetermined pixel region. The system is configured to store pixel data in a predetermined block of memory along with a fill check bit indicative of whether or not values for each pixel within the pixel region are the same as a predetermined reference pixel. The system also provides for the generation of a stream of pixel data corresponding to a pixel region by outputting a value for a pixel within the region that is equal to the reference pixel when the fill check bit is set.

Abstract: A display control apparatus contains a video memory, a video memory controller, a color palette memory and a color palette replacer signal generator. The video memory stores display data that are read from a CD-ROM and contain header data (HA-HD), palette data (P0-P2) and bitmap data (BA-BD) in connection with four planes which are combined together to form one frame of picture. The header data contain a color palette pointer (CPP) and a color palette replacer instruction (CPP31) with respect to each of the planes. The video memory controller reads the palette data and bitmap data from the video memory in accordance with addresses designated by the header data. The color palette replacer signal generator generates a color palette replacer signal (COL) based on the header data so as to make determination whether to replace contents of color palettes with respect to the planes respectively.

Abstract: A memory device having multiple interfaces is described. The memory device may be configured to operate with different interfaces using configuration circuitry in the device that enables switching between the multiple interfaces.

Abstract: This invention provides an image display apparatus for displaying data stored in a random access memory (RAM) such as LCD, more specifically a display driver achieving easy and flexible display control such as scroll in a display screen without increasing load on CPU and an image display apparatus including the same.

Abstract: A data storage device having a fixed device architecture capable of operating in a first capacity mode or in a second capacity mode, and capable of switching between that first capacity mode and that second capacity mode. In certain embodiments, the first capacity mode utilizes a 22 bit blockid format and the second capacity mode utilizes a 32 bit blockid format. In other embodiments, the first capacity mode utilizes a 32 bit blockid format and the second capacity mode utilizes a 22 bit blockid format. A data storage device comprising a computer useable medium having computer readable program code disposed therein for recording information in alternative information storage architectures. A data storage and retrieval system which includes one or more of Applicants' data storage devices. A computer code product comprising a data management system which supports the capability to record information on a data storage medium using alternative information storage architectures.

Abstract: A system and method are disclosed for rendering polygons. In some embodiments, parameter values may be rendered for only one sample position of multiple neighboring sample positions. The parameter values rendered for the one sample position may then be stored in multiple memory locations that correspond to the multiple neighboring sample positions. In some embodiments, storing parameter values in multiple memory locations may be achieved in a single write transaction. In some embodiments, utilization of a method for storage of a rendered sample to multiple memory locations may be subject to a specified test. The method may calculate a value needed for the specified test from vertex data and compare the calculated value with a specified limit. In some embodiments, a multiple storage mode may only be utilized for polygons greater than a certain size.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.

Abstract: In accordance with a first mode of operation of the present invention, a portrait image is received from a system device. The portrait image is translated and stored within the graphics engine memory such that it can be displayed on a landscape monitor that has been rotated 90 degrees. Likewise, when portrait data stored within the memory is sent to the system it is translated such that it is sent back in the same format received by the system. In a second mode of operation in accordance with the present invention, a landscape image received by the graphics adapter is stored in the graphics adapter memory without any translation.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels for one frame is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. While data is being stored, data for pixels from another frame is retrieved from another two memory devices. The banks of devices alternate between storing and retrieving with each frame.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer.

Abstract: A graphic interface device produces a video signal for a display such that the user may select between landscape and portrait image display modes. The graphic interface device has a pixel data memory array from which a video output signal is derived. A primary graphics engine renders graphics in a landscape orientation in conjunction with a frame buffer. The primary landscape graphics engine stores rendered graphics to the pixel data memory array and also copies selected graphics in data blocks within the frame buffer called surfaces. In order to provide other display modes to display images in different physical orientations, a mode control is provided in conjunction with a rotated pixel data array buffer to facilitate the rendering of portrait oriented graphics by the primary landscape graphics engine. In addition, to facilitate the efficiency and speed of rendering portrait oriented graphics, a secondary portrait graphics engine is provided.

Abstract: A projection display apparatus which display a projected image and may be free from connection with a computer. The projection display apparatus carries out processing with information stored in a portable memory and includes a memory controller that reads out the information stored in the portable memory; an image processing section that prepares display image data. The display image data represents an image to be displayed from the image data stored in the portable memory according to an instruction of a processing program that is read from the portable memory and represents a series of processing steps to be executed by the projection display apparatus. An electro-optic device then forms image light in response to the display image data, and an optical system projects the image light to display the image.

Abstract: A method of linking controlled vocabulary data to a computer application includes the steps of invoking a command on a graphical user interface of the application to activate a controlled vocabulary display program which contains a controlled vocabulary, selecting terms of interest in the controlled vocabulary, closing said display program, passing data relating to said selected terms of interest to the computer application, and rendering the controlled vocabulary data in a display of the computer program.

Abstract: A dual-mode dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM). An exemplary DDR SDRAM/SGRAM comprises a single memory device, which itself comprises a memory array including a quad-bank DRAM and a logic circuitry. The logic circuitry is coupled to the memory array and is configurable to operate the single memory device in a first mode and a second mode. The first mode may include a delayed lock loop (DLL) capability while the second mode may include a non-DLL capability.

Abstract: Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be “tossed” and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixel's BEN.

Abstract: A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.

Abstract: A request for video or graphics data is made to a memory controller. When the memory controller determines a translation of the data must first be made, a request is made to a translator. The translator either translates the address or requests translation information from the memory controller. The memory controller accesses memory based upon the translator request. If the request is for translation data the results are tagged for the translator. If the translator request is for the translated address, the results are tagged for the original request.

Abstract: A buffer facilitates reordering of incoming memory access commands so that the memory access commands may be associated automatically according to their row/bank addresses. The storage capacity in the buffer may be dynamically allocated among groups as needed. When the buffer is flushed, groups of memory access commands are selected for flushing whose row/bank addresses are associated, thereby creating page coherency in the flushed memory access commands. Batches of commands may be flushed from the buffer according to a sequence designed to minimize same-bank page changes in frame buffer memory devices. Good candidate groups for flushing may be chosen according to criteria based on the binary bank address for the group, the size of the group, and the age of the group. Groups may be partially flushed. If so, a subsequent flush operation may resume flushing a partially-flushed group when to do so would be more beneficial than flushing a different group chosen solely based on its bank address.

Abstract: A dual-mode dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM). An exemplary DDR SDRAM/SGRAM comprises a single memory device, which itself comprises a memory array and a logic circuitry. The logic circuitry is coupled to the memory array and is configurable to operate the single memory device in a first mode and a second mode. The first mode may include a delayed lock loop (DLL) capability while the second mode may include a non-DLL capability.

Abstract: A method, apparatus and article of manufacture are provided for sequencing graphics processing in a transform or lighting operation. A plurality of mode bits are first received which are indicative of the status of a plurality of modes of process operations. A plurality of addresses are then identified in memory based on the mode bits. Such addresses are then accessed in the memory for retrieving code segments which each are adapted to carry out the process operations in accordance with the status of the modes. The code segments are subsequently executed within a transform or lighting module for processing vertex data.