Abstract: An Electronic Display Board for an automobile has a programmable display capable of being removable secured to an interior surface of an automobile. The angle of the frame may be adjusted by a mounting frame having a plurality of securable positions.

Abstract: A file management device comprising a memory; and a processor coupled to the memory and the processor configured to stores a feature included in a data file and a tag provided to the data file in association with each other as a provision rule, adds a tag to a newly input data file based on the stored provision rule, and displays the stored provision rule. The processor is further configured to displays the provision rule in an editable state by using a character string.

Abstract: A current limiting circuit is a circuit that receives a video signal for a display panel including pixels, and limits current consumption of the pixels. The current limiting circuit includes: a first gain calculation circuit that calculates a first gain for multiplying with the video signal, based on first power consumption that is power consumption of the pixels corresponding to the video signal; a second gain calculation circuit that calculates a second gain for multiplying with the video signal, based on the first power consumption and a rate of change of the first power consumption; a gain selection circuit that selects one of the first gain and the second gain as a gain by which the video signal is to be multiplied; and a gain multiplication circuit that multiplies the video signal by the gain.

Abstract: A display device includes a shift controller which generates an output image by shifting an input image within a shift range; and pixels which displays the output image. The shift controller sets the shift range to a first range when the input image is a moving image, and sets the shift range to a second range smaller than the first range when the input image is a still image.

Abstract: Errors in a blended stream that would result in non-display or obscuring of a live video stream from a medical device may be automatically detected, and a failover stream corresponding to the first live video stream may be displayed to medical personnel. For example, one or more second input streams that are being blended may contain no data or invalid data which may result in the blended stream not displaying (or obscuring) the live video stream (if the blended were displayed). Switching from blending to a failover buffer may occur within the time to process a single video image frame. Upon detection (prior to display) that the blended stream would not display the live video stream, display of the live video stream from the failover buffer may be initiated. Other aspects are also described and claimed.

Abstract: A computing system includes a storage system configured to store data, and a host configured to compress a data block of a preset size loaded to a memory, generate a merged block of the preset size by merging a compressed block corresponding to the data block, an identifier of a node block referring the data block, and an offset indicating an index of the data block among at least one data block referred by the node block, and provide the merged block to the storage system.

Abstract: Data compression techniques are described for saving memory space by using fewer bits to store information while achieving high fidelity. A data set may be partitioned into a plurality of regions. Locally varying numerical ranges of data values (e.g., the minimum and maximum extents) may be determined for the plurality of regions. The data in the individual regions may be encoded using a lower number of bits as interpolation values in reference to the local extents rather than being encoded using a higher number of bits as absolute values. Where there are multiple channels of data in the regions, the number of available bits for encoding the data may be dynamically allocated per region based on the relative degrees of variance in data among the multiple channels.

Abstract: Embodiments include herein are directed towards a double data rate (“DDR”) controller system. Embodiments may include a plurality of read data buffers, wherein each of the plurality of read data buffers is configured for read data storage and is of a same size. Embodiments may further include a port read response queue that stores information corresponding to an incoming read and a command queue configured to receive read data buffer state information from the port read response queue. Embodiments may also include a read data buffer allocation tracker configured to track a state of each of the plurality of read data buffers.

Abstract: Video coding using tiling may include encoding a current frame by identifying a tile-width for encoding a current tile of the current frame, the tile-width indicating a cardinality of horizontally adjacent blocks in the current tile, identifying a tile-height for encoding the current tile of the current frame, the tile-height indicating a cardinality of vertically adjacent block in the current tile, and generating an encoded tile by encoding the current tile, such that a row of the current tile includes tile-width horizontally adjacent blocks from the plurality of blocks, and a column of the current tile includes tile-height vertically adjacent blocks from the plurality of blocks. Encoding the current frame may include outputting the encoded tile, wherein outputting the encoded tile includes including an encoded-tile size in an output bitstream, the encoded-tile size indicating a cardinality of bytes for including the encoded tile in the output bitstream.

Abstract: Methods and systems are provided for using temporal supersampling to increase a displayed resolution associated with peripheral region of a foveated rendering view. A method for enabling reconstitution of higher resolution pixels from a low resolution sampling region for fragment data is provided. The method includes an operation for receiving a fragment from a rasterizer of a GPU and for applying temporal supersampling to the fragment with the low resolution sampling region over a plurality of prior frames to obtain a plurality of color values. The method further includes an operation for reconstituting a plurality of high resolution pixels in a buffer that is based on the plurality of color values obtained via the temporal supersampling. Moreover, the method includes an operation for sending the plurality of high resolution pixels for display.

Abstract: A wearable computing device includes an outer covering, a housing, an electronic display configured to display an image, and a display drive integrated circuit (DDIC) comprising a processor and a memory device. The memory device(s) includes a blanking time programmed therein based on one or more parameters of the image and/or the DDIC, which generally refers to the time period in which the DDIC receives pixel data of the image from an external controller. The memory device stores instructions that when executed by the processor cause the processor to perform operations, including receiving an indication to rotate the image by a certain angle, upon receipt of the indication, starting to receive a transmission of the pixel data of the image from the external controller, and completing the transmission of the pixel data of the image during the blanking time and before the DDIC displays the image on the electronic display so as to avoid a tearing effect of the image on the electronic display.

Abstract: A data processing system, which performs a neural network operation in response to a request from a host, comprising: a controller configured to receive control information and the input data from the host and to generate the output data by performing an operation on the input data and the weight, the control information including a scheme for storing a parameter including input data, output data, and a weight and a scheme for reusing the weight; and a memory device configured to store the weight according to control of the controller as the weight is transmitted from the host, wherein the controller includes an address converter configured to map a physical address provided from the host to a memory address based on the parameter storing scheme and the weight reusing scheme so that a bandwidth of a reading operation of the weight is maximized.

Abstract: The disclosure relates to a method for controlling an operation list, including: obtaining a remaining space between a target operation item and a bottom of a display region, of a display of a device, when the target operation item is located at a preset position; obtaining a size of a current list viewport of the operation list; extending the size of the current list viewport based on the remaining space to generate an extended current list viewport; laying out the operation list based on the extended current list viewport to obtain a size of a next operation item of the target operation item; and determining a display position of the target operation item based on the size of the next operation item and the remaining space.

Abstract: In one embodiment, a display, a storage, and a controller which executes a job of image processing based on a setting value are provided, and the controller stores, as setting history information, the setting value of the executed job in the storage; displays, on the display, a selection screen to select the setting history information stored in the storage; and executes, when the job based on the setting history information received via the selection screen is to be executed, confirmation processing according to the state of user authentication.

Abstract: A method for execution by a temporary ingress storage system includes receiving a set of records to be processed for long-term storage. The set of records are temporarily stored in a set of memory resources of the temporary ingress storage system during a first temporal period. Execution of a query is facilitated by accessing a subset of the set of records from at least one memory resource of the set of memory resources during the first temporal period. The set of records are processed to generate a set of segments for long-term storage. Migration of the set of records from the temporary ingress storage system to a long-term storage system for during a second temporal period that begins after the first temporal period has elapsed by sending the set of records to the long-term storage system.

Abstract: Technologies for media management for column-based memory systems include a memory controller including an indirection table. The memory controller receives a memory access to a column-addressable memory indicative of a memory row address. The memory controller determines a logical sub-block identifier based on the memory row address and looks up a physical sub-block identifier in the indirection table. The memory controller issues a redirected memory access indicative of the physical sub-block identifier to the column-addressable memory. The memory access may include a column read. The memory controller may perform a media management operation by copying or moving data from a source physical sub-block to a destination physical sub-block. The memory controller updates the indirection table with the destination physical sub-block for the associated logical sub-block identifier. Other embodiments are described and claimed.

Abstract: The present disclosure provides a method and device for switching a display channel, a display driving device and a display device. The method includes: sending a first switching signal to a write controller of a current display channel when a switching instruction for switching from the current display channel to a target display channel is received; acquiring a frame address in which final write operation of data is completed, and taking the frame address as a first address and a next frame address as a second address; sending a second switching signal to a write controller of the target display channel; and sending a third switching signal to a read controller.

Abstract: Described herein are, among other things, techniques, devices, and systems for streaming pixel data from a host computer to a wireless display device with low latency. In some embodiments, a user mode driver is executed in user mode of the host computer to configure a wireless network interface controller of the host computer to operate in a low latency manner. The display device may use a Forward Error Correction (FEC) algorithm to reconstruct a frame from the data packets it receives from the host computer. Also disclosed are techniques for scrambling the transmission of a series of data packets using different antenna configurations, as well as setting a modulation and coding scheme (MCS) rate based at least in part on the amount of pixel data to be transmitted to the display device. The display device may comprise a head-mounted display (HMD) that renders virtual reality (VR) game imagery.

Abstract: A display driving circuit according to an example embodiment of the inventive concept is disclosed. A display driving circuit may include an interface configured to receive a synchronization packet and image data from the outside; a memory configured to receive the image data from the interface in the command mode; a synchronization controller configured to receive the synchronization packet and generate a flag control signal and an internal synchronization signal; a flag generator configured to generate a first flag signal and a second flag signal; and an image controller configured to receive the image data from the memory in the command mode, receive the image data from the interface in the video mode, wherein the synchronization controller is configured to calculate a delay time between a generation time of the first flag signal and a reception time of the synchronization packet, and is configured to adjust a generation time of the second flag signal.

Abstract: The present disclosure includes apparatuses and methods for in-memory data switching networks. An example apparatus includes an array of memory cells. Sensing circuitry is selectably coupled to the array of memory cells. An input/output (I/O) line is shared as a data path for in-memory data switching associated with the array. An in-memory data switching network is selectably coupled to the respective shared I/O line. A controller is configured to couple to the in-memory data switching network and direct enablement of a switch protocol.

Abstract: A graphics processing engine has a geometry shading stage having two modes of operation. In the first mode of operation, each primitive output by the geometry shading stage is independent, whereas in the second mode of operation, connectivity between input primitives is maintained by the geometry shading stage. The mode of operation of the geometry shading stage can be determined based on the value of control state data which may be generated at compile-time for a geometry shader based on analysis of that geometry shader.

Abstract: Video coding using tiling may include encoding a current frame by identifying a tile-width for encoding a current tile of the current frame, the tile-width indicating a cardinality of horizontally adjacent blocks in the current tile, identifying a tile-height for encoding the current tile of the current frame, the tile-height indicating a cardinality of vertically adjacent block in the current tile, and generating an encoded tile by encoding the current tile, such that a row of the current tile includes tile-width horizontally adjacent blocks from the plurality of blocks, and a column of the current tile includes tile-height vertically adjacent blocks from the plurality of blocks. Encoding the current frame may include outputting the encoded tile, wherein outputting the encoded tile includes including an encoded-tile size in an output bitstream, the encoded-tile size indicating a cardinality of bytes for including the encoded tile in the output bitstream.

Abstract: The disclosure relates to a display method and a display system. The display method includes: connecting a plurality of display devices in series with each other, the plurality of display devices including a main display device and at least one slave display device, the main display device having EDID; setting the connection order of the display device; correspondingly changing the EDID of the main display device according to the connection order of the display device; configuring the main display device to receive the display image according to the changed EDID; and configuring the display device to perform an image segmentation operation on the display image according to the connection order to respectively display multiple segmented regions of the display image.

Abstract: There is provided an audio information providing system that can solve the problem with the audio lag and includes navigation with higher accuracy. The audio information providing system is an audio guidance system including an audio output device that is worn in the ear of a user and an information processing terminal that is communicatively connected to the audio output device. The audio output device includes: an audio output unit configured to output audio to the ear of the user; and a detection unit configured to detect the direction of the head of the user.

Abstract: In some embodiments, an apparatus includes a volatile memory, a non-volatile memory, a first processor coupled to the non-volatile memory and configured to receive a data set associated with an object and user information associated with a spatial position of a user in a multi-user virtual (IMVR) environment, and a second processor coupled to the volatile memory, the second processor configured to render an instance of the portion of the object in the IMVR environment from a perspective of the user based on the spatial position of the user. The first processor is configured to generate a look-up table (LUT) based on a set of inputs received from a user. The second processor is configured to render, based on the LUT and information related to a manipulation by a user, an updated instance of the portion of the object that manifests an effect of the manipulation in the IMVR environment.

Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.

Abstract: Methods and systems for providing feedback during a medical procedure are provided. A saved optical image of a field of view (FOV) of a site of the medical procedure is obtained along with a live optical image of the FOV of the site during the medical procedure. Navigational information relative to the site of the medical procedure is determined. The navigational information is then mapped to a common coordinate space, to determine the navigational information relative to the FOV of the saved and live optical images of the surgical site. Virtual representations of the navigational information is overlaid on the saved and/or live optical images and displayed on at least one display.

Abstract: An image transmission apparatus includes: a processor that performs a process of generating image data and that transmits the image data to a display apparatus connected via a network; and a clock controller that receives information relating to a display mode of the display apparatus from the display apparatus and that controls a drive clock frequency of the processor based on the information.

Abstract: An adapter configured to transmit signal of the first electronic device to the second electronic device is provided. The adapter includes a first USB type-C controller, a second USB type-C controller and pleural USB type-C data transmission lanes connected to the second USB type-C controller and the first USB type-C controller. The second USB type-C controller is configured to: (1) obtain a first transmission specification supported by the second electronic device; and (2) transmit the first transmission specification to the first USB type-C controller. The first USB type-C controller transmits the first transmission specification to the first electronic device. The first electronic device transmits a control command to the first USB type-C controller according to the first transmission specification. The first USB type-C controller further uses a corresponding number of data transmission lanes according to the control command.

Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

Abstract: Hybrid rendering is described for a wearable display that is attached to a tethered computer. In one example a process include determining a position and orientation of a wearable computing device, determining a rate of motion of the wearable computing device, comparing the rate of motion to a threshold, if the rate of motion is above the threshold, then rendering a view of a scene at the wearable computing device using the position and orientation information, and displaying the rendered view of the scene.

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Abstract: A display driver includes internal oscillator circuitry, timing controller circuitry, and panel interface circuitry. The internal oscillator circuitry is disposed internal to the display driver and configured to generate an internal oscillation signal. The timing controller circuitry is configured to generate a resultant sync signal using an external sync input received from an entity external to the display driver during a first period of a frame period. The timing controller circuitry is further configured to generate the resultant sync signal using the internal oscillation signal during a second period of the frame period, the second period following the first period. The panel interface circuitry is configured to generate, based on the resultant sync signal, an emission control signal that controls emission scan driver circuitry configured to drive a plurality of emission scan lines of a display panel.

Abstract: An image processing device includes an application execution unit which executes an image processing application, an image processing circuit which performs image processing, a memory control circuit which is capable of accessing a plurality of memories and a memory allocation determination unit which determines a memory allocation of the image data on the basis of memory address management information, operation unit-specific information and application information. The application execution unit distributedly stores the image data in the plurality of memories on the basis of the memory allocation determined by the memory allocation determination unit.

Abstract: The present disclosure relates to an imaging device, an imaging method, an electronic apparatus, and an onboard electronic apparatus for suppressing the flicker caused by light sources over a wide range of frequencies. With the present technology, multiple images are captured consecutively at uneven intervals in a single-frame period of a video before being blended. This removes the flicker efficiently. The uneven capture timing in the single-frame period is made the same for multiple frames. This makes it possible to prevent low-frequency flicker from getting higher in frequency. The present disclosure may be applied to onboard cameras, for example.

Abstract: A presentation stand for enabling a mobile device to read barcodes in presentation mode includes a cradle portion that is connected to the base portion. The cradle portion is configured to hold the mobile device in a position for reading a barcode. A shield portion is attached to the cradle portion and configured to modify a field of view of a camera of the mobile device. The shield portion is also configured to modify a field of illumination of an illumination source of the mobile device. The shield portion includes a camera optic system that is at least partially aligned with the camera of the mobile device when the mobile device is held in the cradle portion. The shield portion also includes an illumination optic system that is at least partially aligned with the illumination source of the mobile device when the mobile device is held in the cradle portion.

Abstract: An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.

Abstract: A system comprising a capture device and a database. The capture device may be configured to (i) capture video, (ii) perform video analysis to extract metadata corresponding to the captured video, (iii) store the captured video data and (iv) communicate with a wireless device. The database may be configured to (i) generate search results for a user based on the metadata and (ii) provide the user (a) the metadata and (b) the video based on the search results. The metadata may be used to determine license plates present in the video. The database may provide the capture device an interrupt request to preserve a portion of the video based on the search results. The capture device may flag the portion of the video to prevent overwriting the portion of the video in response to the interrupt request.

Abstract: Disclosed is an IC firmware update method performed by an intermediary circuit. The method includes: communicating with a target circuit to enter a predetermined mode; transmitting a status response message to a host circuit in response to a status asking message of the host circuit so as to inform the host circuit of its entrance to the predetermined mode; after the transmission of the status response message, receiving a first protocol request command of the host circuit; converting the first protocol request command into N request-end unstructured vendor defined message(s) (USVDM(s)) and transmitting the N request-end USVDM(s) to the target circuit to let it execute a firmware update operation, in which the N is a positive integer; receiving N response-end USVDM(s) of the target circuit related to the N request-end USVDM(s); and converting the N response-end USVDM(s) into a first protocol response command and transmitting it to the host circuit.

Abstract: Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.

Abstract: A method is described for secure video processing. The method comprises storing an encrypted video stream (1) in a public stream buffer (2) in public memory accessible by a central processing unit (4) and allocating a private stream buffer (6) at a buffer location in private memory which is accessible by a decryption unit (10), wherein the private memory is not accessible for the central processing unit (4). The method then comprises decrypting the encrypted video stream (1) in the public stream buffer (2) to the private stream buffer (6) at the allocated buffer location (8) in private memory as an associated decrypted video stream (5); appending the allocated buffer location (8) to the public stream buffer (2); and configuring a video decoder unit (12) to read the decrypted video stream (5) from the private stream buffer (6) at the buffer location (8) for further processing.

Abstract: Methods and systems are provided for using temporal supersampling to increase a displayed resolution associated with peripheral region of a foveated rendering view. A method for enabling reconstitution of higher resolution pixels from a low resolution sampling region for fragment data is provided. The method includes an operation for receiving a fragment from a rasterizer of a GPU and for applying temporal supersampling to the fragment with the low resolution sampling region over a plurality of prior frames to obtain a plurality of color values. The method further includes an operation for reconstituting a plurality of high resolution pixels in a buffer that is based on the plurality of color values obtained via the temporal supersampling. Moreover, the method includes an operation for sending the plurality of high resolution pixels for display.

Abstract: The present disclosure provides a semiconductor package including a substrate, a display unit, a driving circuit, and at least one of memory. The substrate has a display region and a peripheral region. The display unit is disposed in the display region and electrically connects with the display unit. The memory is disposed in the peripheral region and electrically connected with the driving circuit. The driving circuit and the memory are spaced apart from each other.

Abstract: A graphics processing system has a rendering space which comprises one or more tiles. The system comprises a processing module configured to perform hidden surface removal for primitives of a tile to determine primitive identifiers identifying the primitives which are visible at each of a plurality of sample positions in the tile. A set of two or more tag buffers store the primitive identifiers determined for each of the sample positions in a tile, thereby representing overlapping layers of primitives. A tag control module controls: (i) selection of a tag buffer for the storage of each of the primitive identifiers according to the layering of the primitive identifiers stored in the tag buffers, and (ii) flushing of primitive identifiers from the tag buffers. A texturing engine applies texturing to the primitives identified by the flushed primitive identifiers.

Abstract: Techniques and apparatus to manage access to accelerator-attached memory are described. In one embodiment, an apparatus to provide coherence bias for accessing accelerator memory may include at least one processor, a logic device communicatively coupled to the at least one processor, a logic device memory communicatively coupled to the logic device, and logic, at least a portion comprised in hardware, the logic to receive a request to access the logic device memory from the logic device, determine a bias mode associated with the request, and provide the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode. Other embodiments are described and claimed.

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

Abstract: In methods and apparatuses for reducing latency in graphics processing inputs are received and a first set of frames is generated and stored. Once all of the frames in the first set of frames have been produced, they may be delivered to a GPU. Each frame is then rendered by the GPU, a latency increase resulting from storing the first set of frames is less than a decrease in overall latency resulting from avoiding thread stalls due to the GPU running out of frames to process. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Systems, apparatuses, and methods for dynamically adjusting the power consumption of prefetch engines are disclosed. In one embodiment, a processor includes one or more prefetch engines, a draw completion engine, and a queue in between the one or more prefetch engines and the draw completion engine. If the number of packets stored in the queue is greater than a high watermark, then the processor reduces the power state of the prefetch engine(s). By decreasing the power state of the prefetch engine(s), power consumption is reduced. Additionally, this power consumption reduction is achieved without affecting performance, since the queue has a high occupancy and the draw completion engine can continue to read packets out of the queue. If the number of packets stored in the queue is less than a low watermark, then the processor increases the power state of the prefetch engine(s).

Abstract: A data storage device includes a memory device and a memory controller. The memory controller selects a predetermined memory block to receive data and records multiple logical addresses in a first mapping table. The first mapping table records which logical page the data stored in each physical page of the predetermined memory block is directed to. A bit table is stored in a buffer memory and includes multiple fields. Each field records a bit value. When the memory controller writes data of a logical page that corresponds to a first logical address into the predetermined memory block, the memory controller records the first logical address in the first mapping table, converts the first logical address according to a predetermined function to generate a first field index of the bit table and sets the bit value corresponding to the first field index as a first value in the bit table.