Abstract: A data processing system can use a method of fine-grained address space layout randomization to mitigate the system's vulnerability to return oriented programming security exploits. The randomization can occur at the sub-segment level by randomizing clumps of virtual memory pages. The randomized virtual memory can be presented to processes executing on the system. The mapping between memory spaces can be obfuscated using several obfuscation techniques to prevent the reverse engineering of the shuffled virtual memory mapping.

Abstract: Methods and systems for attention-based rendering on an entertainment system are provided. A tracking device captures data associated with a user, which is used to determine that a user has reacted (e.g., visually or emotionally) to a particular part of the screen. The processing power is increased in this part of the screen, which increases detail and fidelity of the graphics and/or updating speed. The processing power in the areas of the screen that the user is not paying attention to is decreased and diverted from those areas, resulting in decreased detail and fidelity of the graphics and/or decreased updating speed.

Abstract: A system-on-chip (SoC) device includes: a display controller configured to receive a trigger signal, and to output image data based on the trigger signal; and a transceiver configured to receive a first interrupt. In a first mode, the display controller is configured to output the image data in synchronization with a pulse of the trigger signal. In a second mode, which is different from the first mode, the display controller is configured to output the image data in synchronization with a pulse included in the trigger signal only after receiving the first interrupt.

Abstract: A display device correction method is provided for correcting luminance unevenness in a display device including pixels, which are arranged in a matrix and include light-emitting elements that emit light according to a luminance signal. The method includes obtaining in advance first correction data, which includes correction data components each corresponding to a different one of the pixels and is for correcting the luminance signal. The method also includes transforming the first correction data into second correction data by decomposing the correction data components included in the first correction data into frequency components, and removing a predetermined frequency component among the frequency components. The method further includes correcting the luminance signal using the second correction data.

Abstract: A color test pattern comprising color patches can be printed together with an image (text and/or a pictures, for example) of a print job. After printing, reflections, known as flare, from the image may adversely affect measurements taken of the color patches. To help reduce the effects of flare, a determination is made prior to printing as to the layout of the color patches. The determination involves comparing the color properties of the color patches with those of the image.

Abstract: An image processing apparatus includes an extraction unit, a memory controller, and a transfer unit. The extraction unit extracts, on the basis of image information, pieces of color information having a high frequency of occurrence as color information that is necessary to perform image processing. The memory controller causes a first memory to store a color information group including the pieces of color information extracted by the extraction unit. The transfer unit transfers the color information group from the first memory to a second memory, an access time of the second memory being shorter than an access time of the first memory.

Abstract: Active gameplay of a video game on a computer gaming device is overseen by a platform-level in-game recording companion that executes separately from any of a plurality of different video games. During active gameplay of the video game, the active gameplay is continuously and automatically buffered to a temporary storage buffer. During active gameplay the computer gaming device receives a command to save a segment of the active gameplay for subsequent viewing. While displaying gameplay of the currently-executing video game, an interface for the platform-level in-game recording companion is displayed. The segment of the active gameplay is saved from the temporary storage buffer to a library of the platform-level in-game recording companion.

Abstract: An apparatus includes an integrated circuit configured to be operatively coupled to a sensor array that is configured to generate an ultrasonic wave. The integrated circuit includes a transmitter circuit configured to provide a first signal to the sensor array. The integrated circuit further includes a receiver circuit configured to receive a second signal from the sensor array in response to providing the first signal. The sensor array includes an ultrasonic transmitter configured to generate the ultrasonic wave in response to the first signal and a piezoelectric receiver layer configured to detect a reflection of the ultrasonic wave.

Abstract: When untransformed display lists are used in a tile-based graphics processing system, the processing involved in deriving sub-primitives may need to be performed in both the geometry processing phase and the rasterization phase. To reduce the duplication of this processing, the control stream data for a tile includes sub-primitive indications to indicate which sub-primitives are to be used for rendering a tile. This allows the sub-primitives to be determined efficiently in the rasterization phase based on this information determined in the geometry processing phase. Furthermore, a hierarchical cache system may be used to store a hierarchy of graphics data items used for deriving sub-primitives. If graphics data items for deriving a sub-primitive are stored in the cache, the retrieval of these graphics data items from the cache in the rasterization phase can reduce the amount of processing performed to derive the sub-primitives.

Abstract: Systems and methods for live migration are provided. A hypervisor receives a request to migrate a virtual machine from a source host machine to a destination host machine, and maps memory of the virtual machine on the source host machine to a storage device accessible by the source host machine and by the destination host machine.

Abstract: Provided are a touch display control device and an information terminal device, which are arranged so that the noise resulting from the actions for activation and display on a display panel, and the noise caused by the actions of activation and detection on a touch sensor never affects each other, and are useful for suppressing the elicitation of the difference in brightness attributed to non-display in a display frame. The information terminal device includes: a display controller operable to change start timings of display and non-display periods in a cycle of a frame synchronizing signal of a display frame, in each cycle of the frame synchronizing signal or each sequence of cycles thereof; and a touch panel controller operable to perform the activation of a touch panel and a touch detection during the non-display period.

Abstract: A method and apparatus for video encoding to generate a partitioned bitstream without buffering transform coefficient and/or prediction data for subsequent coding units are disclosed. An encoder incorporating an embodiment according to the present invention receives first video parameters associated with a current coding unit, wherein no first video parameters associated with subsequent coding units are buffered. The encoder then encodes the first video parameters to generate a current first compressed data corresponding to the current coding unit. A first memory address in the first logic unit is determined and the encoder provides the current first compressed data at the first memory address in the first logic unit.

Abstract: A memory control apparatus including: a writing unit configured to output a write request for writing to a memory and issues a first event every time a write operation of each of the first blocks is completed; a reading unit configured to output a readout request for reading of image data that has been written to the memory by the writing unit and issues a second event every time a readout operation of the second block is completed; and a controller that performs a process of incrementing a count value in response to the first event, performs a process of decrementing the count value in response to the second event, and controls whether to permit the write request and the readout request, respectively, based on the count value.

Abstract: A graphics processing system has a rendering space which comprises one or more tiles. The system comprises a processing module configured to perform hidden surface removal for primitives of a tile to determine primitive identifiers identifying the primitives which are visible at each of a plurality of sample positions in the tile. A set of two or more tag buffers store the primitive identifiers determined for each of the sample positions in a tile, thereby representing overlapping layers of primitives. A tag control module controls: (i) selection of a tag buffer for the storage of each of the primitive identifiers according to the layering of the primitive identifiers stored in the tag buffers, and (ii) flushing of primitive identifiers from the tag buffers. A texturing engine applies texturing to the primitives identified by the flushed primitive identifiers.

Abstract: An aspect of the present invention proposes a method for performing partial refresh on display panels. According to one or more embodiments of the present invention, the display panels may be implemented as self-refreshing display panels communicatively coupled with a computing device that generates graphical data for display in the display panel. To perform partial refresh, consecutive frames are compared to identify the portions of the frames with updated material. In one or more embodiments, only the pixels corresponding to the updated portion(s) are refreshed in the display panel.

Abstract: An apparatus having an interface and a circuit is disclosed. The interface may be connectable to a plurality of counters and a plurality of pipelines. The circuit may be configured to increment the counters associated with a first data unit in response to the first data unit being available in a buffer, and monitor a plurality of decrements of the counters by the pipelines. Each pipeline may decrement a respective counter when finished with the first data unit in the buffer. The circuit may also be configured to block the pipelines from processing a second data unit in the buffer until all of the counters associated with the first data unit have been decremented.

Abstract: A driving system capable of supporting multiple display modes is provided. The driving system includes a memory for storing gamma codes corresponding to various display modes, a gamma voltage generation device producing gamma voltages corresponding to the gamma codes, and a timing controller accessing the gamma codes stored in the memory and writing the gamma codes into the gamma voltage generation device according to mode switch signals. The gamma voltage generation device then produces gamma voltages corresponding to the input gamma codes during the vertical blank interval of the display device, thereby achieving display mode switch. The memory may also be integrated in the timing controller. Compared to the prior art, the driving system is compatible with various display modes with reduced cost.

Abstract: The present disclosure includes apparatuses, systems, and methods related to multiple address registers for a solid state device (SSD). An example apparatus includes a controller including a plurality of base address registers (BARs) each including same addresses for data storage in a same memory resource and an SSD that includes the same memory resource.

Abstract: A parallel processor and a method of reducing texture cache invalidation are disclosed. In one embodiment, the parallel processor includes a cache configured to receive lines of data; and a parallel execution unit associated with the cache and configured to execute parallel counterparts of an operation. The parallel counterparts, when executed, are configured to create, in the cache, corresponding aliases of a line of data pertaining to the operation such that the parallel counterparts are operable to invalidate only the corresponding aliases.

Abstract: Methods, systems, and apparatus, including an apparatus for accessing data. In some implementations, an apparatus includes address offset value elements that are each configured to store an address offset value. For each address offset value element, the apparatus can include address computation elements that each store a value used to determine the address offset value. One or more processors are configured to receive a program for performing computations using tensor elements of a tensor. The processor(s) can identify, in the program, a prologue or epilogue loop having a corresponding data array for storing values of the prologue or epilogue loop and populate, for a first address offset value element that corresponds to the prologue or epilogue loop, the address computation elements for the first address offset value element with respective values based at least on a number of iterations of the prologue or epilogue loop.

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

Abstract: Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.

Abstract: Provided is a document providing system, a providing-side apparatus, and a display-side apparatus, capable of increasing the usability. The providing-side apparatus 1 broadcasts the designated information for specifying the designated document. The display-side apparatus 2 holds the documents to be provided, and upon receiving the broadcasted document specifying information, the display-side apparatus 2 searches the held documents to retrieve a document specified by the received information, and displays the retrieved document.

Abstract: Coding techniques for a video image compression system involve improving an image quality of a sequence of two or more bi-directionally predicted intermediate frames, where each of the frames includes multiple pixels. One method involves determining a brightness value of at least one pixel of each bi-directionally predicted intermediate frame in the sequence as an equal average of brightness values of pixels in non-bidirectionally predicted frames bracketing the sequence of bi-directionally predicted intermediate frames. The brightness values of the pixels in at least one of the non-bidirectionally predicted frames is converted from a non-linear representation.

Abstract: An display driving circuit including a buffer write controller transmitting a different image frame to a first buffer or a second buffer, a buffer scan controller scanning an image frame stored in the first buffer or the second buffer on the basis of a predetermined cycle, a write signal detector controlling the buffer write controller such that a second image frame is transmitted to the second buffer after a first image frame is transmitted to the first buffer, and a scan buffer switching controller receiving an EOF (End of Frame) command indicating the completion of transmission of the first image frame to the first buffer and controlling the buffer scan controller such that the first image frame stored in the first buffer is scanned after the image frame previously stored in the second buffer is scanned.

Abstract: An image processor, a display device including the same, and a method for driving display panel using the same are disclosed. In one aspect, the display device includes an image shifter configured to shift a data signal by at least one pixel based at least in part on a shift start signal and output the shifted data signal and a shift direction signal. The display device also includes an image buffer configured to output current data and previous data based at least in part on the shifted data signal and the shift direction signal. The display device also includes an image mixer configured to mix the current data and the previous data over M frames starting at a start frame when the shift start signal is received and output image data, M being a natural number.

Abstract: A display device is disclosed, which may supply gate signals to allow pulse widths of gate signals supplied to adjacent gate lines to be overlapped with each other and at the same time minimize cost increase caused by increase of the number of line memories. The display device comprises a display panel, a gate driver and a timing controller. The display panel includes gate lines, data lines and pixels provided at crossing areas between the gate lines and the data lines. The gate driver supplies gate signals to the gate lines. The timing controller supplies a start signal and gate clock signals for controlling an operation timing of the gate driver to the gate driver. One frame period includes an active period for supplying the gate signals to the gate lines and a vertical blank period for not supplying the gate signals to the gate lines, and the start signal is supplied within the vertical blank period.

Abstract: A method of and device for removing a processor from a low power mode. The method includes and the device provides for performing multiple processor start-up tasks in parallel. Memory interface training between the processor and memory and restoration and initialization of the processor are performed in parallel with each other and with a serial bus controller entering serial bus training to facilitate communication between the processor and a system controller.

Abstract: A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map.

Abstract: A method and system for performing general matrix-vector multiplication (GEMV) operations on a graphics processor unit (GPU) using Smart kernels. During operation, the system may generate a set of kernels that includes at least one of a variable-N GEMV kernel and a constant-N GEMV kernel. A constant-N GEMV kernel performs computations for matrix and vector combinations with a specific value of N (e.g., the number of columns in a matrix and the number of rows in a vector). Variable-N GEMV kernels may perform computations for all values of N. The system may also generate 1B1R kernels, constant-N variable-rows GEMV kernels, and variable-N variable-rows GEMV kernels. The system may generate constant-N variable-threads GEMV kernels, and variable-N variable-threads GEMV kernels. The system may also generate variable-threads-rows GEMV kernels for the set. This may include ConstN kernels (e.g., constant-N variable-threads-rows GEMV kernels), and VarN kernels (e.g., variable-N variable-threads-rows GEMV kernels).

Abstract: An image can be presented using render-tiles, which are movable rendering contexts in which multiple image-tiles can be drawn as a single image. To optimize performance, the render-tiles can be large enough to minimize the number of render-tiles necessary to present the image within the screen view of a client device, while remaining small enough to avoid memory or performance issues when panning or zooming the image. A set of active image-tiles and active render-tiles can be identified based on a specified view boundary that represents a portion of the image that is presented by a client device. The active render-tiles can be presented by the client device and the image-tiles can be drawn into the render-tiles to present the image. The render-tiles can be generated as needed and inactive render-tiles can be stored for later use or recycled.

Abstract: To prioritize repopulation of in-memory compression units (IMCU), a database server compresses, into an IMCU, a plurality of data units from a database table. In response to changes to any of the plurality of data units within the database table, the database server performs the steps of: (a) invalidating corresponding data units in the IMCU; (b) incrementing an invalidity counter of the IMCU that reflects how many data units within the IMCU have been invalidated; (c) receiving a data request that targets one or more of the plurality of data units of the database table; (d) in response to receiving the data request, incrementing an access counter of the IMCU; and (e) determining a priority for repopulating the IMCU based, at least in part, on the invalidity counter and the access counter.

Abstract: A system-on-chip (SoC) device includes: a display controller configured to receive a trigger signal, and to output image data based on the trigger signal; and a transceiver configured to receive a first interrupt. In a first mode, the display controller is configured to output the image data in synchronization with a pulse of the trigger signal. In a second mode, which is different from the first mode, the display controller is configured to output the image data in synchronization with a pulse included in the trigger signal only after receiving the first interrupt.

Abstract: Embodiments provide for a graphics processing apparatus comprising render logic to detect rendering operations that will result in framebuffer having the same data as the initial clear color value and morphing such rendering operations to optimizations that are typically done for initial clearing of the framebuffer.

Abstract: The array substrate includes a substrate and at least one display pixel arranged on the substrate. The display pixel includes a plurality of first pixels and a plurality of second pixels arranged along a row direction and a column direction. The period along the row direction or the column direction includes three display pixels. Wherein within at least one period along the row direction and the column direction, the display pixel of the first row includes one second pixel and two first pixels adjacent to the second pixel. The display pixel of the second row includes one first pixel and two second pixels adjacent to the first pixel. The display pixel of the third row includes one first pixel and two second pixels adjacent to the first pixel, and the first pixel of the third row is in different column from the first pixel of the second row.

Abstract: Embodiments of the present invention provide resource managing methods and systems. The method comprises: receiving a request to allocate resources sent from host code of an application program located on a first device; in accordance with the allocation request and a maintained mapping logic mapping available hardware resources of at least one graphics processing unit (GPU) of the first device to a unified virtual GPU resource, allocating required resources for a device code of the application program from the available hardware resources of at least one GPU of the first device; and forwarding information of the allocated resource back to the host code. The present invention can efficiently utilize GPU resources and reduce implementation costs.

Abstract: A data transfer device includes a shifter block that generates first and second input signals and first and second output signals, an input/output control block that selects the first input signal and the first output signal in correspondence to a mode signal and outputs an input control signal and an output control signal for controlling a data input/output operation, or selects the second input signal and the second output signal and outputs the input control signal and the output control signal, and a buffer block that latches first input data or second input data which have different data bit widths according to the input control signal, and outputs first output data or second output data which have different data bit widths according to the output control signal.

Abstract: Active gameplay of a video game on a computer gaming device is overseen by a platform-level in-game recording companion that executes separately from any of a plurality of different video games. During active gameplay of the video game, the active gameplay is continuously and automatically buffered to a temporary storage buffer. During active gameplay the computer gaming device receives a command to save a segment of the active gameplay for subsequent viewing. Without interrupting the active gameplay, the segment of the active gameplay is saved from the temporary storage buffer to a library of the platform-level in-game recording companion.

Abstract: An image forming apparatus that performs image processing using information stored in a semiconductor memory includes an obtaining unit configured to obtain from the semiconductor memory a block size used for data reading and writing, and a management unit configured to discretely arrange and manage, with respect to a specific region set in the semiconductor memory, use-based information to be updated along with execution of the image processing, included in the stored information, according to the obtained block size.

Abstract: Embodiments of the present invention are directed to improving the performance of anti-aliased image rendering. One embodiment is a method of rendering a pixel from an anti-aliased image. The method includes: storing a first set and a second set of samples from a plurality of anti-aliased samples of the pixel respectively in a first memory and a second memory; and rendering a determined number of said samples from one of only the first set or the first and second sets. Corresponding system and computer program product embodiments are also disclosed.

Abstract: A memory device includes a row selection unit for selecting word lines of a memory array, a column selection unit for selecting data lines of the memory array, a last address storing unit for storing a last row address and a last column address, and a selection address generating unit for providing a row selection address and a column selection address to select the word lines and the data lines. In the memory device, start row and column addresses are determined based on the first and last row addresses, the first and last column addresses, the row section address and the column selection address and forwardly or backwardly counted based on directions corresponding to image data injection directions in a display panel to which the memory device provides the image data.

Abstract: A first set of signal carriers of a plurality of signal carriers may be determined to be faulty. The first set of signal carriers may be for transmitting a first set of respective lane signals of a plurality of lane signals. A second set of signal carriers of the plurality of signal carriers may be identified as not faulty. The second set of signal carriers may be for transmitting a second set of lane signals of the plurality of lane signals. Based on the determining and identifying, one or more of the first set of lane signals may be routed from the first set of signal carriers through a first subset of the second set of signal carriers, the routing of the one or more of the first set of lane signals may cause a bandwidth capacity to increase to a highest available bandwidth.

Abstract: A display driving apparatus including a signal transmission interface, a timing control circuit and an image detection circuit is provided. The signal transmission interface is configured to receive video image data and output the video image data. The timing control circuit is configured to receive the video image data and drive a display panel based on the video image data. The image detection circuit determines whether the video image data is a static image and determines whether the display driving apparatus operates in a power-saving mode based on the determination result. Under the power-saving mode, the signal transmission interface masks a part of the video image data, so as not to output the masked video image data to the timing control circuit. Furthermore, a display driving method adapted for the foregoing display driving apparatus is also provided.

Abstract: A display (101) is controlled by a display drive signal (S2) generated based on an input signal (S1) encoding a safety-critical quantity. A checksum (S4) is computed based on the display drive signal and is used to verify the rendering process by which the display drive signal has been produced. In order for the checksum to depend on the safety-critical quantity only, the checksum is computed based on a filtered display drive signal (S3) in which pixels with a certain value have been excluded. In embodiments of the invention, safety-noncritical quantities are represented using colors that are due to be excluded. Similarly, a checksum for verifying a given quantity can be made independent of other quantities represented in adjacent screen areas by representing the latter using excluded colors. In other embodiments, pixel values corresponding to particular pixel positions may be excluded from contributing.

Abstract: An image display system is provided. The image display system includes a host, and a touch controller configured to generate touch event information corresponding to a touch signal and supply the touch event information to an accelerator, wherein the touch signal is output from a touch panel. The accelerator is configured to generate, based on the touch event information supplied from the touch controller, output image data corresponding to a touch event. The image display system further includes a display controller configured to supply the output image data generated by the accelerator to a display panel.

Abstract: Techniques are disclosed for rendering scene volumes having scene dependent memory requirements. A image plane used to view a three dimensional volume (3D) volume into smaller regions of pixels referred to as buckets. The number of pixels in each bucket may be determined based on an estimated number of samples needed to evaluate a pixel. Samples are computed for each pixels in a given bucket. Should the number of samples exceed the estimated maximum sample count, the bucket is subdivided into sub-buckets, each allocated the same amount of memory as was the original bucket. Dividing a bucket in half effectively doubles both the memory available for rendering the resulting sub-buckets and the maximum number of samples which can be collected for each pixel in the sub-bucket. The process of subdividing a bucket continues until all of the pixels in the original bucket are rendered.

Abstract: Methods and systems for implementing a secure migratable architecture are disclosed. One method includes, upon initiating execution of a process, allocating a portion of a memory for use by the process during execution, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the process is executed. The method also includes executing the process hosted by the operating system, wherein the firmware environment manages the portion of the memory using one or more area descriptors to describe the portion of the memory, each of the one or more area descriptors defining to the firmware environment a base address at which a memory area is located, the base address translated to an address in the memory managed by the operating system, the memory area being within the portion of memory allocated for use by the process.

Abstract: Methods and systems for implementing a secure migratable architecture having improved performance features over existing virtualization systems are disclosed. One method includes allocating a portion of a memory for use by a process, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the process is executed. The method includes associating area descriptors with each of a plurality of memory areas within the portion of the memory used by the process, and receiving a request within the firmware environment to store data within a first memory area of the plurality of memory areas, the first memory area defined by a first area descriptor of the area descriptors, the request being associated with a plurality of memory addresses within the first memory area.

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

Abstract: A method allows changing an image raster direction from an application raster direction to a screen raster direction, in-flight while pixel values of an image are transferred successively from an application output memory to a display unit. A single buffer memory array is implemented between the application output memory and the display unit. Two writing orders for cells of the buffer memory array are used in turn, each being combined with a different reading order for the cells. The method can be hardware-implemented, and is adapted for burst-handling of the pixel values.