Abstract: Methods and systems for providing feedback during a medical procedure are provided. A saved optical image of a field of view (FOV) of a site of the medical procedure is obtained along with a live optical image of the FOV of the site during the medical procedure. Navigational information relative to the site of the medical procedure is determined. The navigational information is then mapped to a common coordinate space, to determine the navigational information relative to the FOV of the saved and live optical images of the surgical site. Virtual representations of the navigational information is overlaid on the saved and/or live optical images and displayed on at least one display.

Abstract: An image transmission apparatus includes: a processor that performs a process of generating image data and that transmits the image data to a display apparatus connected via a network; and a clock controller that receives information relating to a display mode of the display apparatus from the display apparatus and that controls a drive clock frequency of the processor based on the information.

Abstract: An adapter configured to transmit signal of the first electronic device to the second electronic device is provided. The adapter includes a first USB type-C controller, a second USB type-C controller and pleural USB type-C data transmission lanes connected to the second USB type-C controller and the first USB type-C controller. The second USB type-C controller is configured to: (1) obtain a first transmission specification supported by the second electronic device; and (2) transmit the first transmission specification to the first USB type-C controller. The first USB type-C controller transmits the first transmission specification to the first electronic device. The first electronic device transmits a control command to the first USB type-C controller according to the first transmission specification. The first USB type-C controller further uses a corresponding number of data transmission lanes according to the control command.

Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Abstract: Hybrid rendering is described for a wearable display that is attached to a tethered computer. In one example a process include determining a position and orientation of a wearable computing device, determining a rate of motion of the wearable computing device, comparing the rate of motion to a threshold, if the rate of motion is above the threshold, then rendering a view of a scene at the wearable computing device using the position and orientation information, and displaying the rendered view of the scene.

Abstract: A display driver includes internal oscillator circuitry, timing controller circuitry, and panel interface circuitry. The internal oscillator circuitry is disposed internal to the display driver and configured to generate an internal oscillation signal. The timing controller circuitry is configured to generate a resultant sync signal using an external sync input received from an entity external to the display driver during a first period of a frame period. The timing controller circuitry is further configured to generate the resultant sync signal using the internal oscillation signal during a second period of the frame period, the second period following the first period. The panel interface circuitry is configured to generate, based on the resultant sync signal, an emission control signal that controls emission scan driver circuitry configured to drive a plurality of emission scan lines of a display panel.

Abstract: An image processing device includes an application execution unit which executes an image processing application, an image processing circuit which performs image processing, a memory control circuit which is capable of accessing a plurality of memories and a memory allocation determination unit which determines a memory allocation of the image data on the basis of memory address management information, operation unit-specific information and application information. The application execution unit distributedly stores the image data in the plurality of memories on the basis of the memory allocation determined by the memory allocation determination unit.

Abstract: The present disclosure relates to an imaging device, an imaging method, an electronic apparatus, and an onboard electronic apparatus for suppressing the flicker caused by light sources over a wide range of frequencies. With the present technology, multiple images are captured consecutively at uneven intervals in a single-frame period of a video before being blended. This removes the flicker efficiently. The uneven capture timing in the single-frame period is made the same for multiple frames. This makes it possible to prevent low-frequency flicker from getting higher in frequency. The present disclosure may be applied to onboard cameras, for example.

Abstract: A presentation stand for enabling a mobile device to read barcodes in presentation mode includes a cradle portion that is connected to the base portion. The cradle portion is configured to hold the mobile device in a position for reading a barcode. A shield portion is attached to the cradle portion and configured to modify a field of view of a camera of the mobile device. The shield portion is also configured to modify a field of illumination of an illumination source of the mobile device. The shield portion includes a camera optic system that is at least partially aligned with the camera of the mobile device when the mobile device is held in the cradle portion. The shield portion also includes an illumination optic system that is at least partially aligned with the illumination source of the mobile device when the mobile device is held in the cradle portion.

Abstract: An apparatus to facilitate memory tiling is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads via access to the memory and tiling logic to apply a tiling pattern to memory addresses for data stored in the memory.

Abstract: A system comprising a capture device and a database. The capture device may be configured to (i) capture video, (ii) perform video analysis to extract metadata corresponding to the captured video, (iii) store the captured video data and (iv) communicate with a wireless device. The database may be configured to (i) generate search results for a user based on the metadata and (ii) provide the user (a) the metadata and (b) the video based on the search results. The metadata may be used to determine license plates present in the video. The database may provide the capture device an interrupt request to preserve a portion of the video based on the search results. The capture device may flag the portion of the video to prevent overwriting the portion of the video in response to the interrupt request.

Abstract: Disclosed is an IC firmware update method performed by an intermediary circuit. The method includes: communicating with a target circuit to enter a predetermined mode; transmitting a status response message to a host circuit in response to a status asking message of the host circuit so as to inform the host circuit of its entrance to the predetermined mode; after the transmission of the status response message, receiving a first protocol request command of the host circuit; converting the first protocol request command into N request-end unstructured vendor defined message(s) (USVDM(s)) and transmitting the N request-end USVDM(s) to the target circuit to let it execute a firmware update operation, in which the N is a positive integer; receiving N response-end USVDM(s) of the target circuit related to the N request-end USVDM(s); and converting the N response-end USVDM(s) into a first protocol response command and transmitting it to the host circuit.

Abstract: Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.

Abstract: A method is described for secure video processing. The method comprises storing an encrypted video stream (1) in a public stream buffer (2) in public memory accessible by a central processing unit (4) and allocating a private stream buffer (6) at a buffer location in private memory which is accessible by a decryption unit (10), wherein the private memory is not accessible for the central processing unit (4). The method then comprises decrypting the encrypted video stream (1) in the public stream buffer (2) to the private stream buffer (6) at the allocated buffer location (8) in private memory as an associated decrypted video stream (5); appending the allocated buffer location (8) to the public stream buffer (2); and configuring a video decoder unit (12) to read the decrypted video stream (5) from the private stream buffer (6) at the buffer location (8) for further processing.

Abstract: The present disclosure provides a semiconductor package including a substrate, a display unit, a driving circuit, and at least one of memory. The substrate has a display region and a peripheral region. The display unit is disposed in the display region and electrically connects with the display unit. The memory is disposed in the peripheral region and electrically connected with the driving circuit. The driving circuit and the memory are spaced apart from each other.

Abstract: Methods and systems are provided for using temporal supersampling to increase a displayed resolution associated with peripheral region of a foveated rendering view. A method for enabling reconstitution of higher resolution pixels from a low resolution sampling region for fragment data is provided. The method includes an operation for receiving a fragment from a rasterizer of a GPU and for applying temporal supersampling to the fragment with the low resolution sampling region over a plurality of prior frames to obtain a plurality of color values. The method further includes an operation for reconstituting a plurality of high resolution pixels in a buffer that is based on the plurality of color values obtained via the temporal supersampling. Moreover, the method includes an operation for sending the plurality of high resolution pixels for display.

Abstract: A graphics processing system has a rendering space which comprises one or more tiles. The system comprises a processing module configured to perform hidden surface removal for primitives of a tile to determine primitive identifiers identifying the primitives which are visible at each of a plurality of sample positions in the tile. A set of two or more tag buffers store the primitive identifiers determined for each of the sample positions in a tile, thereby representing overlapping layers of primitives. A tag control module controls: (i) selection of a tag buffer for the storage of each of the primitive identifiers according to the layering of the primitive identifiers stored in the tag buffers, and (ii) flushing of primitive identifiers from the tag buffers. A texturing engine applies texturing to the primitives identified by the flushed primitive identifiers.

Abstract: Techniques and apparatus to manage access to accelerator-attached memory are described. In one embodiment, an apparatus to provide coherence bias for accessing accelerator memory may include at least one processor, a logic device communicatively coupled to the at least one processor, a logic device memory communicatively coupled to the logic device, and logic, at least a portion comprised in hardware, the logic to receive a request to access the logic device memory from the logic device, determine a bias mode associated with the request, and provide the logic device with access to the logic device memory via a device bias pathway responsive to the bias mode being a device bias mode. Other embodiments are described and claimed.

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

Abstract: Systems, apparatuses, and methods for dynamically adjusting the power consumption of prefetch engines are disclosed. In one embodiment, a processor includes one or more prefetch engines, a draw completion engine, and a queue in between the one or more prefetch engines and the draw completion engine. If the number of packets stored in the queue is greater than a high watermark, then the processor reduces the power state of the prefetch engine(s). By decreasing the power state of the prefetch engine(s), power consumption is reduced. Additionally, this power consumption reduction is achieved without affecting performance, since the queue has a high occupancy and the draw completion engine can continue to read packets out of the queue. If the number of packets stored in the queue is less than a low watermark, then the processor increases the power state of the prefetch engine(s).

Abstract: In methods and apparatuses for reducing latency in graphics processing inputs are received and a first set of frames is generated and stored. Once all of the frames in the first set of frames have been produced, they may be delivered to a GPU. Each frame is then rendered by the GPU, a latency increase resulting from storing the first set of frames is less than a decrease in overall latency resulting from avoiding thread stalls due to the GPU running out of frames to process. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller selects a predetermined memory block to receive data and records multiple logical addresses in a first mapping table. The first mapping table records which logical page the data stored in each physical page of the predetermined memory block is directed to. A bit table is stored in a buffer memory and includes multiple fields. Each field records a bit value. When the memory controller writes data of a logical page that corresponds to a first logical address into the predetermined memory block, the memory controller records the first logical address in the first mapping table, converts the first logical address according to a predetermined function to generate a first field index of the bit table and sets the bit value corresponding to the first field index as a first value in the bit table.

Abstract: A timing controller, a display apparatus, and an operation method thereof are provided. The display apparatus includes a display panel and a timing controller. The timing controller includes a refresh mark controller and a pixel controller. The refresh mark controller includes a refresh mark table, and a plurality of refresh marks in the refresh mark table correspond to a plurality of sub-regions of a display region in the display panel. The refresh mark controller determines whether the sub-regions need to be refreshed according to an image signal and responds to a specific sub-region required to be refreshed to adjust a specific refresh mark according to a mapping ratio. The pixel controller sequentially looks up whether the refresh marks in the refresh mark table are adjusted, obtains the sub-regions corresponding to the adjusted refresh marks according to the mapping ratio, and performs a pixel refresh operation to the sub-regions.

Abstract: A display apparatus has an image display unit having a plurality of arrayed pixel circuits, and an image signal compensation circuit compensating an image signal and outputs the compensated signal to the image display unit. Each of the pixel circuits has a compensating capacitor which compensates the threshold voltage of the driving transistor. The image signal compensation circuit has a compensation memory storing a compensation data for compensating the current variation of the driving transistors, a first comparison circuit which compares the image signal and first threshold value, and an arithmetic circuit compensating the image signal. When the image signal has a luminance larger than the threshold value, the compensation is performed.

Abstract: A method of super-resolution image processing. The method includes inputting first image data representative of a first version of at least part of an image with a first resolution to a machine learning system. The first image data includes pixel intensity data representative of an intensity value of at least one color channel of a pixel of the first version of the at least part of the image, and feature data representative of a value of at least one non-intensity feature associated with the pixel. The first image data is processed using the machine learning system to generate second image data representative of a second version of the at least part of the image with a second resolution greater than the first resolution.

Abstract: A memory controller circuit coupled to multiple memory circuits may receive requests to access particular locations within the multiple memory circuits. A request may be assigned a particular quality-of-service level. During operation, the memory controller circuit may reallocate the quality-of-service level of a particular request to a new quality-of-service level based on accumulated bandwidth credits associated with the new quality-of-service level.

Abstract: Various exemplary embodiments of the present disclosure relate to an apparatus and method for outputting content in an electronic device. In this case, the electronic device includes a display module, a power module configured to interrupt power supply to at least one element of the electronic device based on a control signal, and a processor. The processor may be configured to transmit to the power module the control signal for interrupting the power supply to the processor if a designated condition is satisfied, and transmit content information to the display module so that the display module displays the content information when the power supply to the processor is interrupted.

Abstract: A method of sharing content rendered on a device, including executing an application which generates audiovisual content, retrieving the application's audiovisual content from a graphics memory, and transmitting the retrieved content to a destination device via a network.

Abstract: Methods, systems, and apparatus, including an apparatus for accessing data. In some implementations, an apparatus includes address offset value elements that are each configured to store an address offset value. For each address offset value element, the apparatus can include address computation elements that each store a value used to determine the address offset value. One or more processors are configured to receive a program for performing computations using tensor elements of a tensor. The processor(s) can identify, in the program, a prologue or epilogue loop having a corresponding data array for storing values of the prologue or epilogue loop and populate, for a first address offset value element that corresponds to the prologue or epilogue loop, the address computation elements for the first address offset value element with respective values based at least on a number of iterations of the prologue or epilogue loop.

Abstract: Processing of commands at a graphics processor are controlled by receiving input data and generating a command for processing at the graphics processor from the input data, wherein the command will cause the graphics processor to write out at least one buffer of data to an external memory, and submitting the command to a queue for later processing at the graphics processor. Subsequent to submitting the command, but before the write to external memory has been completed, further input data is received and it is determined that the buffer of data does not need to be written to external memory. The graphics processor is then signalled to prevent at least a portion of the write to external memory from being performed for the command.

Abstract: Systems, apparatuses, and methods for implementing a timestamp based display update mechanism. A display control unit includes a timestamp queue for storing timestamps, wherein each timestamp indicates when a corresponding frame configuration set should be fetched from memory. At pre-defined intervals, the display control unit may compare the timestamp of the topmost entry of the timestamp queue to a global timer value. If the timestamp is earlier than the global timer value, the display control unit may pop the timestamp entry and fetch the frame next configuration set from memory. The display control unit may then apply the updates of the frame configuration set to its pixel processing elements. After applying the updates, the display control unit may fetch and process the source pixel data and then drive the pixels of the next frame to the display.

Abstract: A graphics processing system has a rendering space which comprises one or more tiles. The system comprises a processing module configured to perform hidden surface removal for primitives of a tile to determine primitive identifiers identifying the primitives which are visible at each of a plurality of sample positions in the tile. A set of two or more tag buffers store the primitive identifiers determined for each of the sample positions in a tile, thereby representing overlapping layers of primitives. A tag control module controls: (i) selection of a tag buffer for the storage of each of the primitive identifiers according to the layering of the primitive identifiers stored in the tag buffers, and (ii) flushing of primitive identifiers from the tag buffers. A texturing engine applies texturing to the primitives identified by the flushed primitive identifiers.

Abstract: A lossless compression method and system applied to hardware video decoding are provided. The method sequentially includes a video decoding step, a compression step, a storage step and a decompression step, wherein in the compression step, lossless compression is performed by taking a 16×4 Y luma block and a corresponding 8×2 U chroma block and V chroma block as a compression unit; in the storage step, compact compression and storage is performed on a complete frame of image by taking four pixel lines as a unit, and a starting address of every four pixel lines is fixed; and the video decoding step includes a reference frame reading step, and a two-level Cache structure is adopted in the reference frame reading step. The system is a system applying the method.

Abstract: An apparatus includes an interface and a circuit. The interface may be connectable to (i) a plurality of counters and (ii) multiple pipelines. The circuit may be configured to (i) increment two or more given counters of the counters associated with a plurality of first data units in response to the first data units being available in a buffer, where two or more of the pipelines each (a) reads a plurality of current units from the first data units and (b) decrements a respective one of the given counters in response to each read of one of the current units, (ii) monitor the decrements of the given counters and (iii) block a second data unit from being copied into the buffer until all of the given counters indicate that the buffer has room to hold the second data unit.

Abstract: A memory device for storing data is disclosed. The memory device comprises a plurality of memory banks, wherein each memory bank comprises a plurality of addressable memory cells. The memory device also comprises a plurality of pipelines each comprising a plurality of pipestages, wherein each pipeline is associated with a respective one of the plurality of memory banks. Further, the device comprises a plurality of cache memories, wherein each cache memory is associated with a respective one of the plurality of memory banks and a respective one of the plurality of pipelines, and wherein each cache memory is operable for storing a second plurality of data words and associated memory addresses, and wherein further each data word of said second plurality of data words is either awaiting write verification associated with a given segment of an associated memory bank or is to be re-written into a given segment of said associated memory bank.

Abstract: Systems, methods, and computer programs are disclosed for providing power-efficient file system operation to a non-volatile block memory. An exemplary embodiment of a system comprises a non-volatile block memory having a file system, a dynamic random access memory (DRAM), and a system on chip (SoC). The SoC comprises a central processing unit (CPU), one or more non-core processors, a DRAM controller, a data interface coupled to an off-chip processor, and a multi-host storage controller. The CPU allocates a storage buffer in the non-volatile block memory. The multi-host storage controller comprises a virtualized client interface for providing the non-core and off-chip processors with direct read/write file system access using the allocated storage buffer while the CPU and the DRAM are in a low power state.

Abstract: Certain aspects of the present disclosure provide techniques for scalably and efficiently converting linear image data into multi-dimensional image data for multimedia applications. In one example, a method for managing image data includes receiving a line of image data in a linear format via a system bus of width T, wherein the image data's native format is a tile format of H lines per tile; forming H subsets of image data from the line of image data in the linear format; writing the H subsets of image data to a memory comprising BN=H banks of BW=T/BN pixel width, wherein each subset of the H subsets is written to a different bank of the BN banks; and outputting the H subsets of image data in the tile format.

Abstract: Systems, apparatuses, and methods for tracking page reuse and migrating pages are disclosed. In one embodiment, a system includes one or more processors, a memory access monitor, and multiple memory regions. The memory access monitor tracks accesses to memory pages in a system memory during a programmable interval. If the number of accesses to a given page is greater than a programmable threshold during the programmable interval, then the memory access monitor generates an interrupt for software to migrate the given page from the system memory to a local memory. If the number of accesses to the given page is less than or equal to the programmable threshold during the programmable interval, then the given page remains in the system memory. After the programmable interval, the memory access monitor starts tracking the number of accesses to a new page in a subsequent interval.

Abstract: Methods and systems may provide for an apparatus having a graphics processing unit (GPU) and a non-volatile memory dedicated to the GPU. If a request for content is detected, a determination may be made as to whether the non-volatile memory contains the content.

Abstract: An apparatus and method are described for managing a virtual graphics processor unit (GPU). For example, one embodiment of an apparatus comprises: a dynamic addressing module to map portions of an address space required by the virtual machine to matching free address spaces of a host if such matching free address spaces are available, and to select non-matching address spaces for those portions of the address space required by the virtual machine which cannot be matched with free address spaces of the host; and a balloon module to perform address space ballooning (ASB) techniques for those portions of the address space required by the virtual machine which have been mapped to matching address spaces of the host; and address remapping logic to perform address remapping techniques for those portions of the address space required by the virtual machine which have not been mapped to matching address spaces of the host.

Abstract: Disclosed herein are techniques to provide both asynchronous frame updates and panel self-refresh in a single implementation. A platform can be arranged to provide frame updates asynchronously with the refresh rate of a connected panel while the connected panel can be arranged to self-refresh where no new updates are provided.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for queuing storage operations. An integrated circuit memory element receives a storage operation command associated with a bank of storage locations of a memory element. An integrated circuit memory element queues a storage operation command for execution on a bank of storage locations by determining a storage location in a page register for data associated with the storage operation command. A storage location in a page register includes a subset of available storage locations in the page register. An integrated circuit memory element stores data associated with a storage operation command at a determined storage location in a page register.

Abstract: The present describes low latency streaming using temporal frame transformation. An execution component in an edge server executes a first instance of an application. A server interface component receives, from a remote server, a resolution delta frame indicating differences between a high resolution first frame and a low resolution first frame of a second instance of the application or, alternatively, receives the high resolution first frame. A video manipulation component generates a motion delta frame by identifying differences between a low resolution first frame and a low resolution second frame of the first instance of the application. The video manipulation component generates a high resolution transformed frame by applying the resolution delta frame and the motion delta frame to the low resolution second frame.

Abstract: A computer-implemented method, computer program product, and computer processing system are provided for eliminating a memory fence for reading a read-mostly volatile variable of a computer system. The read-mostly variable is read from more than written to. The method includes writing data to the read-mostly volatile variable only during a Stop-The-World (STW) state of the computer system. The method further includes executing the memory fence in any mutator threads and thereafter exiting the STW state. The method also includes reading the read-mostly volatile variable by the mutator threads without executing the memory fence after the STW state.

Abstract: A graphics processing system has a rendering space which is divided into tiles. Primitives within the tiles are processed to perform hidden surface removal and to apply texturing to the primitives. The graphics processing system includes a plurality of depth buffers, thereby allowing a processing module to process primitives of one tile by accessing one of the depth buffers while primitive identifiers of another, partially processed tile are stored in another one of the depth buffers. This allows the graphics processing system to have “multiple tiles in flight”, which can increase the efficiency of the graphics processing system.

Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Abstract: The present disclosure relates generally to improved systems and methods for control of a first-in, first-out (FIFO memory). More specifically, the present disclosure relates to improved timing and/or control signals used to control operation of the FIFO memory. For example, access circuitry of the memory device may pulse a control signal used to control latching of data at the FIFO memory. Further, the access circuitry may pulse one or more bits of a column address bus to generate a column address corresponding to data to be latched at the FIFO memory. Accordingly, the current, power, and/or area consumed by the memory device may be reduced.

Abstract: An image processing device includes: an integrated circuit chip arranged on a substrate to perform processing on image data; a first memory chip arranged adjacent to the integrated circuit chip on the substrate and connected to the integrated circuit chip; and a second memory chip stacked on the integrated circuit chip and connected to the integrated circuit chip, wherein the integrated circuit chip sets, according to the processing content, any one of a plurality of operation modes including a first operation mode to operate the first memory chip and limit operation of the second memory chip, and a second operation mode to operate the first memory chip and the second memory chip.

Abstract: A layout engine generates a visual layout tree for a visual description tree of a document whose content is to be rendered in one or more display areas. A visual description tree describes the content of a document along with formatting and logical arrangement the content. Visual description nodes of a visual description tree represent the organization of the constituent elements a document hierarchically. A visual layout tree defines the layout of a document within one or more display areas. Visual layout nodes of a visual layout tree represent the layout of the content of a document hierarchically. The layout engine receives as input a visual description tree and generates the corresponding visual layout tree. A rendering engine then inputs the visual layout tree and generates a graphics buffer containing the pixels representing the layout of the document as defined by the visual layout tree.