Abstract: Some embodiments provide a system that executes a web application. During operation, the system loads the web application in a web browser and loads a native code module associated with the web application into a secure runtime environment. Next, the system writes a set of rendering commands to a command buffer using the native code module and concurrently reads the rendering commands from the command buffer. Finally, the system renders an image for use by the web application by executing the rendering commands using a graphics-processing unit (GPU).

Abstract: A system, method, and computer program product are provided for GPU demand paging. In operation, input data is addressed in terms of a virtual address space. Additionally, the input data is organized into one or more pages of data. Further, the input data organized as the one or more pages of data is at least temporarily stored in a physical cache. In addition, access to the input data in the physical cache is facilitated.

Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.

Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.

Abstract: Memory-based semaphore are described that are useful for synchronizing operations between different processing engines. In one example, operations include executing a context at a producer engine, the executing including updating a memory register, and sending a signal from the producer engine to a consumer engine that the memory register has been updated, the signal including a Context ID to identify a context to be executed by the consumer engine to update the register.

Abstract: The present invention relates to a display device for a glass cockpit of an aircraft, intended to provide video streams to a plurality of viewing screens of said glass cockpit, said aircraft being partitioned into a secured area, a so-called avionic world (AW), and a non-secured area, a so-called open world (OW), said system comprising at least one first port intended to receive first data to be displayed from a system (210, 310, 410) belonging to the avionic area and at least one second port intended to receive second data to be displayed from a system (220, 320, 420) belonging to the open world, the display device comprising: predetermined hardware resources allocated to the processing of the second data; a processor (241, 341, 441), belonging to the avionic area, adapted to controlling the hardware resources used by said processing and interrupting this processing if said hardware resources used exceed said allocated resources.

Abstract: Provided are methods and systems for reducing memory bandwidth usage in a common buffer, multiple FIFO computing environment. The multiple FIFO's are arranged in coordination with serial processing units, such as in a pipeline processing environment. The multiple FIFO's contain pointers to entry addresses in a common buffer. Each subsequent FIFO receives only pointers that correspond to data that has not been rejected by the corresponding processing unit. Rejected pointers are moved to a free list for reallocation to later data.

Abstract: A display apparatus is provided. The display apparatus includes a display, a memory which stores screen setting data on the display, an internal interface which performs data communication in the display apparatus, and a switch which switches between communication between the memory and a host apparatus or communication between the memory and the internal interface. The switch is driven by hot plug power or main power according to a predetermined condition, and, if the main power is turned off, the switch is driven by the hot plug power and performs communication with the host apparatus. Accordingly, the display apparatus satisfies a communication standard for recognizing apparatuses using a single memory.

Abstract: A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (CPUs) and graphic processing units (GPUs). A system creates a subbuffer from a parent buffer for each of a plurality of heterogeneous compute units. If a subbuffer is not associated with the same compute unit as the parent buffer, the system copies data from the subbuffer to memory of that compute unit. The system further tracks updates to the data and transfers those updates back to the subbuffer.

Abstract: The subject matter of this specification can be embodied in, among other things, a method that includes computer-implemented graphics frame buffer process that establishes on a computing device a graphics frame buffer accessible to be written by an application process and to be read by a graphics server process. The method further comprises generating a plurality of control bits whose value or values control access to the frame buffer by the application process and the graphics server process and reading frames from the frame buffer using the value or values in the plurality of control bits.

Abstract: An arbitration circuit to arbitrate an issue between a read/write command and a scan command and a display driver integrated circuit including the arbitration circuit.

Abstract: The present disclosure relates to rendering interactive displays remote from a host application. More specifically, the present disclosure relates to rendering interactive displays, such as interactive geographic map displays and computer game displays, remote from a corresponding host application, such as a web page for a municipality, a university, a computer game, a business, etc., that generates a display which includes the remotely rendered interactive display.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A shared memory is provided accessible by a central processing unit and a graphics processing unit. A bus is provided via which the central processing unit, graphics processing unit and shared memory communicate. A first mechanism controls the graphics processing unit and the central processing unit routes control signals via the bus. An interface is provided between the central processing unit and the graphics processing unit, and an additional mechanism controls the graphics processing unit and the central processing unit provides control signals over the interface. This enables the GPU to continue to be used to handle large batches of graphics processing operations loosely coupled with the operations performed by the CPU, and it is also possible to employ the GPU to perform processing operations on behalf of the CPU in situations where those operations are tightly coupled with the operations performed by the CPU.

Abstract: The described embodiments provide a system that renders graphics for a computer system. During operation, the system loads a software client and a software service in the computing system. Next, the system receives a set of rendering commands from the software client in a command buffer, wherein the rendering commands include at least one of a state change command, a resource allocation command, a direct memory access (DMA) command, buffer data, and a synchronization command. Finally, the system uses the software service to render an image corresponding to the rendering commands by reading the rendering commands from the command buffer and executing the rendering commands.

Abstract: Disclosed herein are methods, apparatuses, and systems for accessing vertex data stored in a memory, and applications thereof. Such a method includes writing vertex data of primitives into contiguous banks of a memory such that the vertex data of consecutively written primitives spans more than one row of the memory. Vertex data of two consecutively written primitives are read from the memory in a single clock cycle.

Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract: A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring instructions and information between the CPU and GPU.

Abstract: An apparatus including a first memory, a second memory, and a memory interface. The first memory may be configured to store an entire image. The second memory may be configured to store a portion of the image during an image processing operation. The memory interface may be configured to transfer the portion of the image (i) from a source area of the first memory to the second memory prior to the image processing operation and (ii) from the second memory to a destination area of the first memory following the image processing operation. The memory interface may be further configured to select from among four modes of transferring image data from the source area of the first memory and to the destination area of the first memory based upon how the source area and the destination area overlap in the first memory.

Abstract: A system and method of capturing, storing, editing and outputting multi-track motion data in a continuous stream on a computer with deterministic timing, where the length of the motion dataset is not limited by computer Random Access Memory. A hard real time periodic motion task takes in data streams from sensors or other computers, stores it in a shared memory area, and streams out the data to other computers so as to actuate motion. A shared memory area stores buffers and flags which indicate what data should be swapped to and from persistent storage. A soft real time periodic task transfers data pages between RAM and persistent storage based on requests from the motion task. Three data pages surround the active point in the motion dataset, four pages are reserved for copying whole blocks of data, and three pages are reserved for data editing. These ten active memory pages define a fixed memory footprint which can handle a deterministic data stream of effectively infinite length.

Abstract: Embodiments are directed to providing direct access to graphical user interface (GUI) frame buffers and to associating input hardware with a login session. In one scenario, a computer system registers a plug-in software module with a remote desktop client. The registering includes requesting one or more frame buffers rendered for display on a computer system display. The computer system determines that a session has been established between a computer system user and the remote desktop client. The computer system then receives the requested frame buffers and displays the frame buffers on the computer system display and/or sends the received frame buffers to various registered third parties.

Abstract: Three dimensional scenes may be managed between a central processing unit and a graphics processing unit using shared and unified graphics processing unit memory. A shared bus memory may be synchronized between the central processing unit and the graphics processing unit. The shared bus memory may be used for more often updated components and other memory may be used for less often updated components. In some embodiments, if the graphics processor and the central processor use a common processor instruction set architecture, data can be sent from the central processor to the graphics processor without serializing the data.

Abstract: A system and method for facilitating access to graphics memory wherein the graphics memory can be shared between a graphics processor and general system application. The method includes detecting an idle state of a graphics processing unit (GPU). The GPU uses graphics memory operable for storing graphics data. The method further includes determining an amount of available memory of the graphics memory of the GPU and signaling an operating system regarding the available memory. Memory data transfers are then received to store data into the available memory of the graphics memory wherein the data is related to general system application. Memory accesses to the available memory of the GPU are translated into a suitable format and executed so that the graphics memory is shared between the GPU and the operating system.

Abstract: In a communication device with a graphics processor, a graphics asset can be shared with two or more applications. The graphics asset can include a bitmap of a digital image. An asset server can host a texture corresponding to the graphics asset and can share the texture with the graphics processor. The asset server can host multiple textures and can share those textures with the graphics processor for rendering. The graphics processor can use the shared texture to render an instance of the graphics asset for each of the two or more applications. The texture can be generated by copying information about the graphics asset into the asset server.

Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced.

Abstract: Various systems and methods are described for accessing a shared memory in a graphics processing unit (GPU). One embodiment comprises determining whether data to be read from a shared memory aligns to a boundary of the shared memory, wherein the data comprises a plurality of data blocks, and wherein the shared memory comprises a plurality of banks and a plurality of offsets. A swizzle pattern in which the data blocks are to be arranged for processing is determined. Based on whether the data aligns with a boundary of the shared memory and based on the determined swizzle pattern, an order for performing one or more wrapping functions is determined. The shared memory is accessed by performing the one or more wrapping functions and reading the data blocks to construct the data according to the swizzle pattern.

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.

Abstract: In a system comprising a plurality of processors and a memory shared by at least a subset of the processors, a method for processing video data includes the steps of: (a) a first one of the processors receiving a first video frame and storing the first video frame in the memory; (b) the first one of the processors receiving at least a second video frame, receipt of the second video frame initiating a release of the first video frame from the memory; (c) the first one of the processors sending the first and second video frames to a second one of the processors together for processing by the second one of the processors; (d) the second one of the processors generating an output video frame based at least on the first and second video frames; (e) storing the output video frame in the memory by overwriting an available memory location therein, the output video frame becoming a new first video frame; and (f) repeating steps (b) through (e) until all video frames to be processed have been received.

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract: A handheld electronic device includes a display manager configured to provide a plurality of objects for display at a plurality of display mechanisms, where at least two of the plurality of display mechanisms display at least one common object, and a control filter having preconfigured filter criteria configured to automatically determine, based on a type of an object, to which of the plurality of display mechanisms the display manager provides the object.

Abstract: A display control device for controlling a display panel includes a contents frame rate detector detecting a contents frame rate of an input image data and outputting a repetitive frame number dependent from a display frame rate of the display panel and the detected contents frame rate; a frame memory for storing a level data of a previous frame; and an emulated level generator in communication with the contents frame rate detector and the frame memory. An output level data to the display panel is generated according to the repetitive frame number from the contents frame rate detector, the previous level data from the frame memory and an input level data of the input image data.

Abstract: A stream based memory access system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A frame buffer memory is included for storing data for the scalar execution unit and the vector execution unit. A memory interface is included for establishing communication between the scalar execution unit and the vector execution unit and the frame buffer memory. The frame buffer memory comprises a plurality of tiles. The memory interface implements a first sequential access of tiles and implements a second stream comprising a second sequential access of tiles for the vector execution unit or the scalar execution unit.

Abstract: One or more embodiments of the invention set forth techniques to allocate a memory buffer in the system memory of a computer system that is shared among a plurality of graphics processing units (GPUs) in the computer system. The GPUs are able to engage in Direct Memory Access (DMA) with the memory buffer thereby eliminating additional copying steps that have been needed to combine data output of the various GPUs without such a shared memory buffer.

Abstract: A computer-program product may have instructions that, when executed, cause a processor to perform operations including managing execution of application functions that access data in a shared buffer; determining if a first instruction that is stored at a first memory location causes, upon execution, data to be read from or written to the shared buffer; and when it is determined that the first instruction causes data to be read from or written to the shared buffer, 1) identify one or more replacement instructions to execute in place of the first instruction; 2) store the one or more replacement instructions; and 3) replace the first instruction at the first memory location with a second instruction that, when executed, causes the stored one or more replacement instructions to be executed.

Abstract: The subject matter of this specification can be embodied in, among other things, a method that includes computer-implemented graphics frame buffer process that establishes on a computing device a graphics frame buffer accessible to be written by an application process and to be read by a graphics server process. The method further comprises generating a token whose value or values control access to the frame buffer by the application process and the graphics server process and reading frames from the frame buffer using the value or values in the token.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: Some embodiments provide a system that executes a web application. During operation, the system loads the web application in a web browser and loads a native code module associated with the web application into a secure runtime environment. Next, the system writes a set of rendering commands to a command buffer using the native code module and concurrently reads the rendering commands from the command buffer. Finally, the system renders an image for use by the web application by executing the rendering commands using a graphics-processing unit (GPU).

Abstract: A method and apparatus for processing data in a heterogeneous multi-core environment, capable of reducing data processing time by storing frames not having redundant data only among input frames in a shared memory. The apparatus compares a second frame with a first frame having a time difference with respect to a first frame, thereby determining identity between the first frame and the second frame. The apparatus stores address information related to the first frame or stores the second frame according to the determination result, thereby reducing quantity of data to be updated.

Abstract: Various systems and methods are described for accessing a shared memory in a graphics processing unit (GPU). One embodiment comprises determining whether data to be read from a shared memory aligns to a boundary of the shared memory, wherein the data comprises a plurality of data blocks, and wherein the shared memory comprises a plurality of banks and a plurality of offsets. A swizzle pattern in which the data blocks are to be arranged for processing is determined. Based on whether the data aligns with a boundary of the shared memory and based on the determined swizzle pattern, an order for performing one or more wrapping functions is determined. The shared memory is accessed by performing the one or more wrapping functions and reading the data blocks to construct the data according to the swizzle pattern.

Abstract: A computer-program product may have instructions that, when executed, cause a processor to perform operations including managing execution of application functions that access data in a shared buffer; determining if a first instruction that is stored at a first memory location causes, upon execution, data to be read from or written to the shared buffer; and when it is determined that the first instruction causes data to be read from or written to the shared buffer, 1) identify one or more replacement instructions to execute in place of the first instruction; 2) store the one or more replacement instructions; and 3) replace the first instruction at the first memory location with a second instruction that, when executed, causes the stored one or more replacement instructions to be executed.

Abstract: One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitted to a video pipeline for processing. The resulting video pixel data is routed to video output encoders, which selectively accept the video pixel data for transmission to attached display devices.

Abstract: A mobile computing device with a mobile operating system and desktop operating system running concurrently and independently on a shared kernel without virtualization. The mobile operating system provides a user experience for the mobile computing device that suits the mobile environment. The desktop operating system provides a full desktop user experience when the mobile computing device is docked to a second user environment. Cross-environment rendering and user interaction support provide a seamless computing experience in a multi-operating system computing environment. The seamless computing experience includes mirroring the active user interaction space of the mobile operating system to a display of a user environment associated with the desktop operating system. The mobile computing device may be a smartphone running the Android mobile operating system and a full desktop Linux distribution on a modified Android kernel.

Abstract: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

Abstract: A system and method for representing multiple prefetchable memory resources, such as frame buffers coupled to graphics devices, as a unified prefetchable memory space for access by a software application. A graphics surface may be processed by multiple graphics devices, with portions of the surface residing in separate frame buffers, each frame buffer coupled to one of the multiple graphics devices. One or more redirection regions may be specified within the unified prefetchable memory space. Accesses within a redirection region are transmitted to a prefetchable memory of a single graphics device. Accesses within the unified prefetchable memory space, but outside of any redirection region may be broadcast to all of the prefetchable memories of the multiple graphics devices.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: Methods, apparatuses and systems directed to hosting, on a computer system, a plurality of application instances, each application instance corresponding to a remote client application; maintaining a network connection to each of the remote client applications for which an application instance is hosted; allocating resources of a graphics processing unit of the computer system between at least two of the remote client applications; concurrently rendering, utilizing the resources of the graphics processing unit of the computer system, the graphical output of the application instances corresponding to the at least two of the remote client applications; and transmitting the rendered graphical output to the at least two of the remote client applications over the respective network connections.

Abstract: Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and a data set partitioned into fields. The first ASIC writes data to a first subset of the fields and reads data from the fields. The first ASIC includes first logic that computes a first value based on the data read from the fields. The second ASIC writes data to a second subset of the fields and reads data from the fields. The second ASIC includes second logic that computes a second value based on the data read from the fields. Based on the first and second values respectively computed by the first and second logic, only one of the first and second ASICs gains access to the shared resource.