Memory Allocation Patents (Class 345/543)
  • Patent number: 10277810
    Abstract: An image processing apparatus comprises: a first processing circuit which carries out image processing on a first image signal obtained from image signals forming a single image; a second processing circuit which carries out the image processing on a second image signal obtained from the image signals forming the image; and a control circuit which controls communication of image signals between the first processing circuit and the second processing circuit, wherein the first image signal and the second image signal do not have overlap region; and wherein the control circuit controls the communication for transferring an image signal of a region of the image additionally required when the first processing circuit carries out the image processing on the first image signal from the second processing circuit to the first processing circuit.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: April 30, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroyuki Yaguchi
  • Patent number: 10277833
    Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S?1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: April 30, 2019
    Assignee: Google LLC
    Inventors: Qiuling Zhu, Ofer Shacham, Jason Rupert Redgrave, Daniel Frederic Finchelstein, Albert Meixner
  • Patent number: 10180793
    Abstract: An example device in accordance with an aspect of the present disclosure includes a plurality of memory segments corresponding to at least one memory channel of a computing system that is to receive a memory module. A performance attribute of an Advanced Configuration and Power Interface (ACPI) table is set to indicate performance of at least one of the plurality of memory segments, and is usable for memory allocation by an operating system memory manager.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 15, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vincent Nguyen, Thierry Fevrier, David Engler
  • Patent number: 10026149
    Abstract: An image processing system includes an image processing module, a frame buffer encoding module and a frame buffer. Each image block includes multiple first-type coding blocks and at least one second-type coding block. The image processing module generates a first image processed result according to multiple first-type coding blocks of a target image block. The frame buffer encoding module generates a first frame buffer encoded result according to the first image processed result. The frame buffer, for the target image block, provides a buffer region including at least one first random access point and a second buffer region including at least one second random access point. The first frame buffer encoded result is stored to the first buffer region. At least one second-type coding block of the target image block is stored to the second buffer region.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: July 17, 2018
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Yi-Shin Tung, Chia-Chiang Ho
  • Patent number: 10009573
    Abstract: The image recording apparatus according to the present invention is provided with a conversion device that converts an optical image of a subject to an electrical signal, a recording circuit that records the electrical signal achieved through the conversion device in a storage device as image data and a display control circuit that detects an available capacity at the storage device and the length of time that power supply by a source is possible and displays them on a display as available capacity information and remaining power supply time information. The available capacity information indicates the length of available recording time remaining at the available capacity that has been detected.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 26, 2018
    Assignee: NIKON CORPORATION
    Inventors: Masahiro Juen, Masaharu Ito, Hirotake Nozaki, Masahide Tanaka, Kenji Toyoda
  • Patent number: 9837048
    Abstract: A data processing system 30 includes a CPU 33, a GPU 34, a video processing engine (video engine) 35, a display controller 36 (or an image processing engine) and a memory controller 313 all having access to off-chip memory 314. A frame to be displayed is generated by, for example, being appropriately rendered by the GPU 34 or video engine 35. The display controller 36 (or the image processing engine) then performs display modifications, such as luminance compensation, on the frame to provide an output frame for display. The display controller 36 (or the image processing engine) also provides display modification information (such as determined luminance compensation parameters) to the GPU 33 and video engine 34. The display modification information is then used to modify the data that is generated for a frame to be displayed.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: December 5, 2017
    Assignee: Arm Limited
    Inventors: Daren Croxford, Sean Tristram Ellis
  • Patent number: 9830288
    Abstract: One embodiment of the present invention sets forth a method for transmitting data rendered on a primary computer to a secondary computer. The method includes transmitting to GPU graphics processing commands received from a graphics application, where the graphics processing commands are configured to cause the GPU to render a first set of graphics data, determining that graphics data should be collected for transmission to the secondary computer, conveying to the GPU that the first set of graphics data should be stored in a first buffer within a frame buffer memory, transmitting to the GPU graphics processing commands received from a process application executing on the primary computer, where the graphics processing commands are configured to cause the GPU to perform operations on the first set of graphics data to generate a second set of graphics data, and transmitting the second set of graphics data to the secondary computer.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: November 28, 2017
    Assignee: NVIDIA CORPORATION
    Inventor: Franck Diard
  • Patent number: 9817922
    Abstract: A method and system for creating three dimensional (3D) models from two dimensional (2D) data for building information modeling (BIM). The method and system allow new, 2D, 3D and higher dimensional models to be created for existing 3D modeling programs (e.g., AUTODESK REVIT, AUTOCAD, VECTORWORKS, MICROSTATION, ARCHICAD, etc.). The new models are used to enhance and extend existing 3D modeling programs. The new models can also be used to directly create physical objects (e.g., windows, doors, etc.) represented by the new models with robots, 3D printers and manufacturing machines.
    Type: Grant
    Filed: March 1, 2014
    Date of Patent: November 14, 2017
    Assignee: Anguleris Technologies, LLC
    Inventors: Benjamin F. Glunz, Wayne R. Pearson, Alfredo F. Munoz
  • Patent number: 9756268
    Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: September 5, 2017
    Assignee: Google Inc.
    Inventors: Neeti Desai, Albert Meixner, Qiuling Zhu, Jason Rupert Redgrave, Ofer Shacham, Daniel Frederic Finchelstein
  • Patent number: 9729900
    Abstract: A method and associated apparatus for processing video data are provided. The video data includes a first frame formed by a plurality of macroblocks. The method includes providing a memory, deblocking a first macroblock in the first frame, and writing the deblocked macroblock into the memory. The step of writing the deblocked macroblock lets a plurality of pixel data of the deblocked macroblock to be stored to a first storage space at consecutive addresses in the memory.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: August 8, 2017
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventor: Jun-Yi Chen
  • Patent number: 9711107
    Abstract: A flag memory is provided which stores a flag indicating whether or not a corresponding pixel is in the initial state. When writing has been performed on an image memory by a drawing unit, a value of the flag of a corresponding pixel is changed from a first value indicating that the pixel is in the initial state to a second value indicating that the pixel is not in the initial state. When a display unit reads a pixel value from the image memory, a flag corresponding to the pixel is read from the flag memory, and if the flag still has the first value, an initial pixel value is supplied to the display unit, and otherwise, a pixel value read from the image memory is supplied to the display unit.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: July 18, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Yorihiko Wakayama
  • Patent number: 9649562
    Abstract: An order of calling sub-functions called from a main function for drawing a vector image is obtained, a group of all of sub-functions having a common combination of call sources and being called in succession, is extracted as a group, and a cache function for caching a vector part image drawn with the sub-functions included in the group, as a raster image, is added to the main function to newly generate an improved main function.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: May 16, 2017
    Assignee: DENA CO., LTD.
    Inventor: Hironori Bono
  • Patent number: 9554132
    Abstract: Compression transforming video into a compressed representation (which typically can be delivered at a capped pixel rate compatible with conventional video systems), including by generating spatially blended pixels and temporally blended pixels (e.g., temporally and spatially blended pixels) of the video, and determining a subset of the blended pixels for inclusion in the compressed representation including by assessing quality of reconstructed video determined from candidate sets of the blended pixels. Trade-offs may be made between temporal resolution and spatial resolution of regions of reconstructed video determined by the compressed representation to optimize perceived video quality while reducing the data rate. The compressed data may be packed into frames. A reconstruction method generates video from a compressed representation using metadata indicative of at least one reconstruction parameter for spatial regions of the reconstructed video.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: January 24, 2017
    Assignee: Dolby Laboratories Licensing Corporation
    Inventors: James E. Crenshaw, Alfred She, Ning Xu, Limin Liu, Scott Daly, Kevin Stec, Samir Hulyalkar
  • Patent number: 9454496
    Abstract: A memory system is provided, which includes a real memory space and a virtual memory space. The memory system includes a memory device having a first memory space which is accessed using a first memory address and a second memory space which is accessed using a second memory address, and a memory controller configured to control access to the memory device; wherein the memory controller is configured to translate the first memory address into the second memory address mapped thereto in response to a request for access to the first memory space, access the second memory space using the translated second memory address, and access the second memory space using the non-translated second memory address, in response to a request for access to the second memory space.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: September 27, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sun-Young Lim
  • Patent number: 9448930
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: September 20, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Patent number: 9420022
    Abstract: A client media application sends a first request for a first chunk of a particular media stream. In response to the request, the client media application begins receiving data packets associated with the requested first chunk of the particular media stream. The data packets are received through a socket having a buffer. Rather than waiting until all of the data packets associated with the first chunk of the particular media stream have been read from the buffer by the client media application before sending a request for a second chunk of the particular media stream, the client media application monitors the amount of data that has been received compared to an expected amount of data, and sends the second request when it determines that the amount of data remaining to be received is less than the size of the buffer.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: August 16, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Pradip K Fatehpuria, Zhefeng (Jeff) Du
  • Patent number: 9396243
    Abstract: In one aspect, a method includes sending a first short hash handle and a first identity bit associated with the first short hash handle to a replication site, determining if a second hash handle is identical to the first short hash handle, determining if a second identity bit associated with the second short hash handle at the replication is set if the second short hash handle is identical to the first short hash handle and using the second hash handle to identify the data if the second identity bit being is set. The first short hash handle is an identifier of data stored on a disk.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: July 19, 2016
    Assignee: EMC Corporation
    Inventors: Ido Halevi, David Meiri
  • Patent number: 9342322
    Abstract: A method for tile-based rendering of content. Content may be rendered in a memory region organized as multiple tiles. In scenarios in which content is generated in layers, for operations that involve compositing image layers, an order in which portions of the image are processed may be selected to reduce the aggregate number of memory accesses times, which in turn may improve the performance of a computer that uses tile-based rendering. An image may be processed such that operations relating to rendering portions of different layers corresponding to the same tile are performed sequentially. Such processing may be used in a computer with a graphics processing unit that supports tile-based rendering, and may be particularly well suited for computers with a slate form factor. An interface to a graphics processing utility within the computer may provide a flag to allow an application to specify whether operations may be reordered.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: May 17, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Blake D. Pelton, Amar Patel, Steve Pronovost
  • Patent number: 9336056
    Abstract: Embodiments include methods, systems and computer program products for providing an extendable job structure for executing instructions on an accelerator. The method includes creating a number of data descriptor blocks, each having a fixed number of memory location addresses and a pointer to a next of the number of the data descriptor block. The method further includes creating a last data descriptor block having the fixed number of memory location addresses and a last block indicator. Based on determining that additional memory is required for executing instructions on the accelerator, the method includes modifying the last data descriptor block to become a data extender block having a pointer to one of one or more new data descriptor blocks and creating a new last data descriptor block.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: May 10, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh W. Asaad, Parijat Dube, Hong Min, Donald W. Schmidt, Bharat Sukhwani, Mathew S. Thoennes
  • Patent number: 9323684
    Abstract: Technologies are presented that allow a portion of a cache to be used as a front memory when there is dynamic need based on system demand. A computing system may include at least one processor, a memory controlled by a controller and communicatively coupled with the at least one processor, a cache communicatively coupled with the at least one processor and the memory, and mapping logic communicatively coupled with the at least one processor, the memory, and the cache. The mapping logic may map a portion of the cache to a portion of the memory, wherein the portion of the cache is to be used by the at least one processor as a local memory, and wherein the mapping is dynamic based on system demand and managed by the controller in a physical address domain.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Altug Koker, Aditya Navale
  • Patent number: 9219926
    Abstract: An image processing apparatus according to the present invention includes, a division unit configured to divide an image to generate a first block group including one or more blocks and a second block group adjacent to the first block group, a first encoding unit to encode the first block group in units of block, a second encoding unit to encode the second block group in units of block, and a storage unit to store encoded information after the first encoding unit processes a block at a predetermined position, in which the storage unit, when the first block group does not include a block at the predetermined position, sets the predetermined position to a block in the first block group and stores the encoded information based on the set position, and wherein the second encoding unit starts encoding based on the encoded information.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 22, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Koji Okawa
  • Patent number: 9208602
    Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 8, 2015
    Assignee: INTEL CORPORATION
    Inventors: Rahul P. Sathe, Tim Foley
  • Patent number: 9202007
    Abstract: A method for providing documentation and/or annotation capabilities for volumetric data may include receiving an indication of user insertion of an annotation with respect to a particular presentation state of a planar view of volumetric data and generating a medical image such as a DICOM image corresponding to the particular presentation state and including the annotation in response to receipt of the indication. A corresponding computer program product and apparatus are also provided.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: December 1, 2015
    Assignee: McKesson Financial Holdings
    Inventors: Allan Noordvyk, Leonard Yan, Cristian Stegaru, Radu Catalin Bocirnea, Monica Paul, Gillian Lo
  • Patent number: 9197933
    Abstract: A display apparatus is provided. The display apparatus includes a signal processor which processes a broadcast signal; an application executor which executes at least one application; a storage which stores a code command to change a use of a memory area, the storage including a first memory area allocated for processing the broadcast signal and a second memory area allocated for execution of the application; and a controller which, if the application is executed, changes, based on the code command, the first memory area to an area for execution of the application.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 24, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Chung-ki Woo
  • Patent number: 9111325
    Abstract: The graphics processing technique includes detecting a transition from rendering graphics on a first graphics processing unit to a second graphics processing, by a hybrid driver. The hybrid driver, in response to detecting the transition, configures the first graphics processing unit to create a frame buffer. Thereafter, an image rendered on the second graphics processing unit may be copied to the frame buffer of the first graphics processing unit. The rendered image in the frame buffer may then be scanned out on the display.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: August 18, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Franck Diard
  • Patent number: 9087394
    Abstract: A new hardware architecture defines an indexing and encoding method for accelerating incoherent ray traversal. Accelerating multiple ray traversal may be accomplished by organizing the rays for minimal movement of data, hiding latency due to external memory access, and performing adaptive binning. Rays may be binned into coarse grain and fine grain spatial bins, independent of direction.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: July 21, 2015
    Assignee: Raycast Systems, Inc.
    Inventor: Alvin D. Zimmerman
  • Patent number: 9053752
    Abstract: Systems and methods for layering a graphics plane on top of a compressed video signal are disclosed herein. A processed video stream is received from a video processing path, wherein the processed video stream comprises a stream of video macroblocks. A graphics plane is received from a graphics processing path, wherein the graphics plane comprises a set of graphics macroblocks. The graphics plane is layered on top of the processed video stream to generate an output video stream. Layering comprises blending a video macroblock from the stream of video macroblocks with a graphics macroblock from the set of graphics macroblocks. By layering one macroblock at time, graphics overlay can occur in real time or faster than real time as the compressed input stream is received.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: June 9, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Anthony D. Masterson
  • Publication number: 20150130825
    Abstract: A method for computing eigenvectors and eigenvalues of a square matrix in a high performance computer involves dynamically reallocating the computer's computing cores for various phases of the computation process.
    Type: Application
    Filed: November 7, 2014
    Publication date: May 14, 2015
    Inventor: Cheng Liao
  • Publication number: 20150109314
    Abstract: There is provided a method and apparatus for managing memory in a system for generating 3-dimensional computer images. The image is subdivided into a plurality of rectangular areas. A memory is provided and a page of the memory is allocated for storing object data for objects in the image. Object data for objects in the image are then written to the allocated page of memory. Finally, a bit mask for the allocated page of memory is compiled, the bit mask indicating the rectangular areas having object data stored in the allocated page of memory. A rectangular area of the image can then be rendered by deriving data for display from the object data stored in the memory, for objects in that rectangular area. Once the rectangular area has been rendered, the bit mask for each page of memory which stored, before the step of rendering, object data for that rectangular area, is updated so that the bit mask no longer indicates that rectangular area.
    Type: Application
    Filed: September 11, 2014
    Publication date: April 23, 2015
    Inventor: Jonathan Redshaw
  • Patent number: 9013473
    Abstract: A graphic processing unit (GPU) and method for decompressing compressed 3-dimensional (3D) compressed data. The GPU may extract segment information by analyzing a compressed data header and decompress segments included in a bit stream based on the segment information.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Su Ahn, Do Kyoon Kim, Tae Hyun Rhee
  • Patent number: 9007387
    Abstract: A drawing processing apparatus is disclosed. A graphic index of a graphic included in a display screen or graphic description information which includes a setting parameter to be applied to the graphic is determined for each of regions dividing the display screen. A data size of the graphic description information is aggregated for the regions. A start address in a memory is determined to store the graphic description information into a successive storage area in the memory, based on the aggregated data size. The data size of an area of an overflow occurrence target is stored when the overflow occurs. The graphic description information of the regions is successively written from the start address when the overflow does not occur. A write process is stopped, and resumed from the area of the overflow occurrence target by using the data size when the overflow occurs.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Fujitsu Limited
    Inventor: Yasushi Sugama
  • Publication number: 20150091924
    Abstract: A method for sharing memory between a central processing unit (CPU) and an input/output (I/O) device of a computing device is described. The method may include creating an allocation of memory for the I/O device to operate on. The method includes detecting whether the allocation is not page-aligned, wherein an allocation is page-aligned when its base address and size be evenly divisible by the applicable page-size. The allocation may be successfully shared, even if not page-aligned, even if an operating system of the computing device doesn't support sharing of non-page-aligned allocations.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Jayanth Rao, Pavan Lanka, Ronald Silvas
  • Patent number: 8994740
    Abstract: A cache line allocation method, wherein the cache is coupled to a graphic processing unit and the cache comprising a plurality of cache lines, each cache line stores one of a plurality of instructions the method comprising the steps of: putting the plurality of instructions in whole cache lines; locking the whole cache lines if an instruction size is less than a cache size; locking a first number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is less than or equal to a threshold; and locking a second number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is large than the threshold; wherein the first number is greater than the second number.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: March 31, 2015
    Assignee: VIA Technologies, Inc.
    Inventors: Bingxu Gao, Xian Chen
  • Publication number: 20150084974
    Abstract: One embodiment sets forth a method for allocating memory to surfaces. A software application specifies surface data, including interleaving state data. Based on the interleaving state data, a surface access unit bloats addressees derived from discrete coordinates associated with the surface, creating a bloated virtual address space with a predictable pattern of addresses that do not correspond to data. Advantageously, by creating predictable regions of addresses that do not correspond to data, the software application program may configure the surface to share physical memory space with one or more other surfaces. In particular, the software application may map the virtual address space together with one or more virtual address spaces corresponding to complementary data patterns to the same physical base address. And, by overlapping the virtual address spaces onto the same pages in physical address space, the physical memory may be more densely packed than by using prior-art allocation techniques.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Eric B. LUM, Cass W. EVERITT, Henry Packard MORETON, Yury Y. URALSKY, Cyril CRASSIN, Jerome F. DULUK, Jr.
  • Publication number: 20150070370
    Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.
    Type: Application
    Filed: November 20, 2014
    Publication date: March 12, 2015
    Inventors: Steve Pronovost, Maxwell Abernethy, Rudolph Balaz, Ameet Chitre
  • Patent number: 8941675
    Abstract: A device, system and method are provided for managing memory for rendering webpages and other structured documents that contain multiple regions. A backing store is created in memory for storing rendered document content. A main region of the structured document is rendered for display, divided into a set of tiles, and stored in the backing store. A subregion of the document is rendered and stored as tiles in the same backing store as well. At least a portion of the tiles for the main region and subregion intersecting with corresponding viewports are outputted to a display. When an active one of the viewports is changed and additional content of the document is to be rendered for display, tiles in the backing store used to store rendered but undisplayed data for the inactive viewport are released to store new rendered content for the active viewport.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: January 27, 2015
    Assignee: BlackBerry Limited
    Inventors: Adam Chester Treat, Eli Joshua Fidler, Antonio Gomes Araujo Netto
  • Patent number: 8938599
    Abstract: In a method of implementing a graph storage system, the graph storage system is stored on a plurality of computing systems. A global address space is provided for distributed graph storage. The global address space is managed with graph allocators, in which a graph allocator allocates space from a block of the distributed global memory in order to store a plurality of graphs.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: January 20, 2015
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Michael Mihn-Jong Lee, Indrajit Roy, Vanish Talwar, Alvin AuYoung, Parthasarathy Ranganathan
  • Patent number: 8928680
    Abstract: A program module executing in a first process space of a mobile computing device receives a buffer request from a graphics driver running in a second process space of the mobile computing device, wherein the second process space is isolated from the first process space. The program module assigns a buffer to the graphics driver to store image data processed by a graphical processing unit (GPU) controlled by the graphics driver. The program module receives a release of the buffer from the graphics driver. The program module assigns the buffer to a media encoder driver for a hardware media encoder to encode the image data in the buffer into a file.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: January 6, 2015
    Assignee: Google Inc.
    Inventors: Pannag Raghunath Sanketi, Jamie Gennis
  • Patent number: 8922712
    Abstract: In an embodiment, there is provided a video processing component comprising a compensation engine configured to generate pixels of a first video frame from a second video frame based at least in part on specified pixel motion; and an access buffer configured to store pixel data corresponding to pixels of the second video frame for reference by the compensation engine, wherein the pixel data is stored by the access buffer at different vertical resolutions depending on vertical distances of the pixels corresponding to the pixel data from a target pixel that is indicated by the compensation engine.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: December 30, 2014
    Assignee: Marvell International Ltd.
    Inventor: Vipin Namboodiri
  • Patent number: 8924677
    Abstract: Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard. If the memory manager detects the computing device is experiencing memory pressure, the memory manager may address the memory pressure by selecting memory space available for discard and discarding the content of the memory space. Before a process reuses content made available for discard, the process may notify the memory manager of the intent to reuse and, in response, receive empty memory and an indication that the content was discarded or receive an indication that the content is still available for use.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: December 30, 2014
    Assignee: Microsoft Corporation
    Inventors: Steve Pronovost, Maxwell Abernethy, Rudolph Balaz, Ameet Chitre
  • Patent number: 8923405
    Abstract: An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: December 30, 2014
    Assignee: Ambarella, Inc.
    Inventors: Ellen M. Lee, Yat Kuen Wong
  • Patent number: 8917279
    Abstract: A system for dynamically binding and unbinding of graphics processing unit GPU applications, the system includes a memory management for tracking memory of a GPU used by an application, and a source-to-source compiler for identifying nested structures allocated on the GPU so that the virtual memory management can track these nested structures, and identifying all instances where nested structures on the GPU are modified inside kernels.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: December 23, 2014
    Assignee: NEC Laboratories America, Inc.
    Inventors: Michela Becchi, Kittisak Sajjapongse, Srimat T. Chakradhar
  • Patent number: 8907964
    Abstract: A system to process a plurality of vertices to model an object. An embodiment of the system includes a processor, a front end unit coupled to the processor, and cache configuration logic coupled to the front end unit and the processor. The processor is configured to process the plurality of vertices. The front end unit is configured to communicate vertex data to the processor. The cache configuration logic is configured to establish a cache line size of a vertex cache based on a vertex size of a drawing command.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: December 9, 2014
    Assignee: Vivante Corporation
    Inventors: Keith Lee, Mike M. Cai
  • Publication number: 20140313214
    Abstract: A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (CPUs) and graphic processing units (GPUs). A system creates a subbuffer from a parent buffer for each of a plurality of heterogeneous compute units. If a subbuffer is not associated with the same compute unit as the parent buffer, the system copies data from the subbuffer to memory of that compute unit. The system further tracks updates to the data and transfers those updates back to the subbuffer.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 23, 2014
    Applicant: Apple Inc.
    Inventors: Aaftab A. Munshi, Ian R. Ollmann
  • Publication number: 20140313213
    Abstract: A memory apparatus may include a tile generator configured to generate a plurality of tiles by dividing a plurality of pixels constituting input data based on a predetermined pixel unit, and a tile storage configured to store the plurality of tiles by sequentially enumerating luminance information and chrominance information about pixels included in the plurality of tiles.
    Type: Application
    Filed: November 19, 2013
    Publication date: October 23, 2014
    Applicants: Industry-Academia Cooperation Group Of Sejong University, Samsung Electronics Co., Ltd.
    Inventors: Won Chang LEE, Gi Ho Park, Do Hyung Kim, Shi Hwa Lee, Seong Uk Jeong
  • Patent number: 8860739
    Abstract: Disclosed is a method of processing a digital representation comprising a plurality of cells having respective cell values and being arranged in a regular grid. The method comprises performing at least one cell data reordering operation and performing at least one arithmetic operation for computing at least a first cell value of a first cell from one or more cell values of respective cells of the digital representation, each arithmetic operation including at least one multiplication. The method comprises performing the at least one reordering operation and the at least one arithmetic operation as at least two concurrent processes, each of the concurrent processes reading respective parts of the digital representation from respective memory buffers of a shared memory.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: October 14, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Jordan Vitella-Espinoza
  • Patent number: 8860740
    Abstract: A computing machine includes a virtual machine monitor and a display adapter. The virtual machine monitor receives a graphics device interface (GDI) instruction including display content information and virtual machine identification information from a virtual machine, obtains video memory identification information by querying a correspondence between the virtual machine identification information and the video memory identification information, and sends a display driver message including the display content information and the video memory identification information to the display adapter. The display adapter receives the display driver message, stores the display content information in a video memory in the display adapter according to the video memory identification information, and sends the display driver message to a client terminal via a network interface card in the display adapter.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Hao Zhang
  • Patent number: 8854388
    Abstract: An image processing apparatus has a plurality of functions and is capable of executing a job relating to any of the plurality of functions. The image processing apparatus includes a memory management unit to secure a storage region in a first storage device for program execution, a save unit to save information from the storage region in the first storage device to a second storage device, a history recording unit to record a history relating to execution of the job each time the image processing apparatus executes the job, and a save restriction unit to restrict saving of information from the storage region in the first storage device to the second storage device in order to execute a job relating to a function which is specified based on a job history recorded by the history recording unit from among the plurality of functions.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: October 7, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Akira Ishikawa
  • Publication number: 20140267334
    Abstract: One embodiment of the present invention includes techniques for a first processing unit to perform an atomic operation on a memory page shared with a second processing unit. The memory page is associated with a page table entry corresponding to the first processing unit. Before executing the atomic operation, an MMU included in the first processing unit evaluates an atomic permission bit that is included in the page table entry. If the MMU determines that the atomic permission bit is inactive, then the two processing units coordinate to change the permission status of the memory page. As part of the status change, the atomic permission bit in the page table entry is activated. Subsequently, the first processing unit performs the atomic operation uninterrupted by the second processing unit. Advantageously, coordinating the processing unit via the atomic permission bit ensures the proper and efficient execution of the atomic operation.
    Type: Application
    Filed: August 27, 2013
    Publication date: September 18, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Jerome F. DULUK, JR., John MASHEY, Mark HAIRGROVE, James Leroy DEMING, Cameron BUSCHARDT, Brian FAHS
  • Patent number: 8836700
    Abstract: A method, system, and computer program product are disclosed for providing tessellated primitive data to a geometry shader. The method comprises computing a set of tessellated vertices and a computed set of connectivity data based on an original set of vertices and an original set of connectivity data, generating computed vertex data based on the original set of vertices and the set of tessellated vertices, receiving the computed set of connectivity data, requesting a subset of the computed vertex data based on the computed set of connectivity data, and processing primitives defined by the subset of the computed vertex data. The system and computer program product are further disclosed for accomplishing a similar result as the aforementioned method.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: September 16, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Vineet Goel