Abstract: A system for storing, communicating, and displaying image or graphic data over a network. The system includes a client that is connectable to a server via a network. The server is configured to store an image file having image data, where the structure of the image file preferably includes submatrices. The submatrices allow the system to render the images using an adaptive rendering technique.

Abstract: A networking conferencing and collaboration tool utilizing an enhanced T.128 application sharing protocol. This enhanced protocol is based on a per-host model command, control, and communication structure. This per-host model reduces network traffic, allows greater scalability through dynamic system resource allocation, allows a single host to establish and maintain a share session with no other members present. The per-host model allows private communication between the host and a remote with periodic broadcasts of updates by the host to the entire share group. This per-host model also allows the host to allow, revoke, pause, and invite control of the shared applications. Subsequent passing of control is provided, also with the hosts acceptance. The model contains no fixed limit on the number of participants, and dynamically allocates resources when needed to share or control a shared application. These resources are then freed when no longer needed.

Abstract: A rotated representation of an image is printed by using a coordinate system to assign tile divisions to the image. The size of the tile divisions are selected to maintain their area equal to, or less, than a predetermined maximum. Each segment of the image, as defined by the tile delineations, is sent separately to a data processing unit for processing. The received tile is assigned new coordinate dictating its new target position on a printed page, and its relation to the other tiles. The tile is itself further rotated prior to being send to the printer.

Abstract: A system and method for optimizing the performance of a graphics intensive software program for graphics acceleration hardware. This system and method encompasses a procedure that validates the different functions of a 3D acceleration capable video card, decides whether to use the acceleration hardware and optimizes the software application to selectively use the functions that work on the specific video acceleration card. Functions checked include sub-pixel positioning, opacity, color replacement and fog. If these tests are successful, then the graphics acceleration is used by the software application. However, if the tests are not successful the decision is made not to use graphics accelerator. Those with ordinary skill in the art will realize that it is not necessary to perform all of the tests in a specific order.

Abstract: Systems and methods for displaying volume data on an arbitrary three-dimensional polygonal surface are disclosed. For each polygon in the polygonal surface, a two-dimensional texture tile is created and these texture tiles are combined to form texture atlases. Each texture atlas is allocated a specific amount of memory in a texture cache. Each polygon in the polygonal surface may be scan-converted and the resulting texels may be placed in the texture cache. Voxels that do not intersect any polygon in the polygonal surface may not be scan-converted. This method may result in reduced use of texture cache.

Abstract: Image data having a bit depth of m bits, where m is not a power of two, may be divided into two parts for storage. The first part is the n most significant bits, where n is a power of two. The second part is the k least significant bits, where k=m?n and k<n. For example, 10-bit data may be separated into 8-bit and 2-bit parts. The 8-bit data for a given image is placed in the bitstream as a contiguous block with the end of the data aligned with a memory boundary, such as a page boundary. The 2-bit data is collected into bytes that are placed in the bitstream as a contiguous block. The block of 2-bit data is placed in the bitstream preceding and contiguous with the block of 8-bit data. Padding may be provided to align the beginning of the image data with a memory boundary. The image data for multiple images may be placed in the bitstream contiguously for storage. 10-bit data for an alpha channel, if any, also may be split into 8-bit and 2-bit parts.

Abstract: A method, apparatus, and computer program product for determining an amount of storage for a level of detail in a MIP map. It includes identifying a given level of detail; identifying a size for an immediately larger level of detail and a magnitude for each dimension of the immediately larger level of detail; and calculating the amount of storage based on the size and magnitudes without using a multiply operation or a precomputed table of offsets.

Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.

Abstract: Local memory associated with one or more companion devices within a system is mapped into a system memory for use by an application processor.

Abstract: A system that can store electronic program guide information using 3D graphics is disclosed. In a particular embodiment, a data filter and a text-to-image converter are used for converting filtered data into a set of digital images that are defined as a set of texture maps. In order to apply those texture maps, a memory analyzer analyzes the set-top box layout and indicates available memory types. The memory analyzer controls a memory distributor for distributing texture maps into the appropriate types of memory.

Abstract: A memory system and methods of operating the same that drastically increase the efficiency in memory use and allocation in graphics systems. In a graphics system using a tiled architecture, instead of pre-allocating a fixed amount of memory for each tile, the invention dynamically allocates varying amounts of memory per tile depending on the demand. In one embodiment all or a portion of the available memory is divided into smaller pages that are preferably equal in size. Memory allocation is done by page based on the amount of memory required for a given tile.

Abstract: In an embedded system, for instance in a household appliance, in addition to the usual embedded microprocessor/microcontroller there is provided another processor which actually executes a user interface HTML document for accepting user input, for instance from a keypad and controlling the display device, for instance an LCD. The embedded microprocessor hosts the user interface document, responds to requests from the other processor, keeps track of changes in variables shared with the other processor, and executes the control device functionality. The other processor renders the graphical user interface to the display and interacts with the user by executing local functions to operate on the memory and i/o resources of the embedded processor as described by the user interface document served to it.

Abstract: The present invention relates to a system and method (“Bid System”) for topologically subdividing and defining the detail scope of work and for inter-linking construction plans and specifications to construction contracts and subcontracts. The Bid System permits full, clear and unambiguous definition of the scope of work under each subcontract, so as to eliminates errors and uncertainty relating to contract performance. The Bid System establishes a series of electronic overlays to the digitized construction plans corresponding to different trades or categories of work, in which each overlay may be divided into a series of optimized topological subdivisions or “boxes” which uniquely identify and locate on the plans a portion of the work to be performed. The system includes linkage of the overlays and boxes to the subcontracts whereby the scope of work to be bid is accurately associated or “mapped” to corresponding regions and overlay category on the architectural drawings or construction plans.

Abstract: A predictive memory performance optimizing unit for use with an interleaved memory, for example a DDR SDRAM memory, and suitable for use in a computer graphics system, among others, is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves. The unit utilizes idle cycles occurring between consecutive requests to activate interleaves with pending requests.

Abstract: Positioning a block of graphics memory within a memory system so as to minimize the number of memory devices and/or banks of memory within memory devices occupied by the block of graphics memory so as to maximize the number of memory devices and/or banks of memory within memory devices that are not occupied by even a portion of the block of graphics memory, and thereby, maximize the number of memory devices and/or banks of memory within memory devices that may be placed into a lower power state without causing the block of graphics memory to become inaccessible so as to impair reading out graphics data to support refreshing an image on a display device.

Abstract: A thin client/server network image processing system has a communication network, a thin client system, and a server, which performs a predetermined application at the request of the thin client system according to a thin client/server network environment/architecture (thin server) and transmits a result of performing the application to the thin client system through the communication network. The thin server has an image processor hardware, which accelerates rendering of a graphic signal to be processed at the request of the thin client system and encodes the rendered graphic signal and video signals linked to the graphic signal.

Abstract: Method for controlling a memory in a digital system, including the steps of (a) dividing the memory into a plurality of fixed sized memory blocks, (b) defining at least one of the memory blocks as a compression/decompression region, (c) assigning compression priorities to rest of the memory blocks except the memory blocks defined as the compression/decompression region, and (d) making the memory blocks to deal with an external data received according to an external command, and carrying out compression/decompression of data required in the dealing with the external data at the compression/decompression region according to the compression priorities.

Abstract: A memory model for a run-time environment is disclosed that includes a process-specific area of memory where objects in call-specific area of memory and session-specific area of memory can be migrated to at the end of a database call. User-specific objects can be then migrated to the session-specific area of memory. In one embodiment, the process-specific area of memory can be saved in a disk file and used to hot start another instance of an application server.

Abstract: A data processing system and method in which, by way of example, a memory system is coupled to a video game program processing system. The video game program processing system has a predetermined address space for executing programs stored in a program memory portion of the memory system. The contents of a plurality of storage locations determine a configuration of the memory system depending on which of a plurality of different game programs is to be executed by the video game program processing system.

Abstract: A device for processing images includes a compressing/coding unit which encodes image data including a plurality of color components to produce fixed-length codes, a memory unit which stores therein the codes produced by the compressing/coding unit, a distribution-measurement unit which measures a distribution of the color components concurrently with the encoding of the image data performed by the compressing/coding unit, and a memory-control unit which releases a memory space assigned to part of the codes relating to colors in the memory unit if the distribution-measurement unit detects that the distribution concentrates on a particular color composition, and records data indicative of the particular color composition in the memory unit.

Abstract: A communication system serving as a transmitter terminal and a receiver terminal for communications with a second communication system via a communication line, the communication system includes a storage section for data storage; a communication section for data communications, the communication section being adapted for reception and transmission of data and size information indicative of the size of the data with respect to the second communication system; a detection section for detecting a free space in the storage section; a comparing section for comparing the data size contained in the size information with the size of the free space in the storage section; a calculating section for, if the storage section is short of free space for accommodation of the data size, calculating a waiting period required for recovery from the shortage of the free space in the storage section; and a timer section for timing the lapse of the waiting period.

Abstract: A programmable graphics processor for multithreaded execution of program instructions including a thread control unit. The programmable graphics processor is programmed with program instructions for processing primitive, pixel and vertex data. The thread control unit has a thread storage resource including locations allocated to store thread state data associated with samples of two or more types. Sample types include primitive, pixel and vertex. A number of threads allocated to processing a sample type may be dynamically modified.

Abstract: A content recording apparatus that writes, when a recording instruction is issued, into a first area of a recording medium predetermined information indicating a predetermined value, records into a plurality of partial areas sporadically distributing in a second area of the recording medium a content to which a plurality of markers are assigned in a predetermined manner, and after completing recording the content, writes into a third area of the recording medium link information indicative of a link state among partial areas in which the content is recorded, and updates a value indicated by the predetermined information written in the first area, includes: a predetermined information detector for detecting the latest predetermined information out of the predetermined information written in the first area when a driving power is input; an area detector for detecting from the second area partial areas in a non-link state based on the link information written in the third area when the predetermined information

Abstract: Dynamically constructing a scan line rasterizer in a rasterization engine includes selecting a base rasterizer, obtaining parameters describing the base rasterizer, obtaining at least one replacement block of code, allocating memory for a dynamically constructed rasterizer, copying the base rasterizer into the memory allocated for the dynamically constructed rasterizer, and copying the at least one replacement block into the base rasterizer stored in the memory using the parameters to form the dynamically constructed rasterizer.

Abstract: A method and mechanism for managing graphics data. A graphics unit is coupled to share a cache and a memory with a processor. The graphics unit is configured to partition rendered images into a plurality of subset areas. During the rendering of an image, data corresponding to subset areas of an image which require a relatively high number of accesses is deemed cacheable for a subsequent rendering. During a subsequent image rendering, if the graphics unit is required to evict data from a local buffer, the evicted data is only stored in the shared cache if a prior rendering indicated that the corresponding data is cacheable.

Abstract: Methods and apparatuses for dynamic virtual frame buffer management. At least one embodiment of the present invention dynamically enables or disables the use of a virtual frame buffer, which is not under control of graphics hardware of a data processing system, without restarting the graphical user interface system (e.g., the window system) of the data processing system. For example, in response to the addition or removing of a frame buffer that is under control of a graphics controller (e.g., due to the activation or deactivation of the graphics controller, or the hot plug-in or hot disconnection of the graphics controller), the virtual frame buffer is disabled or enabled respectively.

Abstract: To provide an apparatus for painting figures which is improved in painting capability better than the conventional art even when a path to an external memory section is narrow. In order to simultaneously write previously generated painting information and read data required for generating painting information later in the painting coordinate generating section and the painting information generating section on the painting apparatus, while painting information is generated, first and second buffers are provided as a buffer section for storing painting information generated in the painting information generating section, and address information storing sections corresponding to the first and second buffers are provided as an address generating section for generating an address for storing painting information, which is accumulated in the buffer section, in an external memory section.

Abstract: Graphics resources are virtualized through an interface between graphics hardware and graphics clients. The interface allocates the graphics resources across multiple graphics clients, processes commands for access to the graphics resources from the graphics clients, and resolves conflicts for the graphics resources among the clients.

Abstract: A method for storing data of a plurality of components of an image in a memory system with four banks comprising the steps of (A) placing a first portion of data of a first component of the plurality of components into a first bank of the four banks and (B) placing a second portion of the data of the first component in a second bank of the four banks, where all of the data of the first component is stored in the first and second banks and occupies at least three pages in the memory system.

Abstract: A graphics processor and method for executing a graphics program as a plurality of threads where each sample to be processed by the program is assigned to a thread. Although threads share processing resources within the programmable graphics processor, the execution of each thread can proceed independent of any other threads. For example, instructions in a second thread are scheduled for execution while execution of instructions in a first thread are stalled waiting for source data. Consequently, a first received sample (assigned to the first thread) may be processed after a second received sample (assigned to the second thread). A benefit of independently executing each thread is improved performance because a stalled thread does not prevent the execution of other threads.

Abstract: A graphics system may include a frame buffer and a hardware accelerator. The frame buffer may include a sample buffer and a double-buffered display area. The hardware accelerator may be coupled to the frame buffer, and configured (a) to receive primitives, (b) to generate samples for the primitives based on a dynamically adjustable sample density value, (c) to write the samples into the sample buffer, (d) to read the samples from the sample buffer, (e) to filter the samples to generate pixels, (f) to store the pixels in a back buffer of the double-buffered display area. A host computer may be configured (e.g., by means of stored program instructions) to dynamically update programmable registers of the graphics system to reallocate the sample buffer in the frame buffer in response to user input specifying a change in one or more window size parameters.

Abstract: A graphics memory includes a plurality of memory partitions. A memory controller organizes tile data into subpackets that are assigned to subpartitions to improve memory transfer efficiency. Subpackets of different tiles may be further assigned to subpartitions in an interleaved fashion to improve memory operations such as fast clear and compression.

Abstract: A method and apparatus for allocating computer memory for an aggregate data type is provided, wherein that allocating is based on data that is separate from a type definition. According to one technique, an instruction to construct an instance of an aggregate data type is received. The aggregate data type (and therefore the instance) includes an attribute. It is determined, based on data called a “Constructor Descriptor”, whether memory for that attribute is to be allocated in-line or out-of-line. The Constructor Descriptor is separate from the type definition of the attribute. Memory for the attribute is allocated in-line or out-of-line depending on the determination made. Using this technique, memory allocation can be customized based on, for example, the system resources of a specific computer system. This technique is applicable, for example, to compilers and interpreters of object oriented or record oriented languages.

Abstract: The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.

Abstract: To provide a drawing device with which drawing speed can be increased without escalation of price of it. A drawing device is established as a GPU on an entertainment device to perform the drawing to a frame buffer in terms of one of different interleaved patterns. Each interleaved pattern is specified by a combination of pixel segments in the frame buffer. The GPU identifies the shape of a figure to be drawn and selects the interleaved pattern that fits for the selected shape of the figure. The pixel segments specified in the frame buffer are not overlapped with other pixel segments in the same interleaved pattern regardless of which interleaved pattern is selected.

Abstract: Color caching method used in color matching processing has advantages and disadvantages, and the processing efficiency depends upon an image to be processed. In view of this, color matching calculation and caching for uniquely determining an output color corresponding to an input color are employed to calculate a hit rate per unit block at a checkpoint block when performing color matching processing in block unit having a predetermined pixel size. Based on the calculated hit rate, a caching method to be applied to a block subsequent to the checkpoint block is determined.

Abstract: A method, apparatus, and computer instructions for managing colors in a color table used in displaying graphics. A request is received for a color map. A color map location is set in the color table, wherein the color map location has a starting point. An identification of the starting point for the color map is placed in an entry in a window attribute table. The colors for the color map are loaded into the color table. The starting point of the color map at the color map location is identified using the window attribute table.

Abstract: A graphics system stores graphics data in a dynamic-random-access memory (DRAM) and in a faster static random-access memory (SRAM). A refresh controller reads pixel data from a frame buffer that is usually in the faster SRAM, while one or more video overlay engines read graphics objects from the DRAM. However, large frame buffers may be partially stored in the DRAM. Some of the graphics data read by the video overlay engine may reside in the SRAM. A dual-layer arbiter receives requests from the refresh controller and the overlay engines for access to the SRAM and DRAM. When two requestors request the same memory device, the dual-layer arbiter arbitrates access. However, often the requests are to different memory devices and the dual-layer arbiter can pass the requests through without delay, since separate buses to the DRAM and SRAM can be used simultaneously.

Abstract: A graphics system includes a hardware accelerator and a frame buffer. The frame buffer includes a sample storage area and a double-buffered display pixel area. The hardware accelerator is operable to (a) render a stream of primitives into samples, (b) store the samples into the sample storage area of the frame buffer, (c) read the samples from the sample storage area, (d) filter the samples to generate pixels, and (e) store the pixels into a first buffer of the display pixel area of the frame buffer. Furthermore, the hardware accelerator is operable to perform (a), (b), (c), (d) and (e) one or more times on one or more corresponding streams of primitives to complete a frame of an animation before passing control of the first buffer to a video output processor.

Abstract: A computer implemented method for utilizing graphics memory of a computer system to provide storage for video BIOS initialization. Video BIOS memory is accessed to execute video BIOS initialization routines. A portion of graphics memory is configured for access by the video BIOS initialization routines. Program execution data from the video BIOS initialization routines is then stored in the portion of graphics memory. The program execution data is stored prior to a completion of a video BIOS power on self test.

Abstract: An address converting unit receives pixel coordinates of a display screen in sequence and converts the received pixel coordinates to addresses and offsets. The addresses and offsets obtained from the conversions are stored in buffers in sequence respectively. A buffer controlling unit detects that one of the buffers is full. In response to the detection by the buffer controlling unit, a pixel processing unit modifies pixel data corresponding to the plural addresses read from the memory device according to pixel information. The pixel data stored in the memory device are rewritten according to the pieces of pixel information inputted in correspondence with the pixel coordinates. Therefore, the pieces of pixel data corresponding to the plural addresses are rewritten at a time.

Abstract: System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and fragment types. Memory space allocated may be of a predetermined size for a thread type. Memory locations within a first memory space may be interleaved with memory locations within a second memory space.

Abstract: A graphics system and method for displaying lines on a display device. The system may comprise a sample buffer, a rendering unit and a sample-to-pixel calculation unit. The rendering unit may (a) generate a plurality of sample positions in a two-dimensional space, (b) determine a sample normal distance for each of the sample positions with respect to a line defined by the line-draw command, (c) assign sample values to the sample positions based on the sample normal distance of each of the sample positions, and (d) store the sample values in the sample buffer. The sample-to-pixel calculation unit may read sample values from the sample buffer, filter them to determine a pixel value, and transmit the pixel value to the display device. The rendering unit may render the line sample values with a narrower width to pre-compensate for the line-expanding effect of the filtering performed by the sample-to-pixel calculation unit.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A video memory manager manages and virtualizes memory so that an application or multiple applications can utilize both system memory and local video memory in processing graphics. The video memory manager allocates memory in either the system memory or the local video memory as appropriate. The video memory manager may also manage the system memory accessible to the graphics processing unit via an aperture of the graphics processing unit. The video memory manager may evict memory from the local video memory as appropriate, thereby freeing a portion of local video memory use by other applications. In this manner, a graphics processing unit and its local video memory may be more readily shared by multiple applications.

Abstract: In a graphics processing circuit, up to N sets of state data are stored in a buffer such that a total length of the N sets of state data does not exceed the total length of the buffer. When a length of additional state data would exceed a length of available space in the buffer, storage of the additional set of state data in the buffer is delayed until at least M of the N sets of state data are no longer being used to process graphics primitives, wherein M is less than or equal to N. The buffer is preferably implemented as a ring buffer, thereby minimizing the impact of state data updates. To further prevent corruption of state data, additional sets of state data are prohibited from being added to the buffer if a maximum number of allowed states is already stored in the buffer.

Abstract: The present invention provides a system and method for checking authorization of remote configuration operations. The method comprises storing at least one image frame such that content of the image frame is stored in a plurality of memory pages in a memory. The method further comprises sending the image frame to the display one memory page at a time to refresh the display.

Abstract: Methods and apparatus for use with AGP-capable computer systems are disclosed. Since each AGP-capable chipset can have a unique range of graphics port aperture sizes that it supports, current graphics port aperture drivers are chipset-specific, with hard-coded tables of supported graphics aperture sizes. Described herein is a driver that dynamically ascertains the range of supported graphics aperture port sizes for an attached AGP-capable chipset, thus allowing this driver to be ported between different chipsets without manual reconfiguration and recompiling. The method employed in the driver sends one or more test aperture size values to a register resident in the chipset, and then reads what is written to see if the chipset changed any of the bits of the test value. The method infers supported sizes from examining which, if any bits, were changed by the chipset.

Abstract: One aspect of the invention is a method for representing a scene (S). The method includes providing a higher-level appearance description of an appearance of geometry in a retained-mode representation (13a, 300). The method also includes traversing the retained-mode representation (13a, 300) to provide a final representation (13b, 310, 320) that can be rendered by a graphics pipeline (17).

Abstract: A dynamically configurable portion of a cache shared between central processing and graphics units in a highly integrated multimedia processor is engaged as a secondary level in a hierarchical texture cache architecture. The graphics unit includes a small multi-ported L1 texture cache local to its 2D/3D pipeline that is backed by the relatively large, single ported portion of the shared cache. Leveraging the shared cache as a secondary level texture cache reduces system memory bandwidth and die size without significant sacrifice in performance.