Abstract: A method, apparatus, and computer implemented instructions for managing a set of memory resources used to store texture objects in a data processing system. A texture manager allocates memory to a current texture object in a set of memory resources. A stored texture object, handled by the texture manager, is selectively removed in response to an inability to allocate sufficient memory to the current texture object. The allocating and selectively removing steps are repeated until the current texture object is allocated sufficient memory. The repeating step is halted in response to an absence of any stored texture objects, handled by a texture manager, being present in the first memory resource. Stored texture objects, handled by another texture manager, are selectively removed in response to an inability to allocate sufficient memory to the current texture object. Memory is allocated in the set of memory resources to the current texture object in response to selectively removing stored texture objects.

Abstract: A graphics system may include a frame buffer, a processing device coupled to output data, a multipurpose memory device that includes a plurality of storage locations and is coupled to store data output from the processing device, and a multipurpose memory controller coupled to the multipurpose memory device. The multipurpose memory controller may be configured to allocate a first plurality of the storage locations to a first image buffer configured to store image data, a second plurality of the storage locations to a first texture buffer configured to store texture data, and a third plurality of the storage locations to a first accumulation buffer configured to store accumulation buffer data. The multipurpose memory device may be configured to include a first image buffer, a first texture buffer, and a first accumulation buffer at the same time.

Abstract: If a user wants to store an image acquired from a site and it is determined that the data size of the image acquired from the site is larger than a designated storage frame in a memory region, then it is determined whether or not the number of colors in the pallet of the acquired image data can be reduced. Next, if the number of pallet colors can be reduced, the number of pallet colors is reduced to thereby compress the pallet and the image data is updated based on the compressed pallet. On the other hand, if it is determined that the number of pallet colors cannot be reduced, a control section determines that the image data cannot be registered or stored and abandons the data and a display section displays storage error.

Abstract: A sliding window (block) system incorporating a methodology for providing a processor access to image data is described. In an exemplary embodiment, the system operates as follows. An image is received for processing that has a size that is too large for the processor to access directly. As a result, the sliding window system creates first, second, and third swappable windows (blocks) for accessing image data from the image; each windows is swappable so that any two are available within the memory space of the processor while a third is being loaded in a background memory. The system cycles through the three windows such that, at any given point in time, two of the three windows are affixed in the memory space of the processor as left and right adjacent windows, while the remaining or third window is being loaded in the background (e.g., in a DRAM) as a temporary shadow or background window. After the shadow window is loaded with appropriate image data, it is brought into the foreground (i.e.

Abstract: A display control apparatus contains a video memory, a video memory controller, a color palette memory and a color palette replacer signal generator. The video memory stores display data that are read from a CD-ROM and contain header data (HA-HD), palette data (P0-P2) and bitmap data (BA-BD) in connection with four planes which are combined together to form one frame of picture. The header data contain a color palette pointer (CPP) and a color palette replacer instruction (CPP31) with respect to each of the planes. The video memory controller reads the palette data and bitmap data from the video memory in accordance with addresses designated by the header data. The color palette replacer signal generator generates a color palette replacer signal (COL) based on the header data so as to make determination whether to replace contents of color palettes with respect to the planes respectively.

Abstract: A method and system according to the present invention provide for sharing memory between applications running on one or more CPUs, and acceleration co-processors, such as graphics processors, of a computer system in which the memory may retain its optimal caching and access attributes favorable to the maximum performance of both CPU and graphics processor. The method involves a division of ownership within which the shared memory is made coherent with respect to the previous owner, prior to handing placing the shared memory in the view the next owner. This arbitration may involve interfaces within which ownership is transitioned from one client to another. Within such transition of ownership the memory may be changed from one view to another by actively altering the processor caching attributes of the shared memory as well as via the use of processor low-level cache control instructions, and/or graphics processor render flush algorithms which serve to enforce data coherency.

Abstract: A method, computer program product and system for allocating the memory space in a frame buffer. A Device Dependent Layer (DDX) of an X-server may read command line options or alternatively an option selected by a user. If the command line options or alternatively the user selectable option indicates to allocate the memory space in the frame buffer to support a particular type of stereo, e.g., double buffered stereo, single buffered stereo, then the DDX may allocate the memory space in the frame buffer accordingly. If the memory space of the frame buffer is allocated for single buffered stereo, then the extra memory space in the frame buffer from not supporting double buffered stereo may be allocated for texture and/or off screen caching.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a graphics accelerator and a graphics cache coupled to the graphics accelerator. The graphics cache stores texture data, color data and depth data.

Abstract: A system and method for generating graphics images from 3-dimensional graphics data representing one or more transparent objects and one or more opaque objects are disclosed. Memory locations for storing transparent samples may be provided by reducing the number of opaque samples per pixel as needed, and storing the transparent samples in the memory locations formerly used to store the discarded opaque samples. A plurality of opaque samples for a plurality of sample positions corresponding to a pixel may be initially stored in a sample memory. A transparent sample rendered for one of the plurality of sample positions may replace an opaque sample in another one of the sample positions of the plurality of sample positions. The transparent and opaque samples rendered for the same position may be blended and the blended samples may be filtered at least once per screen refresh cycle to generate output pixels.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: A memory system and methods of operating the same that drastically increase the efficiency in memory use and allocation in graphics systems. In a graphics system using a tiled architecture, instead of pre-allocating a fixed amount of memory for each tile, the invention dynamically allocates varying amounts of memory per tile depending on the demand. In one embodiment all or a portion of the available memory is divided into smaller pages that are preferably equal in size. Memory allocation is done by page based on the amount of memory required for a given tile.

Abstract: A method increases the efficiency of a memory bank and greatly reduces the risk of erasure of frame data which are required for coding, decoding or display. FM1a, FM1b, FM2a and FM2b are the first frame area of the first image sequence, the second frame area of the first image sequence, the first frame area of the second image sequence and the second frame area of the second image sequence, respectively. AD12a and AD12b are the first address start location of the first image sequence and the second address start location of the first image sequence, respectively. The frame sizes SZ1a and SZ1b are reserved from the respective start locations toward higher addresses in the first image sequence, respectively. The frame sizes SZ2a and SZ2b are reserved from AD12b-SZ2a and AD34a-SZ2b toward higher addresses in the second image sequence, respectively.

Abstract: An apparatus and method for allowing color adjustments in display devices is disclosed The apparatus comprises a multi-resolution structure for providing color adjustments; and an interpolator for interpolating at least one offset of the multi-resolution structure. An apparatus and method in accordance with the present invention uses a combination of color look-up tables with different levels of resolution, followed by interpolation to provide a display process which has high resolution but utilizes minimal memory. In so doing, memory is used for high-resolution areas only where needed. The multi-resolution structure is a very good approximation to the theoretical mapping table in the areas where it is needed. At the same time, since the high resolution areas are localized, a significant reduction in memory storage is possible.

Abstract: In accordance with a specific implementation of the present invention, the control portion of a graphics processor receives a command having both a data portion and a data duration portion. When the data duration portion indicates the data is transient data for short-term use, the control portion stores the data associated with the data portion at the first memory partition. When the data duration portion indicates the data is persistent data for long-term use, the control portion stores the data associated with the data portion at a second memory partition. In a multiple processor system, transient data may be stored only in a memory partition associated with a first processor, while persistent data may be stored in multiple memory partitions, one for each graphics processor.

Abstract: Graphical memory access requests are routed to a plurality of bucket buffers. Filled bucket write buffers and empty bucket read buffers are efficiently emptied and filled respectively via a wide memory bus. The bucket sorting apparatus and method is used to increase the locality of memory references and pixel operations within a graphical rendering system. The increased locality increases graphical rendering performance and facilitates the usage of smaller z-buffers, larger tiles, and low-cost dynamic RAM within a graphics pipeline.

Abstract: Methods and apparatus for adjusting the geometry of buffer pages.

Abstract: Embodiments of the present invention are directed to a method and apparatus for hardware acceleration of graphical fill in display systems. In one embodiment, a bit-mask is maintained. The bit-mask, termed the “filled color bitmap”, has one bit for each pixel of the display data. A register, termed the “filled color register”, capable of storing a single color value is maintained. When a write command is executed to fill a portion of the display memory with the same value that is stored in the filled color register, the bits in the filled color bitmap corresponding to the portion of display memory are set equal to 1. In executing other writes, the value is written to display memory and the bits in the filled color bitmap corresponding to the portion of display memory are set equal to 0. In one embodiment, the bitmap is located in a dynamic random access memory (DRAM).

Abstract: A system and method for optimizing the performance of a graphics intensive software program for graphics acceleration hardware. This system and method encompasses a procedure that validates the different functions of a 3D acceleration capable video card, decides whether to use the acceleration hardware and optimizes the software application to selectively use the functions that work on the specific video acceleration card. Functions checked include sub-pixel positioning, opacity, color replacement and fog. If these tests are successful, then the graphics acceleration is used by the software application. However, if the tests are not successful the decision is made not to use graphics accelerator. Those with ordinary skill in the art will realize that it is not necessary to perform all of the tests in a specific order.

Abstract: Systems and methods are disclosed for providing interactive displays of complex virtual environments. Systems and methods consistent with embodiments of the invention may be implemented to generate virtual reality (VR) file(s) from a 3D model of the complex environment. The VR file(s) may include octree and collision detection information that is used to simulate and render frames of the complex environment. During simulation, moving objects may be evaluated to detect for collisions with other objects. Further, during rendering, objects or elements may be dynamically tessellated during run-time operations to actively control their appearance when displayed to a user. Memory management operations for facilitating the display of complex virtual environments are also disclosed, consistent with embodiments of the invention.

Abstract: System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and pixel types. Memory space allocated may be of a predetermined size for a thread type. Memory locations within a first memory space may be interleaved with memory locations within a second memory space.

Abstract: A method of allocating computer memory for a function in a computer program by a chunk manager operable to interface with an operating system of a computer program. The method includes receiving a request for a block of memory for a function in the computer program. The request is modified such that the size of the requested block corresponds to a standard block size selected from a list of standard block sizes. The method further includes locating a first available block of memory having a size within a predefined range around the requested block size. A system for allocating computer memory is also disclosed.

Abstract: Image data having a bit depth of m bits, where m is not a power of two, may be divided into two parts for storage. The first part is the n most significant bits, where n is a power of two. The second part is the k least significant bits, where k=m−n and k<n. For example, 10-bit data may be separated into 8-bit and 2-bit parts. The 8-bit data for a given image is placed in the bitstream as a contiguous block with the end of the data aligned with a memory boundary, such as a page boundary. The 2-bit data is collected into bytes that are placed in the bitstream as a contiguous block. The block of 2-bit data is placed in the bitstream preceding and contiguous with the block of 8-bit data. Padding may be provided to align the beginning of the image data with a memory boundary. The image data for multiple images may be placed in the bitstream contiguously for storage. 10-bit data for an alpha channel, if any, also may be split into 8-bit and 2-bit parts.

Abstract: An initial address register holds a transfer destination address as an initial address. Data is written into an input data register to which a unique address is allocated. The written data is put together into a data block having a predetermined transfer destination data size. This enhances the efficiency of data transfer from a software program for processing data in several byte units to a memory and a coprocessor optimized for data transfer in block units of several tens of bytes, and thus improves system performance.

Abstract: A method, data processing system, and computer instructions for simulating direct frame buffer access. A request for access to a frame buffer memory is received from an application. A portion of system memory is allocated for use as the frame buffer memory in response to receiving the request. A pointer to the portion of system memory is returned to the application. The application writes data to the portion of system memory, treating the portion of system memory like the frame buffer memory.

Abstract: Processing video data with a combination of one or more operations, such as special effects, on a general-purpose computer may be improved by enabling one or more operations to access and process multiple samples of video data from other operations that introduce latencies for each request for data. Operations that introduce latencies include, for example, hardware for decompression and compression, network interfaces, and file systems. Because a computer program to implement the operations may be executed on several different general-purpose platforms, exact specifications of available hardware are not known in advance. For each operation, a computer program determines the available system memory and an amount of data that can be processed by each operation used in a composition or portion of a composition while sharing the available memory with other operations. Available system memory is allocated among the operations being used.

Abstract: A video memory manager manages and virtualizes memory so that an application or multiple applications can utilize both system memory and local video memory in processing graphics. The video memory manager allocates memory in either the system memory or the local video memory as appropriate. The video memory manager may also manage the system memory accessible to the graphics processing unit via an aperture of the graphics processing unit. The video memory manager may evict memory from the local video memory as appropriate, thereby freeing a portion of local video memory use by other applications. In this manner, a graphics processing unit and its local video memory may be more readily shared by multiple applications.

Abstract: A method and apparatus for graphical processing. A logic core to perform pixel fragment manipulation and processing is instantiated on a single substrate with one or more memory units. The memory units are dynamically segmentable into frame buffer and texture memory. Because the logic core is on the same substrate as the memory units, the bandwidth between the core and the memory is greatly increased.

Abstract: In a memory consolidated image processing LSI for reading data, a DRAM for storing image data for a plurality of page ranges which are formed by segmenting an image plane corresponding to a display screen in order to page-access a memory region of the DRAM, and image data for a plurality of word ranges which are formed by segmenting each of the page ranges in order to word-access the memory region, is consolidated with an image processing circuit. The size of each of the page ranges is set so that the multiplied value of the power consumption per pre-charge in a power consumption model of a memory by an average number of pre-charges is the substantially minimum value, and the size of each of the word ranges is set so that the multiplied value of the power consumption per word access in the power consumption model of the memory by an average number of word accesses is the substantially minimum value.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A method and apparatus for arranging fragments in a graphics memory. Each pixel of a display has a corresponding list of fragments in the graphics memory. Each fragment describes a three-dimensional surface at a plurality of sample points associated with the pixel. A predetermined number of fragments are statically allocated to each pixel. Additional space for fragment data is dynamically allocated and deallocated. Each dynamically allocated unit of memory contains fragment data for a plurality of pixels.

Abstract: Memory is allocated for use by a graphics processor. Available portions of system memory are identified by requesting an amount of system memory from an operating system and receiving locations of the available portions from the operating system. Those available portions are then allocated for use by the graphics processor.

Abstract: A video capture system and method whereby video frames or images, which are received in one of a plurality of possible formats, are acquired and stored into on-board memory in an image format. The image data can then be transferred into system memory at an optimum rate. The video capture system comprises a host computer, including a video capture board, which is coupled to a video source, such as a video camera. The video source provides digital video data in a first format of a plurality of different possible formats. The video capture board includes a memory controller which receives the digital video data in the first format and selectively provides the digital video data to the buffer memory in an image format. The memory controller includes address generation logic for generating buffer memory addresses for storing the video data to the buffer memory in the image format.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A video graphics system (300) employs a method and apparatus for efficiently processing vertex information required to render graphics primitives requested for display by an application (313), such as a video game. The video graphics system includes a graphics driver (317), a graphics processor (305), a memory component (309, 321) that is accessible by the graphics processor, and a memory component (319) that is inaccessible by the graphics processor. After receiving, from the application, a drawing command that includes vertex indices and a reference to a vertex buffer (325) stored in the graphics processor-inaccessible memory component, the graphics driver allocates a new temporary vertex buffer (327) in the graphics processor-accessible memory component and copies the contents of the graphics processor-inaccessible vertex buffer into the temporary vertex buffer.

Abstract: A graphics system in which the dedicated graphics memory is doubly virtualized: it can be paged into host physical memory, and also, beyond that, into host bulk storage. Portions of host physical memory which are needed to support the graphics memory management process can be locked down.

Abstract: The present invention relates to a system and method for accelerating graphics. The system includes a memory device for accelerating graphics operations within an electronic device. A memory controller is used for controlling pixel data transmitted to and from the memory device. A cache memory is electrically coupled to the memory and is dynamically configurable to a selected usable size to exchange an amount of pixel data having the selected usable size with the memory controller. The memory device may be an SDRAM. The cache memory may also comprise a plurality of usable memory areas or tiles.

Abstract: Dynamically constructing a scan line rasterizer in a rasterization engine includes selecting a base rasterizer, obtaining parameters describing the base rasterizer, obtaining at least one replacement block of code, allocating memory for a dynamically constructed rasterizer, copying the base rasterizer into the memory allocated for the dynamically constructed rasterizer, and copying the at least one replacement block into the base rasterizer stored in the memory using the parameters to form the dynamically constructed rasterizer.

Abstract: Methods and systems for optimizing graphics data processing employ various binning flush algorithms to optimize the utilization of binning memory in a graphics system. Binning flush algorithms provide for processing all geometry and commands binned up to the point the binning memory becomes unavailable, and storing and restoring all necessary intermediate data generated during the partial tile rendering.

Abstract: A memory system and method for allocating and accessing memory. The memory system includes first and second addressable memory regions coupled to a memory controller. The memory controller includes a register to store a respective offset value and values defining portions of the first and second addressable memory regions allocated to first and second logical memory spaces. A first portion of the first addressable memory region is allocated to a first requested memory space, and a second portion of the first addressable memory region is allocated to a second requested memory space. Any remaining portions of the first and second requested memory spaces are remapped to the second addressable memory region.

Abstract: A system and method for asynchronously processing video images are provided. A video processing computing device includes one or more video capture boards in communication with a number of image capture devices, such as video cameras. The video image processing computing device includes a video collection application that is operable to instruct the video capture board to acquire video data and store the data in a shared memory area. The video processing computing device also includes a video processing application that is operable to acquire the stored video from the shared memory area and process the video data. By utilizing a shared memory area, the video collection application and the video processing application can process data asynchronously.

Abstract: A telecom mask testing zoom function draws mask. pixels into a raster memory. In this way, the mask is treated as a waveform. Comparison of the mask pixels and waveform pixels to detect collision between a waveform pixel and a mask pixel (i.e., a mask violation) is performed substantially in real time, as the pixels are being composited into the raster memory by the rasterizer. The mask is scalable and repositionable by the rasterizer under control of a controller, because it is treated as a waveform. The mask is lockable to the waveform because both are stored in pixel form in raster memory by the rasterizer under control of the controller.

Abstract: A polygon rendering system for receiving geometric data defining a polygon in an image being generated. The polygon rendering system renders the geometric data as pixel data. The pixel data defines pixels used to display the image. The system comprises a first memory buffer for storing the pixel data. It also comprises a second memory buffer for storing additional pixel data used to render edge pixels at a higher resolution than pixels that are not the edge pixels. Edge pixels are pixels that are located on an edge of the polygon in the image. The system also comprises a display controller for outputting the pixel data in the first memory buffer to output circuitry. The polygon rendering system identifies which of the pixels are the edge pixels and the display controller updates contents of the first buffer with data based on contents of the second buffer.

Abstract: The process for storing, in pages of a memory, image blocks (h, v) consisting of v lines of h pixels, for the reading of image blocks (H, V) consisting of V lines of H pixels, is characterized in that the horizontal shift DI, I+a, in terms of number of blocks (h, v), of the boundary of a page corresponding to any row I of the image with respect to the boundary of a page corresponding to a row I+a is equal to: DI, I+a=a D, ∀ positive integer a less than RM=INT [(V−2)/v]+2, (INT corresponding to the integer part of the division) the value D, which corresponds to the shift between two successive rows being chosen such that: D≧(BM−1), with BM=INT [(H−2)/h]+2. Applications relate, for example to motion estimation and motion compression.

Abstract: Methods and apparatus for use with AGP-capable computer systems are disclosed. Since each AGP-capable chipset can have a unique range of graphics port aperture sizes that it supports, current graphics port aperture drivers are chipset-specific, with hard-coded tables of supported graphics aperture sizes. Described herein is a driver that dynamically ascertains the range of supported graphics aperture port sizes for an attached AGP-capable chipset, thus allowing this driver to be ported between different chipsets without manual reconfiguration and recompiling. The method employed in the driver sends one or more test aperture size values to a register resident in the chipset, and then reads what is written to see if the chipset changed any of the bits of the test value. The method infers supported sizes from examining which, if any bits, were changed by the chipset.

Abstract: A graphics system may include a frame buffer, a processing device coupled to output data, a multipurpose memory device that includes a plurality of storage locations and is coupled to store data output from the processing device, and a multipurpose memory controller coupled to the multipurpose memory device. The multipurpose memory controller may be configured to allocate a first plurality of the storage locations to a first image buffer configured to store image data, a second plurality of the storage locations to a first texture buffer configured to store texture data, and a third plurality of the storage locations to a first accumulation buffer configured to store accumulation buffer data. The multipurpose memory device may be configured to include a first image buffer, a first texture buffer, and a first accumulation buffer at the same time.

Abstract: A pull-model system and method provides display data over a network to a plurality of display devices having the same or different video format requirements. Utilization of image memory bandwidth is balanced between the plurality of display devices. Based on image memory bandwidth requirements for the plurality of display devices, a bandwidth allocation table is generated to indicate a servicing priority for the display devices. A plurality of requests for pixel data are received and stored in a request buffer. The requests are then serviced in an order indicated by the bandwidth allocation table.

Abstract: Memory is allocated for use by a graphics processor. Available portions of system memory are identified by requesting an amount of system memory from an operating system and receiving locations of the available portions from the operating system. Those available portions are then allocated for use by the graphics processor based at least in part on the devices in which the available portions are located.

Abstract: On-screen-display graphics data is transmitted from a source device to a display device over an IEEE 1394-1995 serial bus network utilizing an isochronous data format. The on-screen-display graphics data is generated by the source device and transmitted to a display device, as a stream of isochronous data, separate from video data. Each packet of isochronous data within the stream of on-screen-display graphics data includes an address value corresponding to a memory address within the display device forming a buffer. When received by the display device the on-screen-display graphics data is loaded into the appropriate memory locations within the buffer corresponding to the address values. At the display device, an embedded stream processor is utilized to strip the header information from each packet and determine the appropriate memory location that the data is to be stored. A trigger packet is sent at the end of the data stream for a screen of on-screen-display graphics.

Abstract: An image display device includes a display panel having predetermined numbers of pixels defined in horizontal and vertical directions, respectively, and an interpolated-data generation circuit whereby an expanded image data is produced in such a manner that when the number of pixels in the horizontal direction of the display panel is greater than the number of pixels in the horizontal direction of a given image signal, the interpolated-data generation circuit directly stores a plurality of image data A, B, C, D, E of the original image signal along one horizontal line at data storage locations closest to the original locations, and data at data storage locations remaining after storing all original data are given the results X, Y, and Z obtained by calculation from two original image data at locations adjacent to the respective remaining data storage locations thereby expanding the original image signal to have a resolution well matched to the resolution of the display panel without causing a reduction in con

Abstract: The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.