Texture Memory Patents (Class 345/552)
  • Patent number: 10154072
    Abstract: In various embodiments, methods and systems for intelligent streaming of game content based on the level of interactivity of the game content are provided. The level of interactivity of game content is determined using techniques that classify the level of interactivity. The level of interactivity is defined for different components of game content. Streaming techniques are associated with game content having specific levels of interactivity. An edge computing infrastructure may facilitate intelligent streaming in that game assets classified as prefetch game assets or stream game assets are associated with prefetch instructions. The prefetch instructions are communicated from a game server to a game platform to instruct the game platform to prefetch a prefetch game asset to the edge computing infrastructure in advance of an anticipated game context in which the prefetch game asset is used. During the anticipated game context, the assets are retrieved for output at the game platform.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: December 11, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John Raymond Justice, Euan Peter Garden
  • Patent number: 10127707
    Abstract: A tile identifier may be assigned to tiles processed in order in a pixel shader. When the tiles are processed out of order in the pixel shader, the tile identifier may be used to determine when rendering is complete and a tile may be discarded.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventor: Prasoonkumar Prasoon Surti
  • Patent number: 10115177
    Abstract: A method of variable rate compression of image data in an image pipeline of a graphics processing system, the method includes identifying, by a processor of the graphics processing system, a set of cTiles associated with the image data, each cTile including a plurality of pixels, for each cTile of the set of cTiles identifying, by the processor, a pivot pixel from among the plurality of pixels, identifying, by the processor, a compression type of the cTile by comparing, bit-by-bit , pixels within the cTile with the pivot pixel, and compressing, by the processor, the cTile based on the identified compression type, and generating, by the processor, a metadata entry associated with the set of cTiles, the metadata entry indicating the compression type of each one of the set of cTiles and defining a mapping between an uncompressed address space of the set of cTiles and a compressed address space.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: October 30, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Abhinav Golas, Sangheon Lee, Vandit Mehra
  • Patent number: 10015250
    Abstract: Cache controller (120) for use in a system (180) comprising an image client (100) and an image server (140), the image client enabling a user to navigate through image data having at least three spatial dimensions by displaying views of the image data that are obtained from the image server in dependence on navigation requests of the user, and the cache controller comprising a processor (122) configured for obtaining content data indicative of a content shown in a current view of the image client (100), the current view representing a first viewpoint in the three spatial dimensions of the image data, the processor being further configured for predicting a view request of the image client in dependence on the content data, the view request corresponding to a view representing a second viewpoint in the three spatial dimensions of the image data, and a communication means (124) for obtaining the view from the image server in dependence on the view request, and for caching the view in a cache (130).
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: July 3, 2018
    Assignee: Koninklijke Philips N.V.
    Inventors: Fabian Wenzel, Thomas Netsch, Sebastian Peter Michael Dries
  • Patent number: 9984475
    Abstract: A palette compressed representation may be stored in the index bits, when that is possible. The savings are considerable in some embodiments. In uncompressed mode, the data uses 2304 (2048+256) bits, and in compressed mode, the data uses 1280 bits. However, with this technique, the data only uses the index bits, (e.g. 256 bits) with a 5:1 compression improvement over the already compressed representation, and with respect to the uncompressed representation it is a 9:1 compression ratio.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: May 29, 2018
    Assignee: Intel Corporation
    Inventor: Tomas G. Akenine-Moller
  • Patent number: 9928639
    Abstract: A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: March 27, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Michael Toksvig, Erik Lindholm
  • Patent number: 9892551
    Abstract: The avionics display system is for displaying a scene in an aircraft cockpit. The avionics display system includes a central processing unit CPU, a graphics processing unit GPU operably coupled to the CPU, and a display. The GPU comprises at least one vertex shader, and the CPU is configured to provide vertex data representing at least one graphics primitive to the at least one vertex shader and to call the at least one vertex shader in order to render the at least one graphics primitive, representing at least a part of the scene, into a frame buffer. The display is operably coupled to the frame buffer and displays the scene. The system architecture of the avionics display system simplifies the coding process for the developer and also speeds up image processing in comparison to conventional systems.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: February 13, 2018
    Assignee: GE AVIATION SYSTEMS LIMITED
    Inventor: Lewis William Catton
  • Patent number: 9892555
    Abstract: Systems and methods for reducing the amount of texture cache memory needed to store a texture atlas by using uniquely grouped refined triangles to create each texture atlas.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: February 13, 2018
    Assignee: LANDMARK GRAPHICS CORPORATION
    Inventors: Zitao Xu, Venkatraman Viswanathan, Scott Senften, Charles Sembroski, Ya Sun, Mary Cole
  • Patent number: 9892480
    Abstract: According to some embodiments, a graphics processor may abort a workload without requiring changes to the kernel code compilation or intruding upon graphics processing unit execution. Instead, it is possible to only read the predicate state once before starting and once before restarting a workload that has been preempted because the user wishes to abort the work. This avoids the need to read from each execution unit, reducing the drain on memory bandwidth and increasing power and performance in some embodiments.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventor: Jayanth N. Rao
  • Patent number: 9883122
    Abstract: A method of event-based down sampling includes receiving multiple sensor events corresponding to addresses and time stamps. The method further includes spatially down sampling the addresses based on the time stamps and the addresses. The method may also include updating a pixel value for each of the multiple sensor events based on the down sampling.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: January 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Venkat Rangan, William Howard Constable, Xin Wang, Manu Rastogi
  • Patent number: 9824488
    Abstract: Systems and methods for rendering 2D grids using texture mapping and fragment shaders.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: November 21, 2017
    Assignee: LANDMARK GRAPHICS CORPORATION
    Inventor: Venkatraman Viswanathan
  • Patent number: 9794580
    Abstract: A signal processing system for motion pictures includes a signal processing module, a cache, an analysis module and a control module. The signal processing module performs a signal processing process on motion picture data. The cache temporarily stores a set of reference data that is required for processing the motion picture during the signal processing process. The analysis module generates cache miss analysis information associated with the signal processing process and the cache. The control module determines an index content configuration of the cache according to the cache miss analysis information.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: October 17, 2017
    Assignee: MStar Semiconductor, Inc.
    Inventor: He-Yuan Lin
  • Patent number: 9779542
    Abstract: An apparatus and method are described for implementing flexible finite differences in a graphics processor. For example, one embodiment of a graphics processor comprises: pixel shading logic to perform pixel shading operations on pixels associated with a rasterized primitive using covered pixels and uncovered pixels; and helper pixel selection logic to select helper pixels in the rasterized primitive, the helper pixels to be used by the pixel sharing logic for gradient computations, wherein for one or more of the covered pixels, the helper pixel selection logic attempts to identify one or more suitable covered helper pixels and, if no suitable covered helper pixels exist, identifies one or more uncovered helper pixels.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventor: Franz Petrik Clarberg
  • Patent number: 9760966
    Abstract: A system and method for performing computer algorithms. The system includes a graphics pipeline operable to perform graphics processing and an engine operable to perform at least one of a correlation determination and a convolution determination for the graphics pipeline. The graphics pipeline is further operable to execute general computing tasks. The engine comprises a plurality of functional units operable to be configured to perform at least one of the correlation determination and the convolution determination. In one embodiment, the engine is coupled to the graphics pipeline. The system further includes a configuration module operable to configure the engine to perform at least one of the correlation determination and the convolution determination.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: September 12, 2017
    Assignee: Nvidia Corporation
    Inventors: Guillermo Savransky, Joseph Stam
  • Patent number: 9734598
    Abstract: An engine decompresses texture data belonging to a virtual texture stored in processor readable memory so that decompressed texture data may be used to update a selected sub-image of a large texture image used to render a CGI. The updated sub-image may be at any location in the larger texture image. A processor executes an application to provide control information to the engine. The control information may include commands to decode compressed texture data at source addresses and provide a stream of decompressed virtual texture data to selected sub-image destination addresses in a texture buffer used for rendering a CGI. Similarly, the engine may compress texture sub-image information and store the compressed result at a destination address.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: August 15, 2017
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Mark Grossman
  • Patent number: 9697006
    Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 4, 2017
    Assignee: NVIDIA Corporation
    Inventors: Brian Fahs, Eric T. Anderson, Nick Barrow-Williams, Shirish Gadre, Joel James McCormack, Bryon S. Nordquist, Nirmal Raj Saxena, Lacky V. Shah
  • Patent number: 9679342
    Abstract: A graphics processing pipeline includes a vertex transformation stage 14 having a vertex transformation cache 20. If a request to transform vertex data is received and the vertex transformation cache 20 indicates that the transformed vertex data for that received request has already been generated, then a pointer to that previously generated transformed vertex data is output within a result data stream in place of the transform vertex data. The transform vertex data is stored to a memory 10 before being retrieved as required by a rasterization stage 16.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: June 13, 2017
    Assignee: ARM Limited
    Inventors: Alexander Eugene Chalfin, Bradley Albert Grantham
  • Patent number: 9659399
    Abstract: A system, method, and computer program product are provided for passing attribute structures between shader stages of a processing pipeline. The method includes the steps of receiving data represented at a first level by a processing pipeline including an upstream shader unit, a downstream shader unit, and a processing unit. The upstream shader unit processes the data to generate a first set of attributes corresponding to the data represented at a second level. The upstream shader unit also stores the first set of the attributes in a first portion of a memory system that can be read by the downstream shader unit and any shader units that are downstream in the processing pipeline relative to the upstream shader unit. In one embodiment, the processing unit is coupled between the upstream shader unit and the downstream shader unit.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: May 23, 2017
    Assignee: NVIDIA Corporation
    Inventors: Ziyad Sami Hakura, Henry Packard Moreton, Emmett M. Kilgariff
  • Patent number: 9581452
    Abstract: An apparatus and method are provided. A hierarchical navigation database with multiple levels including tiles is defined. Link data records representative of a road segments are stored in the hierarchical navigation database. A lower level tile containing a starting point data record of a route is identified. A link data record crossing the lower level tile border is identified. Whether the identified link data record also crosses a tile border of a higher level tile is determined. If the identified link data record crosses a tile border of a higher level tile, whether the higher level tile includes a destination point record is determined. Unless the higher level tile is determined to include the destination point record, a next link data record is determined in the route from the higher level.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: February 28, 2017
    Assignee: HERE Global B.V.
    Inventor: Martin Pfeifle
  • Patent number: 9569883
    Abstract: In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Karthik Vaidyanathan, Marco Salvi, Robert M. Toth
  • Patent number: 9544658
    Abstract: According to the present invention, even when the operation requested through the second transmission path (or first transmission path) cannot be performed, it is possible to perform the requested operation by using the function of the device coupled to the first transmission path (or second transmission path).
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: January 10, 2017
    Assignee: HITACHI MAXELL, LTD.
    Inventors: Mayuko Tanaka, Nobuaki Kabuto
  • Patent number: 9483843
    Abstract: The present document describes a method and system for expediting bilinear filtering of textures, by reducing the number of data load operations. The method expands the original data layout with additional borders containing replicated texels. The replicated texels correspond either to wrapped-around texels for two-dimensional textures or neighboring faces in cube textures. Therefore, a 2×2 filter kernel for bilinear filtering is built which requires only one texel address to be computed, with all texel data readable with two load operations which are a predetermined stride apart. Different addressing modes are implemented by adjusting the sampling locus.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: November 1, 2016
    Assignee: Transgaming Inc.
    Inventor: Nicolas Capens
  • Patent number: 9443279
    Abstract: Systems, apparatus, articles, and methods are described including operations to communicate synchronization notifications between a co-processor graphic data producer and a co-processor graphic data consumer via a direct link without passing such communications through the central processing unit.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: September 13, 2016
    Assignee: INTEL CORPORATION
    Inventor: Minjiao Ye
  • Patent number: 9361731
    Abstract: Exemplary embodiments disclose a method of projecting an image onto a surface of a three-dimensional (3D) electronic map. The method includes: extracting nearest intersecting points for each of a plurality of virtual view angle vectors with respect to a position of a virtual photographing apparatus and a plurality of polygons that constitute the 3D electronic map; comparing 3D coordinates of the extracted nearest intersecting points and 3D coordinates of a plurality of pixels constituting the plurality of polygons to select pixels that are within a range of the 3D coordinates of the extracted nearest intersecting points; converting 3D coordinates of the selected pixels to two-dimensional (2D) coordinates to display the selected pixels on a 2D display; and superimposing an input image on top of the selected pixels to output the superimposed image in real-time.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: June 7, 2016
    Assignee: Hanwha Techwin Co., Ltd.
    Inventor: Sung-Duck Kim
  • Patent number: 9355484
    Abstract: A device selectively loads map tiles into its memory while re-using others. As a user chooses different sections of a master map to be displayed, the device determines an intersection between the formerly and currently viewed sections. The device copies selected references to map tiles in the intersection, with some re-indexing, from an array for the formerly displayed section into an array for the newly displayed section. The view of the map might be a three-dimensional perspective view of a two-dimensional surface. The device can create bounding boxes around polygonal perimeters of the viewed areas. The bounding boxes are divided into rectangles corresponding to the tiles located on the master map. The device determines which rectangles within the bounding boxes both (a) contain portions of their respective polygons and (b) overlap each other respective to their locations on the master map. The device already stores map tiles for those rectangles.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: May 31, 2016
    Assignee: APPLE INC.
    Inventor: Alexis Allison Iskander
  • Patent number: 9244833
    Abstract: FLASH memory is allocated to provide a data-storage device and management tables. The management tables may record logical-to-physical address mapping information in a hierarchical structure consisting of at least two levels. Further, in addition to the logical-to-physical address mapping information, the management tables may further provide a valid page count table and an invalid block record. The logical-to-physical address mapping information is updated after an update of the valid page count table is completed. The invalid block record is maintained based on the valid page count table.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: January 26, 2016
    Assignee: SILICON MOTION, INC.
    Inventor: Chang-Kai Cheng
  • Patent number: 9110815
    Abstract: Various embodiments for improving hash index key lookup caching performance in a computing environment are provided. In one embodiment, for a cached fingerprint map having a plurality of entries corresponding to a plurality of data fingerprints, reference count information is used to determine a length of time to retain the plurality of entries in cache. Those of the plurality of entries having a higher reference counts are retained longer than those having lower reference counts.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: August 18, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph Smith Hyde, II, Subhojit Roy
  • Patent number: 9092456
    Abstract: A method and system for reconstructing an image displayed on an electronic device connected to a network, to be a high resolution image. The method of reconstructing a selected area of the image displayed on the electronic device connected to a network, to be a high resolution image, includes: receiving a request to expand the selected area; collecting images including the selected area from the Internet; correcting the selected area to have a high resolution while expanding the selected area based on the collected images; and displaying the image expanded to have a high resolution on the electronic device.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: July 28, 2015
    Assignee: Korea Institute of Science and Technology
    Inventors: Jaewon Kim, Ig Jae Kim, Sang Chul Ahn, Jong-Ho Lee
  • Patent number: 9041723
    Abstract: Each block of texture data elements is encoded as a block of texture data that includes a set of integer values to be used to generate a set of base data values for the block, and a set of index values indicating how to use the base data values to generate data values for the texture data elements that the block represents. The integer values and the index values are both encoded in an encoded texture data block using a combination of base-n values, where n is greater than two, and base-2 values. Predefined bit representations are used to represent plural base-n values (n>2) collectively, and the bits of the bit representations representing the base-n values are interleaved with bits representing the base-2 values in the encoded texture data block.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: May 26, 2015
    Assignee: ARM LIMITED
    Inventors: Jorn Nystad, Anders Lassen
  • Publication number: 20150130826
    Abstract: For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2×2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Inventors: Liang Peng, Steven Spangler
  • Patent number: 9024959
    Abstract: A method and system may include a chip having graphics rendering hardware, a cache and a processor to execute an application with texture allocation logic to receive notification of a page miss from the graphics rendering hardware. The logic can map the page miss to a tile of a texture image, store the tile as an entry to the cache, and map the entry to a virtual address space of a virtual image corresponding to the texture image. The system may also include off-chip memory to store the texture image.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: May 5, 2015
    Assignee: Intel Corporation
    Inventors: Jean-Luc Duprat, Paul Lalonde, Andrew T Forsyth
  • Patent number: 9019292
    Abstract: Methods are provided for reordering operations in execution of an effect graph by graphics processing unit. Memory availability is evaluated for storing images rendered using the effect graph. Memory is allocated for multiple parallel intermediate textures that store images. Operations that write to these textures are executed. It is then determined that there is not sufficient memory to perform additional parallel operations. The memory currently allocated is flushed, and memory for an upper-level texture is allocated. The operations that write pixels to the upper-level texture are executed.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: April 28, 2015
    Assignee: Microsoft Technology Licensing LLC
    Inventors: Jeffrey R. Bloomfield, Stephen P. Proteau, Michael Vincent Onepro
  • Publication number: 20150109315
    Abstract: A system, method, and computer program product are provided for mapping tiles to physical memory locations. In use, a plurality of virtual tiles associated with a texture is identified. Additionally, a request to perform a mapping of the plurality of virtual tiles to one or more physical memory locations is received. Further, the plurality of virtual tiles is mapped to the one or more physical memory locations, utilizing a page table.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 23, 2015
    Applicant: NVIDIA Corporation
    Inventors: Amanpreet Grewal, Andrei Khodakovsky, Yu Denny Dong, Henry Packard Moreton, Naveen Leekha
  • Patent number: 9013499
    Abstract: A method for a computer system including receiving a file comprising textures including a first and a second texture map, which can be regular or irregular texture maps, and metadata, wherein the metadata includes identifiers associated with texture maps and includes adjacency data, associating the first texture map with a first face of an object in response to an identifier associated with the first texture map, associating the second texture map with a second face of the object in response to an identifier associated with the second texture map, determining an edge of the first texture map is adjacent to an edge of the second texture map in response to the adjacency data, and performing a rendering operation with respect to the first and second faces of the object to determine rendering data in response to the first and second texture maps.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: April 21, 2015
    Assignee: Disney Enterprises, Inc.
    Inventors: Brent D. Burley, Christian Eisenacher
  • Patent number: 9007389
    Abstract: Embodiments of the present invention are directed towards increasing texture filtering performance for texel components represented by more than 8 bits. As the number of bits per component increases, the number of texels that are processed each clock cycle decreases since more bits need to be processed to produce each filtered result. A filtered result may be accumulated over two or more iterations, with each iteration producing a portion of the filtered result. When only a portion of the components for each texel are used, the unused texel components are not processed. Elimination of unnecessary texel processing for unused texel components may improve texture filtering performance.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: April 14, 2015
    Assignee: NVIDIA Corporation
    Inventor: Paul S. Heckbert
  • Publication number: 20150097851
    Abstract: A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 9, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Eric T. ANDERSON, Poornachandra RAO
  • Publication number: 20150084975
    Abstract: Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Steven J. HEINRICH, Eric T. ANDERSON, Jeffrey A. BOLZ, Jonathan DUNAISKY, Ramesh JANDHYALA, Joel MCCORMACK, Alexander L. MINKIN, Bryon S. NORDQUIST, Poornachandra RAO
  • Publication number: 20150070371
    Abstract: Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed.
    Type: Application
    Filed: September 6, 2013
    Publication date: March 12, 2015
    Inventor: Bimal Poddar
  • Publication number: 20150049104
    Abstract: One embodiment of the present invention includes techniques for processing a multi-resolution hierarchy, where an application configures a ROP unit to render all the levels included in the multi-resolution hierarchy to a single composite render target. The ROP unit renders memory pages to the composite render target in pitch order. In contrast, the texture unit accesses the composite render target with memory pages in pitch order for each level of the hierarchy. The application configures the MMU to ensure that the composite render target is correctly interpreted by the texture unit. Notably, the MMU translates ROP unit virtual addresses and texture unit virtual addresses using different mapping strategies to the same physical address space. One advantage of the disclosed embodiments is that rendering to the multi-resolution hierarchy does not require the CPU to execute the state parameter changes that are associated with rendering the different hierarchical levels using prior-art techniques.
    Type: Application
    Filed: August 16, 2013
    Publication date: February 19, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Eric B. LUM, Henry Packard MORETON
  • Patent number: 8933925
    Abstract: Methods, systems, and computer-readable media for reconstruction a three-dimensional scene from a collection of two-dimensional images are provided. A computerized reconstruction system executes computer vision algorithms on the collection of two-dimensional images to identify candidate planes that are used to model visual characteristics of the environment depicted in the two-dimensional images. The computer vision algorithms may minimize an energy function that represents the relationships and similarities among features of the two-dimensional images to assign pixels of the two dimensional images to planes in the three dimensional scene. The three-dimensional scene is navigable and depicts viewpoint transitions between multiple two-dimensional images.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: January 13, 2015
    Assignee: Microsoft Corporation
    Inventors: Sudipta Narayan Sinha, Drew Edward Steedly, Richard Stephen Szeliski
  • Publication number: 20140368521
    Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.
    Type: Application
    Filed: May 2, 2014
    Publication date: December 18, 2014
    Applicant: ARM Limited
    Inventors: Anders Lassen, Jorn Nystad, Alexis Mather, Sean Tristram Ellis
  • Publication number: 20140327688
    Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.
    Type: Application
    Filed: May 2, 2013
    Publication date: November 6, 2014
    Applicant: ARM Limited
    Inventor: ARM Limited
  • Patent number: 8878864
    Abstract: Information to be sent over a network, such as the Ethernet, is packetized by using a graphics processing unit (GPU). The GPU performs packetization of data with much higher throughput than a typical central processing unit (CPU). The packetized data may be output through an Ethernet port, video port, or other port of an electronic system.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: November 4, 2014
    Assignee: Barco, Inc.
    Inventors: Ian Baxter, Chris S. Byrne
  • Patent number: 8872839
    Abstract: Performing real-time atlasing of graphics data and creation and maintenance of texture atlases for applications having dynamic graphics content. Embodiments include allocating a texture atlas configured to store textural elements for use in rendering graphical elements, and providing a graphics processing unit (GPU) access to the texture atlas. During subsequent execution of an application, when a graphical element of the application is to be rendered by the GPU, a block of space can be allocated within the texture atlas and a textural element corresponding to the graphical element can be stored within the allocated block. The GPU therefore has access to the textural element when rendering the graphical element.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: October 28, 2014
    Assignee: Microsoft Corporation
    Inventors: Brendan J. Clark, Ashraf Michail, Bede Jordan, George Xin Gao
  • Patent number: 8866834
    Abstract: A sprite capture and reproduction system for a gaming machine is disclosed. A sprite is a graphic image that can move within a larger graphic image. The system includes a sprite capture component and a sprite reproduction component. The sprite capture component enables capture of a sprite in video memory for use as another sprite. The sprite reproduction component enables reproduction of independent animated images that are combinable in a larger animation. The system does not require a discreet texture for each and every image that is loaded. Additionally, the system dramatically increases likelihood that desired images are resident and available for use in video memory, thereby saving texture memory. Further, the system minimizes shadow RAM usage.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: October 21, 2014
    Assignee: Bally Gaming, Inc.
    Inventor: James Lawrence
  • Patent number: 8860743
    Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: October 14, 2014
    Assignee: Nvidia Corporation
    Inventors: Andrew Tao, Jerome F. Duluk, Jr., Jesse D. Hall, Henry Moreton
  • Patent number: 8823724
    Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: September 2, 2014
    Assignee: Nvidia Corporation
    Inventors: Jerome F. Duluk, Jr., Andrew Tao, Bryon Nordquist, Henry Moreton
  • Patent number: 8817035
    Abstract: Circuits, methods, and apparatus that perform a context switch quickly while not wasting a significant amount of in-progress work. A texture pipeline includes a cutoff point or stage. After receipt of a context switch instruction, texture requests and state updates above the cutoff point are stored in a memory, while those below the cutoff point are processed before the context switch is completed. After this processing is complete, global states in the texture pipeline are stored in the memory. A previous context may then be restored by reading its texture requests and global states from the memory and loading them into the texture pipeline. The location of the cutoff point can be a point in the pipeline where a texture request can no longer result in a page fault in the memory.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: August 26, 2014
    Assignee: NVIDIA Corporation
    Inventor: Alexander L. Minkin
  • Patent number: 8810590
    Abstract: A method and apparatus for sorting data into spatial bins or buckets using a graphics processing unit (GPU). The method takes unsorted point data as input and scatters the points, in sorted order, into a set of bins. This key operation enables construction of a spatial data structure that is useful for applications such as particle simulation or collision detection. The disclosed method achieves better performance scaling than previous methods by exploiting geometry shaders to progressively trim the size of a working set. The method also leverages predicated rendering functionality to allow early termination without CPU/GPU synchronization. Furthermore, unlike previous techniques, the method can guarantee sorted output without requiring sorted input. This allows the method to be used to implement a form of bucket sort using the GPU.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: August 19, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher Oat, Shopf Jeremy, Joshua D. Barczak
  • Publication number: 20140204098
    Abstract: A system, method, and computer program product are provided for GPU demand paging. In operation, input data is addressed in terms of a virtual address space. Additionally, the input data is organized into one or more pages of data. Further, the input data organized as the one or more pages of data is at least temporarily stored in a physical cache. In addition, access to the input data in the physical cache is facilitated.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 24, 2014
    Applicant: NVIDIA Corporation
    Inventors: Andreas Dietrich, David K. McAllister, Heiko Friedrich, Konstantin Anatolievich Vostryakov, Steven Parker, James Lawrence Bigler, Russell Keith Morley