Abstract: A system, method, and computer program product are provided for mapping tiles to physical memory locations. In use, a plurality of virtual tiles associated with a texture is identified. Additionally, a request to perform a mapping of the plurality of virtual tiles to one or more physical memory locations is received. Further, the plurality of virtual tiles is mapped to the one or more physical memory locations, utilizing a page table.

Abstract: A method for a computer system including receiving a file comprising textures including a first and a second texture map, which can be regular or irregular texture maps, and metadata, wherein the metadata includes identifiers associated with texture maps and includes adjacency data, associating the first texture map with a first face of an object in response to an identifier associated with the first texture map, associating the second texture map with a second face of the object in response to an identifier associated with the second texture map, determining an edge of the first texture map is adjacent to an edge of the second texture map in response to the adjacency data, and performing a rendering operation with respect to the first and second faces of the object to determine rendering data in response to the first and second texture maps.

Abstract: Embodiments of the present invention are directed towards increasing texture filtering performance for texel components represented by more than 8 bits. As the number of bits per component increases, the number of texels that are processed each clock cycle decreases since more bits need to be processed to produce each filtered result. A filtered result may be accumulated over two or more iterations, with each iteration producing a portion of the filtered result. When only a portion of the components for each texel are used, the unused texel components are not processed. Elimination of unnecessary texel processing for unused texel components may improve texture filtering performance.

Abstract: A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map.

Abstract: Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.

Abstract: Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for applying textures to rendered objects by rendering the texture image itself into the storage to reduce the storage space in which the texture image is stored and to arrange portions of the texture image to be retrieved with fewer accesses. A device to render images includes a processor component; a color analyzer to determine a clear color of a texture image stored as source texture data; and a rendering routine to render the texture image into a storage as reduced texture data, the rendering routine to selectively store in the reduced texture data pixel color values retrieved from the source texture data that are associated with pixels of the texture image not colored with the clear color. Other embodiments are described and claimed.

Abstract: One embodiment of the present invention includes techniques for processing a multi-resolution hierarchy, where an application configures a ROP unit to render all the levels included in the multi-resolution hierarchy to a single composite render target. The ROP unit renders memory pages to the composite render target in pitch order. In contrast, the texture unit accesses the composite render target with memory pages in pitch order for each level of the hierarchy. The application configures the MMU to ensure that the composite render target is correctly interpreted by the texture unit. Notably, the MMU translates ROP unit virtual addresses and texture unit virtual addresses using different mapping strategies to the same physical address space. One advantage of the disclosed embodiments is that rendering to the multi-resolution hierarchy does not require the CPU to execute the state parameter changes that are associated with rendering the different hierarchical levels using prior-art techniques.

Abstract: Methods, systems, and computer-readable media for reconstruction a three-dimensional scene from a collection of two-dimensional images are provided. A computerized reconstruction system executes computer vision algorithms on the collection of two-dimensional images to identify candidate planes that are used to model visual characteristics of the environment depicted in the two-dimensional images. The computer vision algorithms may minimize an energy function that represents the relationships and similarities among features of the two-dimensional images to assign pixels of the two dimensional images to planes in the three dimensional scene. The three-dimensional scene is navigable and depicts viewpoint transitions between multiple two-dimensional images.

Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.

Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.

Abstract: Information to be sent over a network, such as the Ethernet, is packetized by using a graphics processing unit (GPU). The GPU performs packetization of data with much higher throughput than a typical central processing unit (CPU). The packetized data may be output through an Ethernet port, video port, or other port of an electronic system.

Abstract: Performing real-time atlasing of graphics data and creation and maintenance of texture atlases for applications having dynamic graphics content. Embodiments include allocating a texture atlas configured to store textural elements for use in rendering graphical elements, and providing a graphics processing unit (GPU) access to the texture atlas. During subsequent execution of an application, when a graphical element of the application is to be rendered by the GPU, a block of space can be allocated within the texture atlas and a textural element corresponding to the graphical element can be stored within the allocated block. The GPU therefore has access to the textural element when rendering the graphical element.

Abstract: A sprite capture and reproduction system for a gaming machine is disclosed. A sprite is a graphic image that can move within a larger graphic image. The system includes a sprite capture component and a sprite reproduction component. The sprite capture component enables capture of a sprite in video memory for use as another sprite. The sprite reproduction component enables reproduction of independent animated images that are combinable in a larger animation. The system does not require a discreet texture for each and every image that is loaded. Additionally, the system dramatically increases likelihood that desired images are resident and available for use in video memory, thereby saving texture memory. Further, the system minimizes shadow RAM usage.

Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.

Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.

Abstract: Circuits, methods, and apparatus that perform a context switch quickly while not wasting a significant amount of in-progress work. A texture pipeline includes a cutoff point or stage. After receipt of a context switch instruction, texture requests and state updates above the cutoff point are stored in a memory, while those below the cutoff point are processed before the context switch is completed. After this processing is complete, global states in the texture pipeline are stored in the memory. A previous context may then be restored by reading its texture requests and global states from the memory and loading them into the texture pipeline. The location of the cutoff point can be a point in the pipeline where a texture request can no longer result in a page fault in the memory.

Abstract: A method and apparatus for sorting data into spatial bins or buckets using a graphics processing unit (GPU). The method takes unsorted point data as input and scatters the points, in sorted order, into a set of bins. This key operation enables construction of a spatial data structure that is useful for applications such as particle simulation or collision detection. The disclosed method achieves better performance scaling than previous methods by exploiting geometry shaders to progressively trim the size of a working set. The method also leverages predicated rendering functionality to allow early termination without CPU/GPU synchronization. Furthermore, unlike previous techniques, the method can guarantee sorted output without requiring sorted input. This allows the method to be used to implement a form of bucket sort using the GPU.

Abstract: A system, method, and computer program product are provided for GPU demand paging. In operation, input data is addressed in terms of a virtual address space. Additionally, the input data is organized into one or more pages of data. Further, the input data organized as the one or more pages of data is at least temporarily stored in a physical cache. In addition, access to the input data in the physical cache is facilitated.

Abstract: A printer interprets the input print data and determines whether or not a rendering command targeted for reusable data included in print data depends on a placement location for placement of the rendering result in a physical coordinate space based on the interpretation result of the PDL data. When the rendering command depends on a placement location for placement of the rendering result in a physical coordinate space, the printer generates cache data without graphic processing for the rendering command targeted for reusable data and stores the generated cache data in a storage unit. When the rendering command does not depend on a placement location for placement of the rendering result in a physical coordinate space, the printer performs graphic processing for the rendering command targeted for the reusable data, generates cache data based on the result of the graphic processing, and stores the generated cache data in a storage unit.

Abstract: The graphics co-processing technique includes rendering a frame of red, green, blue (RGB) data on a graphics processing unit on an unattached adapter. The frame of RGB data are converted on the graphics processing unit on the unattached adapter to luminance-color difference (YUV) data. The YUV data is copied from frame buffers of the graphics processing unit on the unattached adapter to buffers in system memory. The YUV data is copied from the buffers in the system memory to texture buffers of a graphics processing unit on a primary adapter. A frame of RGB data is recovered from the YUV data in the texture buffer of the graphics processing unit on the primary adapter. The recovered frame of RGB data may then be presented by the graphics processing unit on the primary adapter on the primary display.

Abstract: Some techniques for providing tiles of dynamic content include a service that determines a generation time and update time in response to receiving a request for a particular tile, and that returns the particular tile. The generation time is when the particular tile of dynamic content was most recently generated based on particular vector data associated with the particular tile. The update time is when the particular vector data was most recently updated. The particular tile is generated based on the particular vector data in response to determining that the generation time is not later than the update time. Some techniques include a client that receives data that indicates an estimated time to complete generation of a tile in response to sending a first request for the tile. A second request for the tile is sent at a time based at least in part on the estimated time.

Abstract: A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and facilitates power conservation by utilizing a single unified data fetch stage (e.g., unified data fetch module) that retrieves a variety of different pixel surface attribute values (e.g., depth, color, and/or texture values) in a single stage. Different types of pixel surface attribute data (e.g., depth, color, texture) associated with multiple graphics processing functions (e.g., color blending, texture mapping, etc.) are retrieved in the single unified data fetch graphics pipeline stage. The pixel surface attribute values may be placed in corresponding variable fields of a pixel packet row. The pixel packet rows including the pixel surface attribute values are forwarded to downstream graphics pipeline stages (e.g., an arithmetic logic pipestage).

Abstract: A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and facilitates power conservation by utilizing a single unified data fetch stage (e.g., unified data fetch module) that retrieves a variety of different pixel surface attribute values for different attribute types (e.g., depth, color, and/or texture values) in a single stage. Different types of pixel surface attribute data (e.g., depth, color, texture) associated with multiple graphics processing functions (e.g., color blending, texture mapping, etc.) are retrieved in the single unified data fetch graphics pipeline stage. The pixel packet rows including the pixel surface attribute values are forwarded to other graphics pipeline stages for single thread processing (e.g. to a universal arithmetic logic unit capable of performing multiple graphics functions on the pixel surface attribute values).

Abstract: A shell texture image shared for use among multilayer shell polygons and including a plurality of areas having transparency different from one another, is distorted to varying degrees depending on a position of each layer of the shell polygons, so as to texture-map each layer of the shell polygons therewith and so as to position the multilayer shell polygons in a virtual three-dimensional space. Thus, it is possible to realistically represent hair, grass, and the like with little effort in three-dimensional image processing.

Abstract: In a graphics processing system, when a fragment reaches a texturing stage, it is determined whether the texture to be applied is a static or dynamic texture. If it is determined that the required texels relate to a dynamic texture, then the system first tries to fetch those texels from a dynamic texture memory. If it is found that the texels are not available in the dynamic texture memory, then the relevant texels are generated in an “on-demand” fashion and stored in the dynamic texture memory so that they can be applied to the fragment.

Abstract: A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.

Abstract: Arbitrary size texture palettes. A texture palette storage embodied in a computer readable medium is provided. The texture palette storage is partitioned into texture palette tables of arbitrary size. Texel data is stored for each of the texture palette tables in the texture palette storage. Another aspect is a palette memory that receives a texture index value of y-bits. The palette memory comprises subtables of different length. Each sub-table has a range with a start address and a length. The start address is a multiple of m. Each range is of a length addressable by y-bits. The palette memory also includes a sub-table index value of x-bits.

Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.

Abstract: A plurality of polygons are placed in a 3-dimensional virtual space. Each of plural types of first textures corresponding to plural types of attributes which the plurality of polygons have is mapped to the polygon that has the attribute of the type corresponding to the first texture, the 3-dimensional virtual space is shot by a first virtual camera, and thereby a main image is generated. In addition, each of the plural types of second textures corresponding to plural types of attributes which the plurality of polygons have is mapped to the polygon that has the attribute of the type corresponding to the second texture, the 3-dimensional virtual space is shot by a second virtual camera, and thereby a main image is generated.

Abstract: A texture compression engine of a graphics device receives an uncompressed texture of a 3D graphic application. The received uncompressed texture is transcoded into an AVC reference picture stream. A plurality of mipmaps is constructed from the received uncompressed texture. The texture compression engine determines a texture compression rate based on available memory capacities. The texture compression engine compresses the received texture and its mipmaps at the determined texture compression rate. The compressed texture and mipmaps are further transcoded into the AVC reference picture stream and stored. The transcoded texture and mipmaps comprise either RGB or YCbCr components for a RGB uncompressed texture. The transcoded texture and mipmaps comprise monochrome or luma components for an ARGB uncompressed texture. A graphics accelerator in the graphics device is operable to acquire the stored texture and mipmaps for a 3D graphics scene. The acquired texture and mipmaps are decompressed by AVC decoding.

Abstract: One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value that may be static or computed during execution of a shader program. Any texture operation instruction may specify an index value for each of the texture header and the texture sampler.

Abstract: When multi-frame rate contents including many high frame-rate portions are played back in a video player, a playback can be easily selected by showing to a user a playback time in respective playback modes of a normal playback and a slow playback. The video player includes a rate analysis unit for calculating playback time in the respective playback modes by analyzing a frame rate of multi-frame rate contents, and thumbnail images of multi-frame rate contents and playback time in the respective playback modes are listed and displayed as display units in a pair with respect to a plurality of contents.

Abstract: Improved techniques for texture mapping are described. In one embodiment, for example, a host may include a processor circuit and a graphics management module, and the graphics management module may be operable by the processor circuit to determine that a texture value corresponding to a texture coordinate is unavailable, determine a marginal texture coordinate corresponding to the texture coordinate, determine a marginal texture value corresponding to the marginal texture coordinate, and store the marginal texture value in a memory unit. Other embodiments are described and claimed.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: An apparatus and method of reading texture data for texture mapping. Each of a plurality of blocks included in a cache memory may have any one of an even numbered index or odd numbered index. In this instance, the cache memory may be embodied with an odd numbered index cache memory including odd numbered index blocks and an even numbered index cache memory including even numbered index blocks. Also, address indexes of requested texture data may be analyzed to appropriately access to at least one of the odd numbered index cache memory and even numbered index cache memory, thereby improving an accessing speed.

Abstract: The present invention discloses a character display method and apparatus. The method includes: obtaining a display color value of a character; obtaining a background color value of the character according to a position of the character; obtaining a difference between the display color value and the background color value; obtaining an outline of the character when the difference is smaller than a preset threshold; and displaying the character that has the outline. By adopting the present invention, the character may be clearly displayed in a background without changing a color of the character and a color of the background.

Abstract: Methods and apparatuses for scheduling and storing media creation are described. Methods and apparatuses for rendering a plurality of vector graphic objects on a display are also described.

Abstract: In a communication device with a graphics processor, a graphics asset can be shared with two or more applications. The graphics asset can include a bitmap of a digital image. An asset server can host a texture corresponding to the graphics asset and can share the texture with the graphics processor. The asset server can host multiple textures and can share those textures with the graphics processor for rendering. The graphics processor can use the shared texture to render an instance of the graphics asset for each of the two or more applications. The texture can be generated by copying information about the graphics asset into the asset server.

Abstract: A system maintains data from different resolution levels of an image in textures of a graphics processing unit (GPU). Image data is organized into multiple resolution layers of an image. Data from the lower resolution level(s) is used to process an image while higher resolution data is loaded. In one embodiment, a first resolution representation of the image having a lowest resolution level using data resident in the GPU memory is drawn prior to drawing a portion of a second resolution representation having a higher resolution level using data resident in the GPU memory.

Abstract: A method and apparatus are provided to generate automatically a mip-map chain of texture images from a portion of texture image data such that it may be used in texturing a computer graphic image. A portion of the texture image data is stored temporarily and is filtered to generate at least one lower level of mip-map data from the texture data. This lower level of mip-map texture image data is then stored for use in texturing. Preferably these are stored on a tile-by-tile basis where a tile is a rectangular area of the image being displayed.

Abstract: Embodiments provide texture compression with high compression ratios and low decompression times. Some embodiments partition a texture map into texel blocks. The number of blocks is reduced until a compression threshold is reached, and the resulting blocks are stored as a codebook. An index array is generated by associating each texel block with an index and associating each index with the block in the codebook identified as a closest match to the associated texel block. The codebook may then be compressed according to a technique compatible with a GPU. In certain embodiments, to render a scene, a CPU “inflates” the texture map by copying the appropriate codebook block to each indexed block location of the texture map, as defined by the index array. Because the codebook blocks are already compressed in a format compatible with the GPU, the inflated texture map is also compatible with the GPU without further processing.

Abstract: This disclosure describes techniques for reducing memory access bandwidth in a graphics processing system based on destination alpha values. The techniques may include retrieving a destination alpha value from a bin buffer, the destination alpha value being generated in response to processing a first pixel associated with a first primitive. The techniques may further include determining, based on the destination alpha value, whether to perform an action that causes one or more texture values for a second pixel to not be retrieved from a texture buffer. In some examples, the action may include discarding the second pixel from a pixel processing pipeline prior to the second pixel arriving at a texture mapping stage of the pixel processing pipeline. The second pixel may be associated with a second primitive different than the first primitive.

Abstract: Various technologies for a layered texture compression architecture. In one implementation, the layered texture compression architecture may include a texture consumption pipeline. The texture compression pipeline may include a processor, memory devices, and textures compressed at varying ratios of compression. The textures within the pipeline may be compressed at ratios in accordance with characteristics of the devices in the pipeline that contains and processes the textures.

Abstract: Disclosed are method and apparatus for storing information of a picture. The method includes presenting a picture file to be edited, which at least includes original picture data; editing the picture file with an interface engine; integrating rendering information of the edited picture file according to a preset picture file format; and storing the original picture data and the rendering information. According to the invention, the interface engine is improved, and thus may directly edit a picture in use, and integrate the rendering information of the edited picture file according to a preset picture format. Therefore, during development, it is not required to store rendering information of a picture into codes, so that no programmer is required to intervene in rendering and setting of the picture. An art-designer may directly operate on the interface engine to change rendering effects, meanwhile, final rendering effects may be observed without running a program.

Abstract: A graphic processing system to compute a texture level of detail. An embodiment of the graphic processing system includes a memory device, a driver, and level of detail computation logic. The memory device is configured to implement a first lookup table. The first lookup table is configured to provide a first level of detail component. The driver is configured to calculate a log value of a second level of detail component. The level of detail computation logic is coupled to the memory device and the driver. The level of detail computation logic is configured to compute a level of detail for a texture mapping operation based on the first level of detail component from the lookup table and the second level of detail component from the driver. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than multiplication, square, and square root operations.

Abstract: A handheld electronic device includes a reduced QWERTY keyboard and is enabled with disambiguation software. The device provides output in the form of a default output and a number of variants. The output is based largely upon the frequency, i.e., the likelihood that a user intended a particular output, but various features of the device provide additional variants that are not based solely on frequency and rather are provided by various logic structures resident on the device. The device enables editing during text entry and also provides a learning function that allows the disambiguation function to adapt to provide a customized experience for the user. Additionally, the device can facilitate the selection of variants by displaying a graphic of a special <NEXT> key of the keypad that enables a user to progressively select variants generally without changing the position of the user's hands on the device.

Abstract: A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.

Abstract: A multithreaded rendering software pipeline architecture utilizes a rolling texture context data structure to store multiple texture contexts that are associated with different textures that are being processed in the software pipeline. Each texture context stores state data for a particular texture, and facilitates the access to texture data by multiple, parallel stages in a software pipeline. In addition, texture contexts are capable of being “rolled”, or copied to enable different stages of a rendering pipeline that require different state data for a particular texture to separately access the texture data independently from one another, and without the necessity for stalling the pipeline to ensure synchronization of shared texture data among the stages of the pipeline.

Abstract: Functionality for storing and modifying multi-resolution texture atlases is provided so that applications can expose methods to enable users to access and browse a collection that includes multiple multi-resolution images. The images are stored as thumbnails in a texture atlas having different levels of detail in which the levels are arranged in an image pyramid that includes multiple tiles that are each stored as separate files. The thumbnails are spatially storable as textures in the texture atlas using a fractal layout (which in one illustrative example is a Morton layout) that enables images to be efficiently packed in the tiles. The fractal layout ensures that no more than one tile stores less than a fully packed texture at each level of detail. The same packing order scales across each level of detail in the texture atlas so that layout information is stored for the individual images in the collection only once.

Abstract: Systems and methods for utilizing intermediate target(s) in connection with computer graphics in a computer system allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips.