Abstract: Provided are methods for managing texture data in Graphics Processing Units (GPUs). The methods include receiving, into an arbiter, a preload request configured to request processing of texture data in advance of shader processing and receiving, into the arbiter, a dependent read request configured to request processing of texture data after shader processing. The methods also include receiving, into the arbiter, a capacity signal from a texture buffer and determining, utilizing the virtual buffer capacity signal, a selected request corresponding which of the preload request and the dependent read request is granted. The methods further include processing, in a texture processor, texture data corresponding to the selected request.

Abstract: Provided is a system for managing multiple contexts in a decentralized graphics processing unit. The system includes multiple control units that can include a context buffer, a context processor, and a context scheduler. Also included is logic to receive multiple contexts, logic to identify at least one of the contexts, and logic to facilitate communication among the control units.

Abstract: A “Vector Graphics Encoder” encodes vector graphics in a randomly accessible format. This encoding format enables particular portions of encoded images to be directly accessed, at any desired level of zoom, without processing or otherwise decoding the entire image. This random-access format is based on a coarse image grid of partially overlapping cells wherein each cell is defined by a “texel program.” Unlike fixed-complexity cells used by conventional vector images, each cell defined by a texel program is locally specialized without requiring global constraints on the complexity of each cell. The texel program for each cell is provided as a variable-length string of tokens representing a locally specialized description of one or more of layers of graphics primitives overlapping the cell. Images are then rendered by interpreting the texel programs defining one or more cells.

Abstract: A texturing system for use in a three-dimensional graphics system has an input for receiving object data for an object to be textured. Encrypted texture data is obtained from a store and decrypted in a decryption unit. The decrypted texture data generates texture image data for a frame buffer from which the texture image data can be outputted for display. A method for producing a software application for using in a three-dimensional graphics system which creates instructions for a software application and static texture data for using in conjunction with the instructions is also provided. The static texture data is encrypted and provided as encrypted texture data with the software instructions.

Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.

Abstract: The current invention involves new systems and methods for increasing texture filtering performance by reorganizing a texture sampling order used to read and filter texels when anisotropic filtering is used. Texel read performance is improved for anisotropic filtering by reorganizing texel reads when a texel cache is used. The texel reads are paired based on a major axis alignment in pixel space. The paired texel reads for a pixel footprint may also be ordered to improve texel coherency, thereby improving a texture cache hit rate.

Abstract: A system for displaying a digital video sequence includes a graphics processing unit (GPU) and a display device. The GPU receives and modifies the digital video sequence to compensate for perceived blur based on motion between frames of the digital video sequence. The display device displays the modified digital video sequence. A method and computer readable medium having computer readable code is also provided.

Abstract: Methods, systems and apparatus, including computer program products, for processing a computer graphics illustration having pieces of artwork.

Abstract: A system, method and computer program product are provided for retrieving instructions from memory utilizing a texture module in a graphics pipeline. During use, an instruction request is sent to memory utilizing a texture module in a graphics pipeline. In response thereto, instructions are received from the memory in response to the instruction request utilizing the texture module in the graphics pipeline.

Abstract: Embodiments of the present invention provide a seamless way to emulate legacy graphics processing on modern graphics hardware. In particular, in some embodiments, the present invention provides a way for modern GPUs to emulate the bitwise operations and rendering processes of previous generations of graphics hardware. The present invention utilizes a novel pixel shader program. The pixel shader program provides a texture lookup functionality that compensates for any missing bitwise functionality. When a bitwise operation is requested, the system will copy out the destination area to a temporary image. This temporary image is fed to the pixel shader program along with a precomputed texture. The texture is precomputed by the CPU for the various bitwise operations and acts as a lookup table for the requested operation. With the temporary image and precomputed texture, the shader program on the GPU can then emulate the legacy graphics operations seamlessly.

Abstract: A cache control unit of a video data playback control apparatus sets priority video data in order to efficiently use a storage area of a cache memory. The priority video data includes video data which includes a greater number of portions of video data than that of data displayed in a display unit, which includes a smaller number of portions of video data than a maximum number that can be held in the cache memory, and which has a high possibility of being output from the cache memory to the display unit. Also, the cache control unit preferentially reads the priority video data from a recording medium and stores it in the cache memory.

Abstract: The present invention is a unified shader unit used in texture processing in graphics processing device. Unlike the conventional method of using one shader for texture coordinate shading and another for color shading, the present shader performs both operations. The unified shader uses the same precision for both texture coordinate and color shading, thus simplifying the complexity of programming for two separate conventional shaders with different levels of precision. Furthermore, the present invention uses enhanced scheduling logic to perform indirect texture and bump mapping in a single first-in, first-out (FIFO) memory structure and avoids the problems associated with large FIFOs with buffer registers found in conventional shaders. In one embodiment, a plurality of ALU-memory pairs are synchronized to form a plurality of pipelines to execution shading instructions. In another embodiment, a plurality of unified shaders are synchronized and connected together to processing shading operations concurrently.

Abstract: A graphics processing system including a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data according to a respective address. The cache memory includes first and second memories coupled together by a plurality of activation lines. The first memory has a corresponding plurality of address detection units to store addresses and provide activation signals in response to receiving a matching address. The second memory includes a corresponding plurality of data storage locations. Each data storage location is coupled to a respective one of the plurality of address storage locations by a respective activation line to provide graphics data in response to receiving an activation signal from the respective address storage location.

Abstract: Disclosed is as system for reducing memory and computational requirements of graphics operations. The system provides techniques for combining otherwise individual operations to apply filters to images. The combined filter emerging from the combination spares the processor time and the creation of an entire intermediary image. The system further provides for application of these techniques in many contexts including where the operations are fragment programs in for a programmable GPU.

Abstract: Systems and methods for performing data array resizing using a graphics processor resize a source data array of any dimensions to produce a destination data array of other dimensions. A pixel shader program may be used to configure the graphics processor to sample and filter the source data array to produce the destination data array. One or more destination data arrays may be mip maps of the source data array. A box filter or other type of filter may be used to produce each destination data array. Each pixel in the destination data array is produced in isolation, i.e., independently, thereby permitting the use of parallel processing to produce each pixel in the destination data array.

Abstract: One embodiment of the invention sets forth a method for storing graphics data in a texture array in a local memory coupled to a graphics processing unit. The method includes the steps of specifying the texture array as a target in the local memory, and loading a first block of texture maps into the texture array, wherein each texture map in the first block has a first resolution and corresponds to a different slice of the texture array. One advantage of the disclosed method is that a complete block of texture images may be loaded into a texture array using a single API call. Thus, compared to prior art systems, where a texture array must be loaded one image for one slice of the array at a time, the disclosed method increases the efficiency of using arrays of texture maps for graphics processing operations.

Abstract: A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file, and a vector functional unit that perform partitioned instructions. In addition, an enhanced rasterization unit is used to generate inverse-mapped source coordinates in addition to destination output coordinates for graphics and other media processing. An enhanced texture address unit generates corresponding memory addresses of source texture data for graphics processing and source media data for media processing. Data retrieved from memory are stored in an enhanced texture cache for use by the vector functional unit. A vector output unit includes a blending unit for graphics data and an output buffer for wide media data.

Abstract: Disclosed herein is an image processing apparatus, including: first storage means for storing data in a unit of a word; second storage means for storing data in a unit of a word, address information for managing writing and reading out of the data of a unit of a word and a correction flag which indicates, in a unit of a word, whether or not it is necessary to correct the data, in an associated relationship with each other; and supplying means for reading out and supplying the data of a unit of a word, corresponding address information and a corresponding correction flag stored in the second storage means to the first storage means; the first storage means referring to the address information to correct the data of a unit of a word corresponding to the correction flag to the data of a unit of a word.

Abstract: Systems and methods are provided for variable source rate sampling in connection with image rendering, which accumulate and resolve over all samples forward mapped to each pixel bin. In accordance with the invention, the textured surface to be rendered is sampled, or oversampled, at a variable rate that reflects variations in frequency among different regions, taking into account any transformation that will be applied to the surface prior to rendering and the view parameters of the display device, thus ensuring that each bin of the rendering process receives at least a predetermined minimum number of samples. In one embodiment, the sampling rate is variably set such that each bin is assured to have at least one sample point. In another embodiment, a tiling approach to division of the surface is utilized.

Abstract: An embodiment generally relates a device for rotating images. The device includes an image memory configured to store an image and a plurality of buffers. The plurality of buffers are configured to interface with the image memory to read data words of the image from the image memory and to write rotated data words to the image memory. The device also includes a logic module configured to interface with the plurality of buffers and to micro-rotate and macro-rotate an image based on a selection of three orientations. The logic module is also configured to execute a read of data words from the image memory to a first buffer of the plurality of buffers, a rotation of a data word, and a write of rotated data words from a second buffer of the plurality of buffers to the image memory substantially simultaneously.

Abstract: A new transparency group may be rendered and blended with other, previously rendered, transparency groups, by using the Porter-Duff algebra available on the GPU even though the transparency groups include pre-multiplied color and alpha information. Additionally, the number of copies of the back buffer (the image information for the previously rendered transparency groups) required to properly render, blend and combine the new transparency group into the image information of previously rendered transparency groups may be minimized.

Abstract: A virtually-addressed local texture memory stores selected regions (a sparse representation) of a texture for use by a graphics processor. The graphics processor requests a texel of the texture by referencing a virtual address of the texel. A memory interface references an address map to determine whether the requested texel is in one of the regions of the texture that is resident in the local texture memory. If so, the texel is retrieved from the local memory and used in the rendering operation; if not, an alternative texel that is resident in the local memory is retrieved and used in the rendering operation. Non-resident regions that include requested texels are retrieved from a primary texture data store at regular intervals (e.g., once per frame) and stored in local texture memory for use in a subsequent rendering operation.

Abstract: An apparatus and method of reading texture data for texture mapping. Each of a plurality of blocks included in a cache memory may have any one of an even numbered index or odd numbered index. In this instance, the cache memory may be embodied with an odd numbered index cache memory including odd numbered index blocks and an even numbered index cache memory including even numbered index blocks. Also, address indexes of requested texture data may be analyzed to appropriately access to at least one of the odd numbered index cache memory and even numbered index cache memory, thereby improving an accessing speed.

Abstract: A computer system in which a graphics accelerator unit manages page faulting of texture data invisibly to the host processor.

Abstract: A method and system for accessing texture data is disclosed. The method includes the step of storing a low resolution version of a block of texture data in a low latency memory and storing a high resolution version of the block of texture data in high latency memory. Upon a request for the high resolution version of the block of texture data, the high resolution version is fetched from the high latency memory to the low latency memory. The low resolution version is subsequently accessed from the low latency memory until the high resolution version is fetched into the low latency memory.

Abstract: An object collation method comprising a registration procedure for registering the registered data of a registered object in a database, and a collation procedure for collating the input image of a target object with the registered data. The registration procedure includes a step of storing the three-dimensional shape of the registered object and a texture space defined by a texture group indicating the luminance and/or color information of each position of the object surface under various illumination conditions. The collation procedure includes the steps of: generating an illumination fluctuation space defined by the image group under the various illumination conditions, at the location and position of the target object in the input image from the three-dimensional shape and the texture space; and collating the target object and the registered object based on the distance between the illumination fluctuation space and the input image.

Abstract: Circuits, methods, and apparatus provide for the storage of texture descriptors in a graphics memory. Since the texture descriptors are stored in a graphics memory, they do not need to be stored in the graphics processor itself, thus reducing graphics processor circuitry and cost. This allows more textures to be associated with each graphics primitive, thereby improving image realism.

Abstract: Circuits, methods, and apparatus provide for the storage of texture descriptors in a graphics memory. Since the texture descriptors are stored in a graphics memory, they do not need to be stored in the graphics processor itself, thus reducing graphics processor circuitry and cost. This allows more textures to be associated with each graphics primitive, thereby improving image realism.

Abstract: A system, method and apparatus to provide flexible texture filtering. A programmable texture filtering module is introduced into the graphics processing pipeline of a graphic coprocessor and graphic processor integrated with the host. A program from a defined instruction set may then be loaded into texture processing cores to process texture data consistent with the program.

Abstract: A memory controller having graphic processing function that includes a graphic processing unit operating in response to a selection signal from a master, and a memory interface for storing outputs of the graphic processing unit in an external memory at and receiving graphic data from the external memory to provide the graphic data to the graphic processing unit.

Abstract: A method of interdigitation for display of an autostereoscopic source image to a screen comprising a plurality of pixels having sub-pixels and sub-pixel components and apparatus for interdigitation is provided. The method comprises generating a texture memory coordinate at each pixel location on the screen of the source image, calculating screen pixel location based on the texture memory coordinate of each pixel, computing view numbers based on screen pixel location, wherein view numbers comprise one value for each sub-pixel component, mapping proportional pixel locations in tiles from multiple tile perspective views of the autostereoscopic image to a resultant image using the view numbers, and extracting one subpixel component from each proportional pixel location to represent color for the pixel in the resultant image.

Abstract: Methods for texture image management are provided. An embodiment of a method for texture image management comprises the following steps. A texture image is acquired from a non-writable memory device. The received texture image is directly applied to a fragment.

Abstract: Systems and methods are provided for progressive mesh storage and reconstruction using wavelet-encoded height fields. A method for progressive mesh storage includes reading raster height field data, and processing the raster height field data with a discrete wavelet transform to generate wavelet-encoded height fields. In another embodiment, a method for progressive mesh storage includes reading texture map data, and processing the texture map data with a discrete wavelet transform to generate wavelet-encoded texture map fields. A method for reconstructing a progressive mesh from wavelet-encoded height field data includes determining terrain blocks, and a level of detail required for each terrain block, based upon a viewpoint. Triangle strip constructs are generated from vertices of the terrain blocks, and an image is rendered utilizing the triangle strip constructs. Software products that implement these methods are provided.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Abstract: Methods and systems for texture mapping in a computer-implemented graphics pipeline are described. A sample group is identified as including a divergent pixel. A determination is made whether an operand of an instruction executing on the divergent pixel satisfies a condition. A scheme for determining a level of detail for the texture mapping is selected depending on whether or not the condition is satisfied.

Abstract: A method and system for rendering three-dimensional graphics, including text, provide a compressed texture bitmap. The texture bitmap may represent multiple symbols, each comprised of multiple pixels. Each pixel in the texture bitmap may store information for more than one symbol, including compressed pixels corresponding to multiple distinct symbols. For example, the compressed texture bitmap may have n-bit pixels (e.g., 8-bit pixels) that each store m (e.g., four) n/m-bit (e.g., 2-bit) compressed values. The compressed texture bitmap may be configured for unpacking by a conventional pixel shader, such as a pixel shader that does not typically perform bitwise operations. The unpacking may include matching a fetched pixel to a value in a lookup table, such as a 32-bit value from a 256-color palette. The looked-up value can be separated into separate sub-values to facilitate processing by the pixel shader.

Abstract: Texture mapping (TM) apparatus includes unit acquiring texture data items (TD) and model data items (MD), unit generating control data used for TM according to TD and MD, unit generating control instructions (CIs) for TM processes corresponding to control data, unit selecting at least one model data item (ALMD) and TD from TD and MD, based on first CI, unit determining arrangement of selected ALMD and TD, unit storing selected ALMD and TD based on determined arrangement, unit selecting, from stored MD and TD, MD and TD used for rendering, based on second CI, unit correcting MD selected for rendering and TD selected for rendering, using first measure designated by third CI, unit performing interpolation on corrected MD and TD, using second measure designated by fourth CI, unit mapping interpolated TD onto interpolated MD, using third measure designated by fifth CI, and unit outputting data as computer graphics data.

Abstract: Various technologies for a layered texture compression architecture. In one implementation, the layered texture compression architecture may include a texture consumption pipeline. The texture compression pipeline may include a processor, memory devices, and textures compressed at varying ratios of compression. The textures within the pipeline may be compressed at ratios in accordance with characteristics of the devices in the pipeline that contains and processes the textures.

Abstract: A pixel is textured by storing a first texel reference value, a second texel reference value, and texel mapping values where each texel mapping value represents a k-tuple of (ternary) references to the first texel reference value, the second texel reference value and a third texel reference value to thereby represent a block of texels. A pixel value for the pixel is generated from the stored texel values and the pixel is displayed responsive to the generated pixel value. In some embodiments, respective pluralities of texel reference values and texel mapping values that map thereto are stored for respective ones of a plurality of overlapping blocks of texels. In further embodiments, a first mipmap value for a pixel is bilinearly interpolated from the retrieved texel values for the set of nearest neighbor texels. A second mipmap value for the pixel is generated by averaging the retrieved texel values for the set of nearest neighbor texels.

Abstract: A transform engine within a graphics pipeline is configured to rotate, or rotate and translate, one or more polygons in response to a screen orientation. The transform engine obtains a texture from a pre-rotated polygon and applies the texture to the rotated polygon. An image that reflects the rotated or rotated and translated polygon is then rendered in response to the screen orientation.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip uses window descriptors to describe logical surfaces, or windows, of graphics information to be displayed on the screen. The chip incorporates a unified memory architecture that provides a high level of system performance while conserving memory bandwidth and chip size. Video and graphics scaling capabilities as well as anti-flutter filtering capability are provided.

Abstract: A multi-resolution texture mapping system suitable for large scale terrain rendering using commodity graphics processing units (GPU). The GPU vertex and fragment shaders are used to implement the clip-mapping functionality. The terrain texture is represented by a combination of a mip-map and a multi-level clip-map having independent origins and off-set values. The independent clip-map levels may be independently updated. The offset values allow the origins to be associated with a reference point in a scene to be rendered. The desired clip-map level to be used to render a particular fragment may be determined using the base 2 logarithm of the maximum screen-space derivative of the source texture required by the terrain geometry to be drawn. If the desired clip-map level is non-integer and lies between two clip-map levels, appropriate texel data is created by interpolating between the bounding clip-map levels. This interpolation allows a multi-resolution texture mapping to be displayed.

Abstract: A video streaming data processing method is used in a video streaming data processing system including a central processing unit, a system memory, a graphic processing unit and a video random-access memory. After video streaming data are received, a video decoding operation is performed on the video streaming data by the central processing unit to produce image data and the image data are then stored into the system memory. Next, the image data are stored from the system memory to a texture buffer of the video random-access memory. Next, the image data that are stored in the texture buffer are read out and subject to a specific image processing algorithm by the graphic processing unit, and then stored back to the texture buffer. Afterwards, the image data are stored from the texture buffer to a video buffer of the video random-access memory.

Abstract: Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected for each virtual memory page to modify the number of sequential addresses mapped to each physical memory partition and change the interleaving granularity. The addressing scheme allows for modification of a bank interleave pattern for each virtual memory page to reduce bank conflicts and improve memory bandwidth utilization. The addressing scheme also allows for modification of a partition interleave pattern for each virtual memory page to distribute accesses amongst multiple partitions and improve memory bandwidth utilization.

Abstract: A system and method for a mosaic rendering of a 3D model is provided. Textures are created using polygon information related to a vertex of each face of an inputted 3D model, a normal, and a face index, and the textures are one-to-one mapped on respective polygons of the 3D model, using a geometrical structure of the 3D mode, thereby rendering a mosaic image showing a volume and a crinkled effect of paper.

Abstract: Circuits, methods, and apparatus that provide for partial texture load instructions. Instead of one instruction that may take several shader passes to complete, several instructions are issued, where each instruction is an instruction to retrieve a part or portion of a texture. While each instruction is performed, the other shader circuits can perform other instructions, thus increasing the utilization of the shader circuits when large textures are read from memory. Since several shader passes may be required to read a texture, if a particular instruction needs the texture, one exemplary embodiment reorders instructions such that other instructions are performed before the particular instruction that needs the texture.

Abstract: A transform engine is configured to rotate, and/or rotate and translate, one or more polygons in response to screen orientation. Thus, when texture data obtained from a pre-rotated image is applied to a rotated polygon from an image, a rotated version of the image is generated in response to screen orientation. Alternatively, a user may select a rotation to re-orient the image to a screen view position. The rotated image may also be shifted to maintain conformance with edge rules.

Abstract: A method and system for performing texture mapping across adjacent texture maps. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of determining whether a texel crosses a boundary of a first texture map, examining a first texture state identifier associated with the first texture map, and requesting for a second texture state identifier associated with a second texture map that is adjacent to the first texture map to enable traversal to the second texture map to access the texel if the first texture state identifier includes a mode indicative of wrapping to an adjacent texture map and texture adjacency information that points to a second texture map.

Abstract: One embodiment of the present invention relates to a system for reconstructing an image. During operation, the system receives an original image, wherein the original image includes a defective area to be reconstructed. The system also receives a reference to a texture image, which contains a texture to be used during the reconstruction. The system then divides the values of pixels in the defective area and surrounding boundary pixels, by the values of corresponding pixels in the texture image to produce a first intermediate image. Next, the system solves a partial differential equation (PDE) for non-boundary pixels in the first intermediate image subject to values of the boundary pixels in the first intermediate image to produce a second intermediate image. The system then multiplies the values of pixels in the second intermediate image by the values of corresponding pixels in the texture image to produce a replacement image.

Abstract: Embodiments of systems and methods for managing a constant buffer with rendering context specific data in multithreaded parallel computational GPU core are disclosed. Briefly described, one method embodiment, among others, comprises responsive to a first shader operation, receiving at a constant buffer a first group of constants corresponding to a first rendering context, and responsive to a second shader operation, receiving at the constant buffer a second group of constants corresponding to a second context without flushing the first group.