Cache Patents (Class 345/557)
  • Patent number: 11257278
    Abstract: Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: February 22, 2022
    Assignee: Apple Inc.
    Inventors: Anthony P. DeLaurier, Michael J. Swift, Michal Valient, Robert S. Hartog, Tyson J. Bergland, Gokhan Avkarogullari
  • Patent number: 11219827
    Abstract: A gaming key mode adjusting method and an electronic device are provided. The gaming key mode adjusting method includes: retrieving a display image; determining that the display image corresponds to a gaming scenario; obtain a key mode corresponding to the gaming scenario and process a keyboard input signal according to the key mode. In the key mode, key travels correspond to a plurality of key press values.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: January 11, 2022
    Assignee: Acer Incorporated
    Inventors: Chien-Wei Chiu, Ling-Fan Tsao
  • Patent number: 11175949
    Abstract: A mechanism is described to facilitate microcontroller-based flexible thread scheduling launching in computing environments. An apparatus of embodiments, as described herein, includes facilitating a graphics processor hosting a microcontroller having a thread scheduling unit, and detection and observation logic to detect a scheduling algorithm associated with an application at the apparatus. The apparatus may further include reading and dispatching logic to facilitate the microcontroller to prepare a flexible dispatch routine based on the scheduling algorithm. The apparatus may further include scheduling and launching logic to facilitate the thread scheduling unit to dynamically schedule and launch threads based on the flexible dispatch routine, where the threads are hosted by the graphics processor.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: November 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Kiran C. Veernapu, Kamlesh Pillai, James Valerio, Joydeep Ray, Abhishek Appu
  • Patent number: 11127196
    Abstract: A cache for use in a tile-based rendering graphics processing system for storing transformed primitive blocks, the graphics processing system having a rendering space sub-divided into a plurality of tiles to which primitives can be associated, the graphics processing system comprising rasterization logic that rasterizes primitives on a per tile basis in a plurality of stages, the cache comprising: memory configured to store a plurality of transformed primitive blocks in the cache, each transformed primitive block comprising transformed geometry data for one or more primitives; control logic configured to: maintain a counter for each of the plurality of transformed primitive blocks stored in the cache that indicates a number of tiles of the plurality of tiles that are currently being processed by the rasterization logic and require access to that transformed primitive block, the counter being updated when any stage of the rasterization logic indicates a tile no longer requires access to the transformed primiti
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: September 21, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Robert Brigg, John W Howson, Xile Yang
  • Patent number: 11087433
    Abstract: A convolutional neural network (CNN) for an image processing system comprises an image cache responsive to a request to read a block of N×M pixels extending from a specified location within an input map to provide a block of N×M pixels at an output port. A convolution engine reads blocks of pixels from the output port, combines blocks of pixels with a corresponding set of weights to provide a product, and subjects the product to an activation function to provide an output pixel value. The image cache comprises a plurality of interleaved memories capable of simultaneously providing the N×M pixels at the output port in a single clock cycle. A controller provides a set of weights to the convolution engine before processing an input map, causes the convolution engine to scan across the input map by incrementing a specified location for successive blocks of pixels and generates an output map within the image cache by writing output pixel values to successive locations within the image cache.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: August 10, 2021
    Assignee: FotoNation Limited
    Inventors: Mihai Constantin Munteanu, Alexandru Caliman, Corneliu Zaharia, Dragos Dinu
  • Patent number: 11089081
    Abstract: A system, method, and computer readable storage medium for inter-process rendering pipeline for shared process remote web content rendering. The method includes obtaining an image rendering request through an inter-process communication channel established by an application in which the image rendering request including a content area. The method further includes selecting a content rendering engine based on one or more image resources needed to generate web content as specified in the image rendering request, determining the one or more image resources corresponding to the image rendering request by using the content rendering engine, and generating the web content on the content area based at least in part on the one or more image resources.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 10, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Jari Karppanen
  • Patent number: 11069175
    Abstract: Disclosed are various embodiments for determining a wagering game to play on a client device. The client device can determine the orientation of a display using one or more sensors. The wagering game can be selected using the orientation. The selected wagering game can be rendered on the display. An outcome of the wagering game can be generated.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 20, 2021
    Assignee: IGT
    Inventor: Dwayne Nelson
  • Patent number: 11048555
    Abstract: According to one example embodiment of the present disclosure, there is provided a method for optimization in a distributed system, where the distributed system comprises a client and multiple hosts among which a host comprises a computing node. The method comprises: receiving a first command requesting to use the computing node from an application at the client; determining the type of the first command; and adjusting the first command on the basis of the type of the first command to optimize the execution of the first command in the distributed system, where the computing node is a graphics processing unit, and the first command is a remote procedure call of the graphics processing unit.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: June 29, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Wei Cui, Kun Wang
  • Patent number: 11016900
    Abstract: Technology for selectively prefetching data, such that less data is prefetched when it is determined that the requested data is located in logical addresses allocated to a symbol table data structure. In some embodiments, data is still prefetched when the request is directed to the symbol table, but the amount of data prefetched (measured in memory lines, bytes or other unit) is decreased relative to what it otherwise would be in the context of a non-symbol-table request. In other embodiments, prefetching is simply not performed at all when the request is directed to the symbol table.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mohit Karve, Edmund Joseph Gieske
  • Patent number: 11010954
    Abstract: A computer-implemented redundant-coverage discard method and apparatus for reducing pixel shader work in a tile-based graphics rendering pipeline is disclosed. A coverage block information (CBI) FIFO buffer is disposed within an early coverage discard (ECD) logic section. The FIFO buffer receives and buffers coverage blocks in FIFO order. At least one coverage block that matches the block position within the TCPM is updated. The TCPM stores per-pixel primitive coverage information. The FIFO buffer buffers a moving window of the coverage blocks. Incoming primitive information associated with the coverage blocks is compared with the per-pixel primitive coverage information stored in the tile coverage-primitive map (TCPM) table at the corresponding positions for the live coverages only. Any preceding overlapping coverage within the moving window of the coverage blocks is rejected. An alternate embodiment uses a doubly linked-list rather than a FIFO buffer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: May 18, 2021
    Inventors: Nilanjan Goswami, Derek Lentz, Adithya Hrudhayan Krishnamurthy, David C. Tannenbaum
  • Patent number: 10963986
    Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive one or more frames for a workload, determine one or more compute resource parameters for the workload, and store the one or more compute resource parameters for the workload in a memory in association with workload context data for the workload. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: March 30, 2021
    Assignee: INTEL CORPORATION
    Inventors: Balaji Vembu, Josh B. Mastronarde, Altug Koker, Nikos Kaburlasos, Abhishek R. Appu, Joydeep Ray
  • Patent number: 10929304
    Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 23, 2021
    Assignee: Intel Corporation
    Inventors: Jayanth N. Rao, Murali Sundaresan
  • Patent number: 10896528
    Abstract: Implementations of the present application describe updating tile maps in virtual maps, including the following. A central area in which a virtual object is located is determined in a first area. The first area comprises an area of a map that includes tile maps loaded into a virtual map including the virtual object. A border of the central area is located in the first area. A distance parameter is determined after the virtual object moves out of the central area. The distance parameter indicates relative distances of a tile map containing the virtual object relative to the central area in x-axis and y-axis directions. A loading status of a tile map not shared by the first area and a second area is updated based on the distance parameter. The second area comprises a map area determined after moving the first area based on the distance parameter.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: January 19, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Huan Liu, Rongyan Zheng
  • Patent number: 10866907
    Abstract: A method comprising, in an image processing operation, identifying location data indicative of a read path for the image processing operation, the read path at least partly traversing a block of pixels of an image. Parameter data relating to a characteristic of the read path in the context of the block is generated from the location. Storage prioritization data is associated with the block at least partly on the basis of the parameter data. The storage prioritization data is for determining whether block data representative of the block is to be evicted from storage.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: December 15, 2020
    Assignee: Apical Ltd.
    Inventors: Metin Gokhan Ünal, Kushan Vijaykumar Vyas, Robert Shorter, Mario Jose David Manzano
  • Patent number: 10825129
    Abstract: One disclosed embodiment is directed to graphics processing method for displaying a user interface. The method includes executing a plurality of graphic processing operation in a single rendering pass. The rendering pass includes several render targets. At least one of the render targets is designated as a memory-less render target. The memory-less render target is used to store intermediate data. The intermediate data is combined with the outcome of at least one other graphics processing operation to generate a combined result. The combined result is stored in the frame buffer memory for display.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: November 3, 2020
    Assignee: Apple Inc.
    Inventors: Bartosz Ciechanowski, Michael Imbrogno, Gokhan Avkarogullari, Nathaniel C. Begeman, Sean M. Gies, Michael J. Swift
  • Patent number: 10692111
    Abstract: A computer-based method for asynchronously requesting content items to a user computing device is described. The method is implemented using a user computing device in communication with a memory. The method includes receiving a content management response, generating a plurality of content request messages for requesting at least one content item from a plurality of content providers based on the plurality of links, asynchronously transmitting a first content request message to a first content provider and a second content request message to a second content provider where the first and second content request messages are transmitted based on the at least one transmission rule, receiving a content response message including a content item from at least one of the first and the second content provider, determining the content item to display on the user computing device, and displaying the determined online content item on the user computing device.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: June 23, 2020
    Assignee: Google LLC
    Inventor: Alex Kwan Yeung Chik
  • Patent number: 10628975
    Abstract: Implementations of the present application describe updating tile maps in virtual maps, including the following. A central area in which a virtual object is located is determined in a first area. The first area comprises an area of a map that includes tile maps loaded into a virtual map including the virtual object. A border of the central area is located in the first area. A distance parameter is determined after the virtual object moves out of the central area. The distance parameter indicates relative distances of a tile map containing the virtual object relative to the central area in x-axis and y-axis directions. A loading status of a tile map not shared by the first area and a second area is updated based on the distance parameter. The second area comprises a map area determined after moving the first area based on the distance parameter.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: April 21, 2020
    Assignee: Alibaba Group Holding Limited
    Inventors: Huan Liu, Rongyan Zheng
  • Patent number: 10523956
    Abstract: Systems and methods are provided for encoding a multi-pixel caching scheme for lossless encoders. The systems and methods can include obtaining a sequence of pixels, determining repeating sub-sequences of the sequence of pixels consisting of a single repeated pixel and non-repeating sub-sequences of the sequence of pixels, responsive to the determination, encoding the repeating sub-sequences using a run-length of the repeated pixel and encoding the non-repeating sub-sequences using a multi-pixel cache, wherein the encoding using a multi-pixel cache comprises, encoding non-repeating sub-sequences stored in the multi-pixel cache as the location of the non-repeating sub-sequences in the multi-pixel cache, and encoding non-repeating sub-sequences not stored in the multi-pixel cache using the value of the pixels in the non-repeating sub-sequences.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: December 31, 2019
    Assignee: CITRIX SYSTEMS, INC.
    Inventor: Muhammad Dawood
  • Patent number: 10373029
    Abstract: A data processing method processes data using a processor including N (N is an integer equal to or more than 2) cores and a memory. The data processing method includes: searching a new character as a character whose raster data is not stored in the memory among a plurality of characters specified by character data included in print data to count a count of the searched new characters; generating M (M is an integer equal to or less than the N) threads, wherein the M is a count determined based on the count of the counted new characters among the N; dividing and allocating the plurality of characters to the M threads to generate raster data for the new characters using any one of the N cores for each of the M threads; and rendering the plurality of characters using raster data corresponding to the character data.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 6, 2019
    Assignee: Kyocera Document Solutions Inc.
    Inventor: Hideo Nakahara
  • Patent number: 10319068
    Abstract: One disclosed embodiment includes memory allocation methods for use by a graphics processing unit in rendering graphics data for display. The method includes receiving a buffer attachment associated with a first rendering pass. The hardware prerequisites for operation of the first rendering pass is determined. The method also includes receiving an indication to not allocate system memory for the received buffer attachment. Thereafter, it may be determined whether the received buffer attachment will be loaded from or stored to by the subsequent rendering passes. If it is determined that the buffer attachment will be accessed by the subsequent rendering passes, an error message may be generated indicating that system memory must be allocated. If it is determined that the buffer attachment will not be accessed by the subsequent rendering passes, the buffer attachment is rendered without allocating system memory.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: June 11, 2019
    Assignee: Apple Inc.
    Inventors: Michael J. Swift, Michael Imbrogno, Gokhan Avkarogullari
  • Patent number: 10310761
    Abstract: A storage device includes a memory unit, an access monitor, and a memory configurator. The memory unit includes a plurality of memory blocks. The access monitor is configured to monitor whether an access mode of the memory unit is a continuous-access mode or a random-access mode, to generate a monitor signal. The memory configurator configures, according to the monitor signal, any of the memory blocks to be either in a cache mode or a SRAM state to generate a configuration signal.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: June 4, 2019
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Zongpu Qi, Di Hu, Wei Zhao, Zheng Wang, Xiaoyang Li
  • Patent number: 10310973
    Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: June 4, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Nick Barrow-Williams, Brian Fahs, Jerome F. Duluk, Jr., James Leroy Deming, Timothy John Purcell, Lucien Dunning, Mark Hairgrove
  • Patent number: 10304169
    Abstract: Provided is a method and device for correction restoration and analysis alarming of a distorted image. The method includes that: an original distorted image acquired by a distortion lens is received, and original distorted coordinates of each coordinate point in the original distorted image are acquired; and pre-stored distortion parameters of the distortion lens are acquired, and restored coordinates of each coordinate point in the original distorted image are determined to obtain a restored image.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: May 28, 2019
    Assignee: ZTE CORPORATION
    Inventor: Bin Chen
  • Patent number: 10297003
    Abstract: This disclosure describes techniques for context switching. In one example, a graphics processing unit may be configured to generate one or more signatures for context information stored in on-chip memory of the graphics processing unit, determine whether the one or more signatures match any previously generated signatures for context information stored in one or more memories accessible by the graphics processing unit, store, to at least one of the one or more memories, any signature of the one or more signatures that is determined not to match any previously generated signature stored in at least one of the one or more memories, and store, to at least one of the one or more memories, the context information respectively corresponding to the one or more signatures determined not to match any previously generated signature stored in at least one of the one or more memories.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: May 21, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Anirudh Rajendra Acharya
  • Patent number: 10216389
    Abstract: Embodiments of the present invention are directed at providing a mirror snapping system for selecting candidate snap points as endpoints for path segments with symmetry in a created image. In one embodiment, generating candidate snap locations from a newly created path segment can be accomplished by automatically constructing an axis of symmetry for the newly created path segment and reflecting created path segment endpoints in the design across the axis of symmetry. In a further embodiment, upon selection of a candidate snap location as the anchored endpoint for an unanchored endpoint of a path segment, line parameters associated with the candidate snap location can be implemented in the path segment. Such parameters can include weight, color, and curvature of the path segment. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: February 26, 2019
    Assignee: ADOBE INC.
    Inventors: Narciso Batacan Jaramillo, Tomas Krcha
  • Patent number: 10163238
    Abstract: A graphics processing core of a tile-based graphics processing system when processing a tile of a graphics output reads a primitive to be processed off a tile list for the tile being processed, along with an identifier for that primitive. The graphics processing core then checks whether or not the identifier matches the identifier stored for any entry stored in a primitive data cache. A match indicates that primitive-specific data (including line equations, depth equations and barycentric equations) for the primitive to be processed is stored in the cache. If a match is found then the stored primitive-specific data is retrieved and used to process (rasterise and render) the primitive. If no match is found, primitive-specific data is calculated from scratch, stored in the primitive data cache, and used to process the primitive.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: December 25, 2018
    Assignee: Arm Limited
    Inventor: Marko Johannes Isömaki
  • Patent number: 10140681
    Abstract: The present invention relates to a caching method of multi-core graphic processing unit (GPU) for improving image processing performance by efficiently storing video data into the cache memory out of the global memory. One aspect of the present invention is to provide a caching method of graphic processing unit (GPU) having multiple cores wherein at least a part of pixels out of A*B pixels of video data are cached into a cache memory in order to perform image processing on k pixels of N*N size (where, k, N, A and B are natural numbers; k=N*N; A>N; B>N), the method comprising: grouping the at least a part of pixels out of A*B pixels into k pixel groups; mapping the k pixel groups to k cores of the GPU one-to-one basis by utilizing index information of each of the k pixels; and storing video data of the k pixel groups in the cache memory with reference to the mapping result.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: November 27, 2018
    Assignee: INNODEP CO., LTD.
    Inventors: Changseo Kee, Youngju Heo, Sungjin Lee
  • Patent number: 10114865
    Abstract: Tile cache techniques are described. In at least some embodiments, a tile cache is maintained that stores tile content for a plurality of tiles. The tile content is ordered in the tile cache to match a visual order of tiles in a graphical user interface. When tiles are moved (e.g., panned and/or scrolled) in the graphical user interface, tile content can be retrieved from the tile cache and displayed.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: October 30, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Adrian J. Garside, Milena Salman, Vivek Y. Tripathi
  • Patent number: 10037228
    Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: July 31, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Nick Barrow-Williams, Brian Fahs, Jerome F. Duluk, Jr., James Leroy Deming, Timothy John Purcell, Lucien Dunning, Mark Hairgrove
  • Patent number: 10025879
    Abstract: A system, computer readable medium, and method are disclosed for performing a tree traversal operation. The method includes the steps of executing, via a processor, a tree traversal operation for a tree data structure, receiving a transformation node that includes transformation data during the tree traversal operation, and transforming spatial data included in a query data structure based on the transformation data. Each node in the tree data structure is classified according to one of a plurality of nodesets, the plurality of nodesets corresponding to a plurality of local coordinate systems. The processor may be a parallel processing unit that includes one or more tree traversal units, which implement the tree traversal operation in hardware, software, or a combination of hardware and software.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: July 17, 2018
    Assignee: NVIDIA Corporation
    Inventors: Tero Tapani Karras, Samuli Matias Laine, Timo Oskari Aila
  • Patent number: 9965827
    Abstract: A graphics processing system for processing polygons includes a cache with cache lines for storing data entries, each line having a tag for identifying the data stored in the line. The polygons have vertices with which pieces of vertex attribute data are associated. The system also includes processing circuitry which writes, to a line in a first set of lines, data entries associated with pieces of vertex attribute data. The pieces of vertex attribute data are associated with the vertices of a polygon. The processing circuitry also writes a tag including a polygon identifier to identify the polygon associated with the data entries to the line in the first set of lines, and writes, to a second set of lines of the cache, data entries associated with pieces of vertex attribute data. The processing circuitry also writes tags including vertex identifiers to the second set of lines to identify the vertices associated with the data entries.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: May 8, 2018
    Assignee: Arm Limited
    Inventors: Simon Charles, Andreas Engh-Halstvedt
  • Patent number: 9773476
    Abstract: A cache memory apparatus including a cache memory including a bank, a partition configuration unit configured to divide the cache memory into partitions by allocating the bank to a texture among textures for rendering, and a controller configured to receive a partition ID, of texture data requested by a device that performs the rendering, determine whether the requested texture data is stored in a partition corresponding to the partition ID among the plurality of partitions, and output the requested texture data to the device based on a result of the determination.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: September 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwontaek Kwon, Heejun Shim
  • Patent number: 9734548
    Abstract: One embodiment of the present invention includes techniques for adaptively sizing cache tiles in a graphics system. A device driver associated with a graphics system sets a cache tile size associated with a cache tile to a first size. The detects a change from a first render target configuration that includes a first set of render targets to a second render target configuration that includes a second set of render targets. The device driver sets the cache tile size to a second size based on the second render target configuration. One advantage of the disclosed approach is that the cache tile size is adaptively sized, resulting in fewer cache tiles for less complex render target configurations. Adaptively sizing cache tiles leads to more efficient processor utilization and reduced power requirements. In addition, a unified L2 cache tile allows dynamic partitioning of cache memory between cache tile data and other data.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: August 15, 2017
    Assignee: NVIDIA Corporation
    Inventors: Ziyad S. Hakura, Rouslan Dimitrov, Emmett M. Kilgariff, Andrei Khodakovsky
  • Patent number: 9626735
    Abstract: Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Altug Koker, Aditya Navale
  • Patent number: 9600148
    Abstract: An image display apparatus includes a detection unit and a controller. The detection unit detects a specified position on a display screen on which an image is displayed. When the specified position on the display screen is moved, the controller performs a page switching operation or a move operation on the basis of a movement direction in which the specified position is moved. The page switching operation is an operation of switching an image being displayed on the display screen to another image. The move operation is an operation of moving a display position of the image being displayed on the display screen.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 21, 2017
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Kiyoko Shimadate
  • Patent number: 9572080
    Abstract: Systems and methods for vehicle connectivity continuity are provided.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: February 14, 2017
    Assignee: Honeywell International Inc.
    Inventors: Guoqing Wang, Yan Wu, Haixin Li
  • Patent number: 9514563
    Abstract: When processing a set of tiles to generate an output in a tile based graphics processing pipeline, the pipeline, for one or more tiles of the set of tiles, renders one or more render targets containing data to be used in a processing operation (602), and stores the render targets in the tile buffer (604). It also stores some but not all of the sampling position values for a render target or targets for use when processing an adjacent tile of the set of tiles (606). It then performs a processing operation for the tile using the stored render target or targets (608) and one or more stored sampling position values from another, adjacent tile of the set of tiles (610), to generate an output for the tile (612).
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 6, 2016
    Assignee: ARM LIMITED
    Inventors: Sean Tristram Ellis, Jorn Nystad, Andreas Engh-Halstvedt
  • Patent number: 9501412
    Abstract: A cache system includes a processor chip to receive a processing unit address. The cache system also includes a comparator to compare the processing unit address to an address information stored in an allocated tag subset of a tag memory of the processor chip to determine whether the processing unit address matches the address information. The cache system further includes a mapping device to map the portion of the address information to an external memory data, temporarily stored in an allocated data memory subset and a corresponding data memory set of a data memory in the processor. Furthermore, the cache system includes a stacking loop to prioritize the allocated tag subset and a corresponding tag set when the processing unit address matches the address information.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: November 22, 2016
    Assignee: GAINSPAN CORPORATION
    Inventors: Dipankar Talukdar, Alan Herring
  • Patent number: 9491081
    Abstract: Methods, systems, and computer readable media for generating test packets in a network device using value lists caching are disclosed. In one method, value lists are stored in dynamic random access memory of a network test device. Each value lists includes values for user defined fields (UDFs) to be inserted in test packets. Portions of each value lists are read into per-port caches. The UDF values are drained from the per-port caches using per-port stream engines to generate and send streams of test packets to one or more devices under test. The per-port caches are refilled with portions of the value lists from the DRAM and a rate sufficient to maintain the sending of the stream engine packets to the one or more devices under test.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: November 8, 2016
    Assignee: Ixia
    Inventors: Gerald R. Pepper, Matthew R. Bergeron, Johnny Tsung Lin Ho
  • Patent number: 9463692
    Abstract: In the display of an image including a fixed background image and a variation image of the background image, at least one of the amount of data to be held and the amount of work to be processed is reduced. A display control device acquires pixel description data including a combination of position information for specifying a position on a pixel array and address information for specifying an address in an image storage unit of image data which is displayed at the position specified by the position information. Furthermore, the display control device reads out the image data from the address of the image storage unit specified by the address information and specifies the position on the pixel array specified by the image description data to the display to input the read out image data.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: October 11, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Minoru Usui
  • Patent number: 9436972
    Abstract: Methods and systems may provide for executing, by a physically distributed set of compute slices, a plurality of work items. Additionally, the coherency of one or more memory lines associated with the plurality of work items may be maintained, by a cache fabric, across a graphics processor, a system memory and one or more host processors. In one example, a plurality of crossbar nodes track the one or more memory lines, wherein the coherency of the one or more memory lines is maintained across a plurality of level one (L1) caches and a physically distributed cache structure. Each L1 cache may be dedicated to an execution block of a compute slice and each crossbar node may be dedicated to a compute slice.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventors: Altug Koker, Aditya Navale
  • Patent number: 9398297
    Abstract: Techniques related to integral image coding are described herein.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: July 19, 2016
    Assignee: INTEL CORPORATION
    Inventor: Niraj Gupta
  • Patent number: 9390444
    Abstract: A product adaptor of a server receives a request from an interface application associated with the product adaptor. The request includes a request for a subset of all available products that are offered by a communication service provider. The subset of the products includes particular products that a user is permitted to purchase. The product adaptor determining whether a cache of the product adaptor stores a response that satisfies the request based on information in the request. The response includes information about the subset of the products. The product adaptor retrieves the response from the cache of the product adaptor when the cache of the product adaptor stores the response. The product adaptor further transmits the information about the subset of the products to the interface application. The interface application utilizes the information about the subset of the products to offer one or more of the particular products to the user.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: July 12, 2016
    Assignee: VERIZON PATENT AND LICENSING INC.
    Inventors: Ibrahim Itani, Muhammed Shaphy, Yogesh Sawant
  • Patent number: 9324128
    Abstract: Various embodiments are generally directed to techniques for causing the storage of a color data value of a clear color to be deferred or entirely avoided as color data values of primitives of an image are stored. An apparatus includes a processor element; and a logic to store color data values of a block of pixels of the image in a first portion of a cache line, store an indication of the first portion as written and of a second portion of the cache line as not in a per-portion table, evict contents of the first and second portions, and store the contents of the first portion in an image data and store a color data value of a clear color in place of the contents of the second portion in the image data in response to the indications stored in the per-portion table. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 26, 2016
    Assignee: INTEL CORPORATION
    Inventors: Steven J. Spangler, Prasoonkumar Surti, Christopher D. Berry, Hiroshi Akiba
  • Patent number: 9317892
    Abstract: Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 19, 2016
    Assignee: INTEL CORPORATION
    Inventors: Bryan E. Veal, Travis T. Schluessler, Murali Ramadoss, Balaji Vembu
  • Patent number: 9307253
    Abstract: The present invention relates to a method for encoding digital video data corresponding to a sequence of digital source images using a cache memory, each of the digital source images having an equal source image width corresponding to a first number of blocks, the cache memory having a cache width corresponding to a second number of blocks, wherein the second number of blocks is smaller than the first number of blocks.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: April 5, 2016
    Assignee: Axis AB
    Inventor: Stefan Lundberg
  • Patent number: 9277223
    Abstract: In an embodiment, an integrated circuit comprises a decrypt unit configured to decrypt an encrypted, compressed video stream; an on-chip buffer; and a decompressor coupled to the decrypt unit and the on-chip buffer. The decompressor is configured decompress the video stream, and to store a first portion of each of a first plurality of frames decompressed from the video stream in the on-chip buffer. The decompressor is further configured to store a remaining portion of each of the first plurality of frames in an external memory, wherein each frame as stored in the external memory is incomplete because the first portion is not stored in the external memory.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: March 1, 2016
    Assignee: Apple Inc.
    Inventor: Conrad H. Ziesler
  • Patent number: 9224187
    Abstract: Blocks of pixels from a video frame may be encoded in a block processing pipeline using wavefront ordering, e.g. according to knight's order. Each of the encoded blocks may be written to a particular one of multiple buffers such that the blocks written to each of the buffers represent consecutive blocks of the frame in scan order. Stitching information may be written to the buffers at the end of each row. A stitcher may read the rows from the buffers in order and generate a scan order output stream for the frame. The stitcher component may read the stitching information at the end of each row and apply the stitching information to one or more blocks at the beginning of a next row to stitch the next row to the previous row. Stitching may involve modifying pixel(s) of the blocks and/or modifying metadata for the blocks.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 29, 2015
    Assignee: Apple Inc.
    Inventors: Guy Cote, Jim C. Chou, Timothy John Millet, Manching Ko, Weichun Ku
  • Patent number: 9204157
    Abstract: A system and method for organizing pixel information in memory. A method according to an embodiment of the disclosure includes storing data representative of pixels of a scene in a growing window (“GW”) portion of a reference frame in an on-chip memory, storing data representative of pixels of the visual scene in a sliding window (“SW”) portion of the reference frame thereby forming a hybrid window, searching the memory to locate a portion of the stored data that corresponds with data representative of pixels in a current frame descriptive of the scene, performing motion estimation according to results of the search, generating a compressed version of the current frame according to results of the motion estimation, and storing the compressed version for later visual rendering. The system includes a processing unit and a video encoder. The processing unit includes an on-chip memory. The video encoder includes a motion estimation engine and a compression unit.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: December 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ajit Deepak Gupte, Hetul Sanghvi, Herve Catan
  • Patent number: 9171525
    Abstract: A processor and a system are provided for performing texturing operations loaded from a texture queue that provides temporary storage of texture coordinates and texture values. The processor includes a texture queue implemented in a memory of the processor, a crossbar coupled to the texture queue, and one or more texture units coupled to the texture queue via the crossbar. The crossbar is configured to reorder texture coordinates for consumption by the one or more texture units and to reorder texture values received from the one or more texture units.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: October 27, 2015
    Assignee: NVIDIA Corporation
    Inventor: John Erik Lindholm