Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

Abstract: A system, computer readable medium, and method are disclosed for performing a tree traversal operation. The method includes the steps of executing, via a processor, a tree traversal operation for a tree data structure, receiving a transformation node that includes transformation data during the tree traversal operation, and transforming spatial data included in a query data structure based on the transformation data. Each node in the tree data structure is classified according to one of a plurality of nodesets, the plurality of nodesets corresponding to a plurality of local coordinate systems. The processor may be a parallel processing unit that includes one or more tree traversal units, which implement the tree traversal operation in hardware, software, or a combination of hardware and software.

Abstract: A graphics processing system for processing polygons includes a cache with cache lines for storing data entries, each line having a tag for identifying the data stored in the line. The polygons have vertices with which pieces of vertex attribute data are associated. The system also includes processing circuitry which writes, to a line in a first set of lines, data entries associated with pieces of vertex attribute data. The pieces of vertex attribute data are associated with the vertices of a polygon. The processing circuitry also writes a tag including a polygon identifier to identify the polygon associated with the data entries to the line in the first set of lines, and writes, to a second set of lines of the cache, data entries associated with pieces of vertex attribute data. The processing circuitry also writes tags including vertex identifiers to the second set of lines to identify the vertices associated with the data entries.

Abstract: A cache memory apparatus including a cache memory including a bank, a partition configuration unit configured to divide the cache memory into partitions by allocating the bank to a texture among textures for rendering, and a controller configured to receive a partition ID, of texture data requested by a device that performs the rendering, determine whether the requested texture data is stored in a partition corresponding to the partition ID among the plurality of partitions, and output the requested texture data to the device based on a result of the determination.

Abstract: One embodiment of the present invention includes techniques for adaptively sizing cache tiles in a graphics system. A device driver associated with a graphics system sets a cache tile size associated with a cache tile to a first size. The detects a change from a first render target configuration that includes a first set of render targets to a second render target configuration that includes a second set of render targets. The device driver sets the cache tile size to a second size based on the second render target configuration. One advantage of the disclosed approach is that the cache tile size is adaptively sized, resulting in fewer cache tiles for less complex render target configurations. Adaptively sizing cache tiles leads to more efficient processor utilization and reduced power requirements. In addition, a unified L2 cache tile allows dynamic partitioning of cache memory between cache tile data and other data.

Abstract: Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.

Abstract: An image display apparatus includes a detection unit and a controller. The detection unit detects a specified position on a display screen on which an image is displayed. When the specified position on the display screen is moved, the controller performs a page switching operation or a move operation on the basis of a movement direction in which the specified position is moved. The page switching operation is an operation of switching an image being displayed on the display screen to another image. The move operation is an operation of moving a display position of the image being displayed on the display screen.

Abstract: Systems and methods for vehicle connectivity continuity are provided.

Abstract: When processing a set of tiles to generate an output in a tile based graphics processing pipeline, the pipeline, for one or more tiles of the set of tiles, renders one or more render targets containing data to be used in a processing operation (602), and stores the render targets in the tile buffer (604). It also stores some but not all of the sampling position values for a render target or targets for use when processing an adjacent tile of the set of tiles (606). It then performs a processing operation for the tile using the stored render target or targets (608) and one or more stored sampling position values from another, adjacent tile of the set of tiles (610), to generate an output for the tile (612).

Abstract: A cache system includes a processor chip to receive a processing unit address. The cache system also includes a comparator to compare the processing unit address to an address information stored in an allocated tag subset of a tag memory of the processor chip to determine whether the processing unit address matches the address information. The cache system further includes a mapping device to map the portion of the address information to an external memory data, temporarily stored in an allocated data memory subset and a corresponding data memory set of a data memory in the processor. Furthermore, the cache system includes a stacking loop to prioritize the allocated tag subset and a corresponding tag set when the processing unit address matches the address information.

Abstract: Methods, systems, and computer readable media for generating test packets in a network device using value lists caching are disclosed. In one method, value lists are stored in dynamic random access memory of a network test device. Each value lists includes values for user defined fields (UDFs) to be inserted in test packets. Portions of each value lists are read into per-port caches. The UDF values are drained from the per-port caches using per-port stream engines to generate and send streams of test packets to one or more devices under test. The per-port caches are refilled with portions of the value lists from the DRAM and a rate sufficient to maintain the sending of the stream engine packets to the one or more devices under test.

Abstract: In the display of an image including a fixed background image and a variation image of the background image, at least one of the amount of data to be held and the amount of work to be processed is reduced. A display control device acquires pixel description data including a combination of position information for specifying a position on a pixel array and address information for specifying an address in an image storage unit of image data which is displayed at the position specified by the position information. Furthermore, the display control device reads out the image data from the address of the image storage unit specified by the address information and specifies the position on the pixel array specified by the image description data to the display to input the read out image data.

Abstract: Methods and systems may provide for executing, by a physically distributed set of compute slices, a plurality of work items. Additionally, the coherency of one or more memory lines associated with the plurality of work items may be maintained, by a cache fabric, across a graphics processor, a system memory and one or more host processors. In one example, a plurality of crossbar nodes track the one or more memory lines, wherein the coherency of the one or more memory lines is maintained across a plurality of level one (L1) caches and a physically distributed cache structure. Each L1 cache may be dedicated to an execution block of a compute slice and each crossbar node may be dedicated to a compute slice.

Abstract: Techniques related to integral image coding are described herein.

Abstract: A product adaptor of a server receives a request from an interface application associated with the product adaptor. The request includes a request for a subset of all available products that are offered by a communication service provider. The subset of the products includes particular products that a user is permitted to purchase. The product adaptor determining whether a cache of the product adaptor stores a response that satisfies the request based on information in the request. The response includes information about the subset of the products. The product adaptor retrieves the response from the cache of the product adaptor when the cache of the product adaptor stores the response. The product adaptor further transmits the information about the subset of the products to the interface application. The interface application utilizes the information about the subset of the products to offer one or more of the particular products to the user.

Abstract: Various embodiments are generally directed to techniques for causing the storage of a color data value of a clear color to be deferred or entirely avoided as color data values of primitives of an image are stored. An apparatus includes a processor element; and a logic to store color data values of a block of pixels of the image in a first portion of a cache line, store an indication of the first portion as written and of a second portion of the cache line as not in a per-portion table, evict contents of the first and second portions, and store the contents of the first portion in an image data and store a color data value of a clear color in place of the contents of the second portion in the image data in response to the indications stored in the per-portion table. Other embodiments are described and claimed.

Abstract: Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.

Abstract: The present invention relates to a method for encoding digital video data corresponding to a sequence of digital source images using a cache memory, each of the digital source images having an equal source image width corresponding to a first number of blocks, the cache memory having a cache width corresponding to a second number of blocks, wherein the second number of blocks is smaller than the first number of blocks.

Abstract: In an embodiment, an integrated circuit comprises a decrypt unit configured to decrypt an encrypted, compressed video stream; an on-chip buffer; and a decompressor coupled to the decrypt unit and the on-chip buffer. The decompressor is configured decompress the video stream, and to store a first portion of each of a first plurality of frames decompressed from the video stream in the on-chip buffer. The decompressor is further configured to store a remaining portion of each of the first plurality of frames in an external memory, wherein each frame as stored in the external memory is incomplete because the first portion is not stored in the external memory.

Abstract: Blocks of pixels from a video frame may be encoded in a block processing pipeline using wavefront ordering, e.g. according to knight's order. Each of the encoded blocks may be written to a particular one of multiple buffers such that the blocks written to each of the buffers represent consecutive blocks of the frame in scan order. Stitching information may be written to the buffers at the end of each row. A stitcher may read the rows from the buffers in order and generate a scan order output stream for the frame. The stitcher component may read the stitching information at the end of each row and apply the stitching information to one or more blocks at the beginning of a next row to stitch the next row to the previous row. Stitching may involve modifying pixel(s) of the blocks and/or modifying metadata for the blocks.

Abstract: A system and method for organizing pixel information in memory. A method according to an embodiment of the disclosure includes storing data representative of pixels of a scene in a growing window (“GW”) portion of a reference frame in an on-chip memory, storing data representative of pixels of the visual scene in a sliding window (“SW”) portion of the reference frame thereby forming a hybrid window, searching the memory to locate a portion of the stored data that corresponds with data representative of pixels in a current frame descriptive of the scene, performing motion estimation according to results of the search, generating a compressed version of the current frame according to results of the motion estimation, and storing the compressed version for later visual rendering. The system includes a processing unit and a video encoder. The processing unit includes an on-chip memory. The video encoder includes a motion estimation engine and a compression unit.

Abstract: A processor and a system are provided for performing texturing operations loaded from a texture queue that provides temporary storage of texture coordinates and texture values. The processor includes a texture queue implemented in a memory of the processor, a crossbar coupled to the texture queue, and one or more texture units coupled to the texture queue via the crossbar. The crossbar is configured to reorder texture coordinates for consumption by the one or more texture units and to reorder texture values received from the one or more texture units.

Abstract: A client computer group is created at a server computer by selecting a subset of a group of client computers, where each of the group of client computers has a separate communication channel with the server computer. A message from at least one of the subset of the group of client computers is received at the server computer. In response to receiving messages from at least two of the subset of the group of client computers within the client computer group, the messages are grouped under a single unit of work. A single decision associated with the single unit of work for the client computer group is computed. Each of the at least two of the subset of the group of client computers is operable to accept the single decision.

Abstract: In some embodiments of the invention, a system for serving dynamic content objects is provided. The system includes a request fulfiller that: receives a request for a webpage from an end-user system, retrieves a content file associated with the requested webpage, and transmits a modified content file to the end-user system. The system further includes a content-file modifier that generates the modified content file, the content-file modifier including: a dynamic-code detector that detects that the retrieved content file comprises or is associated with a dynamic code; and a reporting-code injector that injects a reporting code into the retrieved content file or an associated content file to produce the modified content file, the reporting code including instructions to report data identifying usage characteristics of one or more content objects. A high-priority content object is identified based on the reported data, and access to the high-priority content object is improved.

Abstract: Methods, apparatus and articles of manufacture for graphics processing of a vertex buffer using a relative index buffer are disclosed. Example methods to process a vertex buffer disclosed herein include accessing a first relative index stored in a relative index buffer, the first relative index specifying an offset from a current index selecting a first entry of the vertex buffer. Such disclosed example methods also include, in response to the first relative index being a nonzero value, processing data associated with a second entry of the vertex buffer to determine a rasterizer output associated with the first entry of the vertex buffer, the second entry of the vertex buffer being selected using the current index offset by the first relative index.

Abstract: A tiled-map display control with a predictive caching technique that minimizes user wait time and provides at least the illusion of continuous panning, even while map tile images are being loaded. Important components of the tiled map display are its definition and cached use of map tiles, as well as the way that the map tiles are put together on a small screen. Easy, seamless, wait-free and convenient viewing of a map for a user of a wireless device provides information, e.g., mapped traffic conditions. The disclosed embodiments are techniques that have been reduced to practice in both a BREW platform, and then in a J2ME platform, and deployed for operation in major carrier wireless networks. The invention has particular applicability for use in wireless devices with typically smaller display screens requiring the need for panning, and limited bandwidth capabilities of the supporting wireless network.

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract: A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Abstract: A system and method for efficiently allocating data in a memory hierarchy. A system includes a memory controller for controlling accesses to a memory and a display controller for processing video frame data. The memory controller includes a cache capable of storing data read from the memory. A given video frame may be processed by the display controller and presented on a respective display screen. During processing, control logic within the display controller sends multiple memory access requests to the memory controller with cache hint information. For the frame data, the cache hint information may alternate between (i) indicating to store frame data read in response to respective requests in the memory cache and (ii) indicating to not store the frame data read in response to respective requests in the memory cache.

Abstract: A three-dimensional computer graphics rendering system allows a tile-based rendering system to operate with a reduced amount of storage required for tiled screen space geometry by using an untransformed display list to represent the screen's geometry.

Abstract: The present disclosure may take the form of a method for enhancing performance of interactive content. The method includes analyzing by a processing element a user actuated object of the interactive content, predicting action of the user actuated object in a proceeding frame of the interactive content, using the predicted action, determining by the processing element if the user actuated object can be cached for the proceeding frame, if the user actuated object can be cached, saving the user actuated object as a bitmap object and display the bitmap object in the proceeding frame and if the user actuated object cannot be cached, rendering a vector graphic of the user actuated object in the proceeding frame.

Abstract: A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor. The two-dimensional (2-D) cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a two-dimensional structure of the 2-D image.

Abstract: A cache line allocation method, wherein the cache is coupled to a graphic processing unit and the cache comprising a plurality of cache lines, each cache line stores one of a plurality of instructions the method comprising the steps of: putting the plurality of instructions in whole cache lines; locking the whole cache lines if an instruction size is less than a cache size; locking a first number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is less than or equal to a threshold; and locking a second number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is large than the threshold; wherein the first number is greater than the second number.

Abstract: An image optimized rolling cache system extracts pixel information and address information of a corresponding pixel from an input image to store the extracted pixel information and the extracted address information, and processes the image by applying a vertical rolling mechanism or a horizontal rolling mechanism using the stored information.

Abstract: One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location of a storage circuit where a target unit of data resides. The hierarchical address comprises a level field indicating a hierarchical level for the unit of data and a node identifier that indicates which GPU within the GPU cluster currently stores the unit of data. The hierarchical address may further comprise one or more identifiers that indicate which storage circuit in a particular hierarchical level currently stores the unit of data. The hierarchical address is constructed and interpreted based on the level field. The technique advantageously enables programs executing within the GPU cluster to efficiently access data residing in other GPUs using the hierarchical address.

Abstract: A graphics or image rendering system, such as a map image rendering system, receives image data from an image database, such as a map database, in the form of vector data having image object elements defined as sets of vertex data points. The image rendering system stores and tabulates the vertex data points used to render an image object element. A code specifies a number of vertex data points that can be obtained from a tracking table as well as an amount of vertex data points to be sent from the image database. An image rendering engine uses the stored and transmitted vertex data points to render the image object element to be displayed.

Abstract: [Problem] The present invention provides an apparatus and a method, which can reduce required memory, for obtaining blur image in computer graphics. [Method of solution] The present invention performs processing leaving only the calculation results of the necessary column to obtain blur image without full memory of the SAT table. As a result, the present invention provides an apparatus and a method, which can reduce required memory, for obtaining blur image in computer graphics.

Abstract: GPU fragment programs can be used to render images in a computer system. These fragment programs are generated from render trees, which specify one or more filters or functions to be applied to an input image to render an output image. It is not uncommon for successive frames to require application of substantially the same filters. Therefore, rather than regenerate and recompile new fragment programs for successive corresponding render trees, the render trees are substantially uniquely identified and cached. Thus, when a render tree is received, it can be identified, and this identifier (such as a hash) can be used to determine whether a corresponding fragment program has already been generated, compiled and cached. If so, the corresponding cached fragment program is retrieved and executed. If not, a fragment program for the newly received render tree is generated and cached.

Abstract: One embodiment of the present invention includes a graphics subsystem for processing multi-sample anti-aliasing work. The graphics subsystem includes a cache unit, a tiling unit, and a screen-space pipeline coupled to the cache unit and to the tiling unit. The tiling unit is configured to organize multi-sample anti-aliasing commands into cache tile batches. The screen-space pipeline includes a pixel shader and a raster operations unit, and receives cache tile batches from the tiling unit. The pixel shader is configured to generate sample data based on a set of primitives and to generate resolved data based on the sample data. The raster operations unit is configured to store the sample data in the cache unit and to invalidate the sample data after the pixel shader generates the resolved data.

Abstract: Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a. memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.

Abstract: The fragment processing pipeline 10 of a graphics processing core 2 has an associated occlusion query cache 19 that is used to maintain a set of local occlusion counters 21. The occlusion query cache 19 is maintained in a local memory 3 of the graphics processing system and can communicate via an interconnect 7 with a set of master occlusion counters 22 in a main memory 5 for the graphics processing system. When an occlusion query starts, a corresponding occlusion counter 22 is initialised in the main memory 5. A corresponding local occlusion counter 21 is also provided in the occlusion query cache 19 in the local memory 3 of the graphics processor, and is used to count the results of the occlusion query. The local occlusion counter value is written back to the occlusion counter 22 for the query in the main memory 5 at the appropriate time for further processing.

Abstract: Tile cache techniques are described. In at least some embodiments, a tile cache is maintained that stores tile content for a plurality of tiles. The tile content is ordered in the tile cache to match a visual order of tiles in a graphical user interface. When tiles are moved (e.g., panned and/or scrolled) in the graphical user interface, tile content can be retrieved from the tile cache and displayed.

Abstract: In one embodiment, a graphics processing unit 170 may support a logical resource using a physical tile pool 350 for sparse data sets. The graphics processing unit 170 may allocate a physical memory allocation into a primary physical tile pool 350. The graphics processing unit 170 may define a mapping for a logical tile set 300 for a logical resource. The graphics processing unit 170 may selectively map a primary logical tile 320 of the logical tile set 300 to a primary physical tile 360 of the primary physical tile pool 350.

Abstract: Some implementations disclosed herein provide techniques for caching memory data and for managing cache retention. Different cache retention policies may be applied to different cached data streams such as those of a graphics processing unit. Actual performance of the cache with respect to the data streams may be observed, and the cache retention policies may be varied based on the observed actual performance.

Abstract: The embodiment of the disclosure discloses a method and terminal for implementing display cache, which comprise storing, in memory, texts to be displayed as text component objects; creating a cache image object with a same size as a stored text component when displaying the text component on a screen. In the solution of display cache according to the embodiment of the disclosure, cache images are only created for text regions. Memory that would be occupied by creating cache images for non-text regions, can be saved, which offers the cache images a smaller area and a less memory occupation. By means of the solution according to the embodiment of the disclosure, a lot of running memory can be saved for programs and memory requirements of a lot of product characteristics can be met, without affecting fast display.

Abstract: A system to process a plurality of vertices to model an object. An embodiment of the system includes a processor, a front end unit coupled to the processor, and cache configuration logic coupled to the front end unit and the processor. The processor is configured to process the plurality of vertices. The front end unit is configured to communicate vertex data to the processor. The cache configuration logic is configured to establish a cache line size of a vertex cache based on a vertex size of a drawing command.

Abstract: The present invention relates to a method for browsing images and an Image browser. The browsing is performed on a display of an electronic device having an image cache and includes the acts of determining an image, from accessible images not already stored in the image cache, being more likely to be displayed during the browsing than one image already stored in the image cache, storing the determined image in the image cache, shifting images presented on the display in response to a user input and at an image shifting rate of S. Said shifting images includes reading image data from the image cache and present the image on the display.

Abstract: Methods, systems, and computer-storage media for performing a method of facilitating caching glyph data in hardware are provided. In embodiments, the method includes referencing a first glyph and a second glyph. Thereafter, a determination is made as to whether to merge the first glyph and the second glyph for rendering together as a set of merged glyphs. If it is determined to merge the first glyph and the second glyph, the merged glyph set including the first glyph and the second glyph are rendered. On the other hand, if it is determined to render the first glyph and the second glyph separately, glyph data associated with the first glyph that is in a hardware glyph cache and glyph data associated with the second glyph that is in the hardware glyph cache are used to render the first glyph and the second glyph separately.

Abstract: Computer-implemented systems, methods and apparatus are provided for rendering different scenes of an application. An application framework is provided that includes a scene controller and a scene cache pre-fetch module that stores at least some of the different scenes as cached scenes. When the scene controller receives a request for a new scene (e.g., to change the current active scene) it can determine whether that new scene is stored at the scene cache pre-fetch module. If so, the scene controller can load the cached scene directly from the scene cache pre-fetch module as a new active scene.