Bit Block Transfer Patents (Class 345/562)
  • Patent number: 11630701
    Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: April 18, 2023
    Assignee: Texas Instmments Incorporated
    Inventors: Niraj Nandan, Hetul Sanghvi, Mihir Narendra Mody
  • Patent number: 11017495
    Abstract: Embodiments improve processing of data by determining if a read-modify-write operation on a frame is necessary or not. Some frames may be converted into a block of 8 bpp data. There may be no need to read the destination since the unnecessary pixels may be protected by the byte-enables. The burst write transfer may be performed for the entire frame when it is 8 bpp depth. An original transfer frame may be split into smaller portions of the frame. One or more of the smaller frame portions may be converted into byte alignment thus obviating the need for the read function to be performed on the smaller frame portions. Accordingly, significant bits of data are no longer processed under this operation which speeds up the overall processing of data. Portions of transfer frames that may not be converted to 8 bpp may be processed with read-modify-write operations.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 25, 2021
    Inventors: Kendrick Esperanza Wong, Masayoshi Nakamura
  • Patent number: 10824716
    Abstract: Techniques for leveraging legacy code to deploy native-code desktop applications over a network (e.g., the Web) are described herein. These techniques include executing an application written in native code within a memory region that hardware of a computing device enforces. For instance, page-protection hardware (e.g., a memory management unit) or segmentation hardware may protect this region of memory in which the application executes. The techniques may also provide a narrow system call interface out of this memory region by dynamically enforcing system calls made by the application. Furthermore, these techniques may enable a browser of the computing device to function as an operating system for the native-code application. These techniques thus allow for execution of native-code applications on a browser of a computing device and, hence, over the Web in a resource-efficient manner and without sacrificing security of the computing device.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 3, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jonathan R. Howell, Jacob R. Lorch, Jeremy E. Elson, John R. Douceur
  • Patent number: 10013731
    Abstract: Methods and systems may include a computing system having a graphics processor with a three-dimensional (3D) pipeline, one or more processing units, and compute kernel logic to process two-dimensional (2D) command. A graphics processing unit (GPU) scheduler may dispatch the 2D command directly to the one or more processing units. In one example, the 2D command includes at least one of a render target clear command, a depth-stencil clear command, a resource resolving command and a resource copy command.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Selvakumar Panneer, Carl S. Marshall
  • Patent number: 9934610
    Abstract: Various embodiments are generally directed to techniques for downloading graphics assets of a software application in a form in which they are rendered as needed on a computing device based on its characteristics and then stored therein for later use. A computer-implemented method includes determining whether a requested graphics asset is stored in a storage of a computing device, retrieving the graphics asset from the storage when the graphics asset is stored in the storage, rendering the graphics asset when the graphics asset is not stored in the storage, and visually presenting the graphics asset on a display of the computing device. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: April 3, 2018
    Assignee: Facebook, Inc.
    Inventor: Ryan Gomba
  • Patent number: 9384523
    Abstract: The subject technology discloses configurations for receiving, by a first process, a set of input events from an application in which the set of input events includes a set of input update commands. The first process writes the set of input update commands into a low-latency graphics pipeline. The subject technology dispatches, by the first process, the set of input update commands from the low-latency graphics pipeline to a second process. The second process receives the set of input update commands from the low-latency graphics pipeline. The subject technology then writes, by the second process, a set of input data into a shared graphics processing unit (GPU) texture.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: July 5, 2016
    Assignee: Google Inc.
    Inventors: Eric Scott Penner, Simon Hatch
  • Patent number: 9324180
    Abstract: A simple technique for zmax-culling on a per-tile basis conservatively estimates the maximum depth of the samples in a tile using a layer of masks and a number of zmax-values. No feedback loop is needed from the depth unit, in some embodiments. In addition, the occlusion test may be masked.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Magnus Andersson, Tomas G. Akenine-Moller, Jon N. Hasselgren
  • Patent number: 9007373
    Abstract: A system, method and a computer-readable medium for creating texture exemplars from images are provided. The texture exemplars are created by receiving an image containing a plurality of pixels representing a plurality of textures, wherein each texture in the plurality of textures is configured to be selectable by a user, determining a desired texture in the plurality of textures contained within the image and defining a scale of the desired texture, generating a heat mapping of the image, wherein the heat mapping indicates location of the desired texture, generating, based on the heat mapping, a plurality of tiles corresponding to the defined scale of the desired texture, and generating an exemplar of desired texture.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: April 14, 2015
    Assignee: Yale University
    Inventors: Yitzchak Lockerman, Holly Rushmeier, Julie Dorsey
  • Patent number: 8933953
    Abstract: A scoreboard for a video processor may keep track of only dispatched threads which have not yet completed execution. A first thread may itself snoop for execution of a second thread that must be executed before the first thread's execution. Thread execution may be freely reordered, subject only to the rule that a second thread, whose execution is dependent on execution of a first thread, can only be executed after the first thread.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Hong Jiang, James M. Holland, Prasoonkumar Surti
  • Patent number: 8847971
    Abstract: A device includes a processor which executes a process including generating data of a second graphic identified by shifting each of first sides of a first graphic by a length in a direction toward an inside of the first graphic and by tracing, in a direction, the first sides after the shifting and intersection points between the first sides after the shifting, generating data of a third graphic by shifting each of second sides of the second graphic to both sides of each of the second side by the length and by linking end points of the second sides after the shifting using a circular arc which is centered on an end point of the second side before the shifting and which has a radius of the length, and generating data of a fourth graphic by performing a logical addition operation between the second graphic and the third graphic.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: September 30, 2014
    Assignee: Fujitsu Limited
    Inventors: Tomo Kaniwa, Takahiko Orita
  • Patent number: 8847981
    Abstract: A method and apparatus for accumulative vector drawing are provided. The method includes receiving a graphics command, accumulating the graphics command, and rendering the graphics command in an order reverse to an order in which the graphics command was stored, and when the graphics command is a valid definite drawing command, calculating a clipping area of the valid definite drawing command and reflecting the clipping area when rendering graphics commands rendered after the valid definite drawing command.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung-hee Cho
  • Patent number: 8723878
    Abstract: A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by b*x columns of memory locations. Each memory location is adapted to store n-bit image data for one of the pixels of the display device. A memory location remapping circuit is adapted to map image data stored in the b*x columns of memory locations in the memory device to the a*x columns of the display device.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: May 13, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongkon Bae, Kyuyoung Chung
  • Patent number: 8693042
    Abstract: The disclosure discloses an image copying method, which includes the steps of: copying, an image to be copied, to a destination address line by line, in the case of the image to be copied having a width of one pixel; copying, the image to be copied, to the destination address by a number of bytes according to a size of the image to be copied, in the case of the image to be copied not having a width of one pixel. The image copying method can save the image copying time and deduce the Central Processing Unit (CPU) occupation rate.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: April 8, 2014
    Assignee: ZTE Corporation
    Inventors: Jianhua Xiao, Jianfei Yu, Keying Fang
  • Patent number: 8581933
    Abstract: A method controls display of an image by dividing a source image into a plurality of M×N blocks of pixels, selecting a first one of the blocks, and transferring the pixels in the first block from a source memory to a display memory, the pixels in the first block transferred based on orientation change information. The selecting and transferring steps are then repeated to transfer pixels in remaining ones of the blocks to the display memory. Each block corresponds to only a portion of the source image, where any given portion represents less than a full line of pixels in the source image.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: November 12, 2013
    Assignee: LG Electronics Inc.
    Inventors: Guruprasad Nagaraj, Krishna Koteshwara Sridhar Murthy, Vijayalaxmi Patil, Nataraja Kambadahalli Muniyappa, Sunil Ramappa Nyamagouda
  • Patent number: 8432409
    Abstract: A computer readable medium embodies a set of instructions. The set of instructions includes an instruction to manipulate a processor to determine a first value representative of a source memory location of a source storage component, a second value representative of a destination memory location of a destination storage component, a third value representative of a number of lines of a data block to be transferred from the source storage component to the destination storage component, a fourth value representative of a number of bytes to be transferred per line of the data block, a fifth value representative of a byte width of the source storage component and a sixth value representative of a byte width of the destination storage component. The instruction further is to transfer a data block from the source storage component to the destination storage component based on the first, second, third, fourth, fifth and sixth values.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: April 30, 2013
    Inventors: Frederick S. Dunlap, Mark A. Krom, Adam Snay
  • Patent number: 8326083
    Abstract: An image processing circuit includes: a memory that stores the location and pixel values that compose graphical images; a calculation unit that calculates the difference between a target location to which the graphical images is aligned in binary image data and an initial location designated in the graphical images; an output unit that outputs pixel values at locations distanced from the locations of the pixel values by an amount equivalent to the calculated difference; a first multiplier that multiplies the output pixel value with the pixel value included in the binary image data; an inverter that inverts the pixel value in the binary image data; a second multiplier that multiplies the pixel values in the binary image data or the pixel values included in background image data with the inverted pixel values; and an adder that adds the result of the multiplications performed by the first and second multipliers.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: December 4, 2012
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiyuki Ono, Takashi Sawasaki, Akira Saito
  • Patent number: 8319783
    Abstract: A system and method for performing zero-bandwidth-clears reduces external memory accesses by a graphics processor when performing clears and subsequent read operations. A set of clear values is stored in the graphics processor. Each portion of a color or z buffer may be configured using a zero-bandwidth-clear command to reference a clear value without writing the external memory. The clear value is provided to a requestor without accessing the external memory when a read access is performed.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: November 27, 2012
    Assignee: NVIDIA Corporation
    Inventors: David Kirk McAllister, Steven E. Molnar, Peter B. Holmqvist, Jerome F. Duluk, Jr., Cass W. Everitt, Emmett M. Kilgariff, Patrick R. Brown, Christian Johannes Amsinck
  • Patent number: 8300699
    Abstract: A system, method and computer-readable medium for reducing the required throughput in an ultra-wideband system is provided. A temporal sub-sampling routine limits the number of frames, or portions thereof, to be transmitted to a sink over an RF link. The temporal sub-sampling routine may have a fixed, or static, sub-sampling rate that specifies the rate at which frames are discarded. In accordance with another embodiment, an automatic temporal sub-sampling mechanism is provided. Additionally, a tile copying mechanism may be implemented for reducing the throughput of the RF link. A WDV subsystem may include an interface to an external frame buffer that facilitates the temporal sub-sampling and tile copy routines disclosed herein.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: October 30, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Fred S. Stivers, Felix C. Fernandes, Sidney B. Schrum, Jr., Matthew B. Shoemake
  • Patent number: 8254680
    Abstract: An apparatus usable in an image encoding and/or decoding system includes a segmentation unit to convert a first image of a first resolution into a second image of a second resolution, to segment the second image of the second resolution with one or more blocks of a binary mask layer having a foreground and a background, and to convert the segmented second image into a third image of a third resolution as a segmented image.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: August 28, 2012
    Assignees: Samsung Electronics Co., Ltd., Purdue Research Foundation
    Inventors: Hyung-Soo Ohk, Jonghyon Yi, Charles A. Bouman, Eri Haneda
  • Patent number: 8169444
    Abstract: A bit block transfer (Bitblt) circuit includes a read register, a write register, a bit shifting circuit and an overflowing register. The read register stores decomposition data including original data. The bit shifting circuit shifts the decomposition data in the read register to the write register and shifts bits of the decomposition data in the write register such that an initial bit of the original data of the decomposition data is situated apart from an initial address of the write register by a bit-shifting amount. The overflowing register coupled to the write register stores overflowing data of the original data overflowing from a memory length of the write register when the bits of the decomposition data in the write register are being shifted. The write register outputs and writes the decomposition data therein to a memory cell of a first memory.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: May 1, 2012
    Assignee: Himax Technologies Limited
    Inventors: Chou-Liang Tsai, Tzung-Ren Wang
  • Patent number: 8098254
    Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 17, 2012
    Assignee: NVIDIA Corporation
    Inventors: Krishnan Sreenivas, Koen Bennebroek, Sanford S. Lum, Karthik Bhat, Stefano A. Pescador, David G. Reed, Brad W. Simeral, Edward M. Veeser
  • Patent number: 7978200
    Abstract: Stochastic dithering may be used to reduce the size of the frame buffer and the complexity of the D/A Converters (DACs) in the drive circuitry that are used in a video display system. Hardware for stochastic dithering can be simplified when pixel data is presented in raster order. The hardware adds algebraic noise to the image to be dithered, and thresholds the result.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: July 12, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey A. Small, John S. Childs, Jeffrey Lillie, Vladimir Misic
  • Patent number: 7898550
    Abstract: Various embodiments for reducing external bandwidth requirements for transferring graphics data are included. One embodiment includes a system for reducing the external bandwidth requirements for transferring graphics data comprising a prediction error calculator configured to generate a prediction error matrix for a pixel tile of z-coordinate data, a bit length calculator configured to calculate the number of bits needed to store the prediction error matrix, a data encoder configured to encode the prediction error matrix into a compressed block and a packer configured to shift the compressed block in a single operation to an external memory location.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: March 1, 2011
    Assignee: VIA Technologies, Inc.
    Inventors: Boris Prokopenko, Timou Paltashev
  • Patent number: 7876327
    Abstract: Display data and video data are stored within a graphics processing unit to reduce power consumed by the computing device during video playback. Storing display data and video data within the GPU reduces power consumption, because bus transaction activity is reduced and the need to read data from a larger, common main memory is avoided.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: January 25, 2011
    Assignee: NVIDIA Corporation
    Inventors: Krishnan Sreenivas, Koen Bennebroek, Sanford S. Lum, Karthik Bhat, Stefano A. Pescador, David G. Reed, Brad W. Simeral, Edward M. Veeser
  • Patent number: 7830393
    Abstract: In the case where a previous character (P1) is cleared on a screen (20) and a new character (P2) is displayed on the right of the previous one, first, image data to be transferred (P2) is prepared in a source image memory. Next, a write start address (W) is set at the head of a bit sequence of a left clearance width (LC)×BPP, which precedes the destination address (T) of a frame buffer into which the head (S) of the image data (P2) is to be written. After that, a series of burst transfer repeatedly copies clearance data held in a register into a region of the left clearance width (LC), starting from the write start address (W), and subsequently writes one line (a transfer width (W1)×BPP) of the image data (P2). The write start address is incremented by a frame width (FW)×BPP.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: November 9, 2010
    Assignee: Panasonic Corporation
    Inventor: Yorihiko Wakayama
  • Patent number: 7821521
    Abstract: Embodiments of the present invention provide a seamless way to emulate legacy graphics processing on modern graphics hardware. In particular, in some embodiments, the present invention provides a way for modern GPUs to emulate the bitwise operations and rendering processes of previous generations of graphics hardware. The present invention utilizes a novel pixel shader program. The pixel shader program provides a texture lookup functionality that compensates for any missing bitwise functionality. When a bitwise operation is requested, the system will copy out the destination area to a temporary image. This temporary image is fed to the pixel shader program along with a precomputed texture. The texture is precomputed by the CPU for the various bitwise operations and acts as a lookup table for the requested operation. With the temporary image and precomputed texture, the shader program on the GPU can then emulate the legacy graphics operations seamlessly.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: October 26, 2010
    Assignee: Red Hat, Inc.
    Inventor: Adam Jackson
  • Patent number: 7787707
    Abstract: Image-processing device for ROP is disclosed. Upon receiving a ROP command, the image-processing device determines whether the size of the brush data is required to be modified through a size modifying operation, based on the printing resolution of the printing device. If the size modifying operation is necessary, the image-processing device performs a process to enlarge or reduce the brush data, depending on the printing resolution. The image-processing device converts the ROP code associated with the operational expression using brush data to a combination of ROP codes associated with operational expressions using the source bitmap, but not brush data. The image-processing device controls a ROP processor to perform the ROP processes corresponding to these ROP codes using the enlarged or reduced brush data as the source bitmap in order to implement a ROP process equivalent to the ROP code inputted with the ROP command.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: August 31, 2010
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Yuji Miyata, Kenichi Watanabe
  • Patent number: 7782331
    Abstract: An exemplary method for performing a bit block transfer (bitblt) includes receiving one or more graphics parameters specifying the bitblt and generating a specialized bitblt function to perform the bitblt. The specialized bitblt function includes a one or more code blocks selected from a superset of code blocks based on the graphics parameters. A system includes a specialized bit block transfer (bitblt) function generator generating a specialized bitblt function to perform a specified bitblt. The specialized bitblt function includes intermediate language code corresponding to one or more graphics parameters specifying the bitblt. A translator translates the specialized bitblt function into machine-specific language code.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: August 24, 2010
    Assignee: Microsoft Corporation
    Inventors: Jeffrey R Sirois, Joshua W Buckman, Kent D. Lottis
  • Publication number: 20090164713
    Abstract: A bit block transfer (Bitblt) circuit includes a read register, a write register, a bit shifting circuit and an overflowing register. The read register stores decomposition data including original data. The bit shifting circuit shifts the decomposition data in the read register to the write register and shifts bits of the decomposition data in the write register such that an initial bit of the original data of the decomposition data is situated apart from an initial address of the write register by a bit-shifting amount. The overflowing register coupled to the write register stores overflowing data of the original data overflowing from a memory length of the write register when the bits of the decomposition data in the write register are being shifted. The write register outputs and writes the decomposition data therein to a memory cell of a first memory.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Chou-Liang Tsai, Tzung-Ren Wang
  • Patent number: 7545380
    Abstract: Method, apparatuses, and systems are presented for processing an ordered sequence of images for display using a display device, involving operating a plurality of graphics devices, including at least one first graphics device that processes certain ones of the ordered sequence of images, including a first image, and at least one second graphics device that processes certain other ones of the ordered sequence of images, including a second image, the first image preceding the second image in the ordered sequence, delaying at least one operation of the at least one second graphics device to allow processing by the at least one first graphics device to advance relative to processing by the at least one second graphics device, in order to maintain sequentially correct output of the ordered sequence of images, and selectively providing output from the graphics devices to the display device.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: June 9, 2009
    Assignee: Nvidia Corporation
    Inventors: Franck R. Diard, Wayne Douglas Young, Philip Browning Johnson
  • Patent number: 7525549
    Abstract: Method, apparatuses, and systems are presented for processing a sequence of images for display using a display device involving operating a plurality of graphics devices, including at least one first graphics device that processes certain ones of the sequence of images, including a first image, and at least one second graphics device that processes certain other ones of the sequence of images, including a second image, delaying processing of the second image by the at least one second graphics device, by a specified duration, relative to processing of the first image by the at least one first graphics device, to stagger pixel data output for the first image and pixel data output for the second image, and selectively providing output from the at least one first graphics device and the at least one second graphics device to the display device.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: April 28, 2009
    Assignee: Nvidia Corporation
    Inventors: Franck R. Diard, Wayne Douglas Young, Philip Browning Johnson
  • Patent number: 7522171
    Abstract: A system of processing data in a graphics processing unit having a core configured to process data in hexadecimal form and other graphics modules configured to process data in quads includes a transpose buffer with a crossbar to reorganize incoming data, several memory banks to store the reorganized data over a period of several clock cycles, and a second crossbar for reorganizing the stored data after it is read from the bank of memories in one clock cycle. The method for converting between data in hexadecimal form and data in quads includes providing data in hexadecimal form, reorganizing the data provided in hexadecimal form, storing the reorganized data in several memories, and reading several of the memory locations, which contain all of the elements of the quad, in one clock cycle.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: April 21, 2009
    Assignee: NVIDIA Corporation
    Inventor: Bryon S. Nordquist
  • Patent number: 7508397
    Abstract: Methods, apparatuses, and systems are presented for modifying data in memory associated with an image, involving processing data operations in a pipelined process affecting data in memory corresponding to the image. The data operations include a first data operation involving a first read operation followed by a first write operation, and a second data operation involving a second read operation followed by a second write operation. After starting the first read operation, a determination is made whether data associated with the first data operation overlaps with data associated with the second data operation. If a data overlap occurs, the second read operation is started after the first write operation is completed, and if no data overlap occurs, the second read operation is started before the first write operation is completed.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: March 24, 2009
    Assignee: Nvidia Corporation
    Inventors: Steven E. Molnar, Justin Legakis
  • Patent number: 7460128
    Abstract: In an image drawing apparatus for conducting a data transfer at a bit unit for image data stored in a memory device, a region storing part stores a region where at least one attribute value concerning a pixel is not constant in the image data, an attribute value storing value stores each attribute value of pixels in the region, a constant value storing part stores a constant value as the attribute value, an inside region determining part determines whether or not a coordinate being transferred is within the region, and a selection signal generating part selects one of the attribute value storing part as a selected storing part and the constant value storing part based on a determination result obtained by the inside region determining part, and generating a selection signal indicating the selected storing part, wherein a predetermined process for source image data is conducted by obtaining the attribute value from the selected storing part.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: December 2, 2008
    Assignee: Fujitsu Limited
    Inventors: Takahiro Oka, Munenori Takimoto
  • Patent number: 7379070
    Abstract: An exemplary method for performing a bit block transfer (bitblt) includes receiving one or more graphics parameters specifying the bitblt and generating a specialized bitblt function to perform the bitblt. The specialized bitblt function includes a one or more code blocks selected from a superset of code blocks based on the graphics parameters. A system includes a specialized bit block transfer (bitblt) function generator generating a specialized bitblt function to perform a specified bitblt. The specialized bitblt function includes intermediate language code corresponding to one or more graphics parameters specifying the bitblt. A translator translates the specialized bitblt function into machine-specific language code.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: May 27, 2008
    Assignee: Microsoft Corporation
    Inventors: Jeffrey R Sirois, Joshua W. Buckman, Kent D. Lottis
  • Patent number: 7362333
    Abstract: Methods to manipulate the mobile wireless device screen more efficiently are provided. The method and devices allow a graphical user interface to be used more efficiently on a mobile handset with limited processing ability. A graphical user interface can be implemented on a mobile wireless device efficiently by limiting processing to only the areas of the display screen on the mobile wireless device that is changing. For example, if a graphical item is to be displayed on the display screen the value in the display screen memory location that will be covered by the graphical item can be stored for future use. If the graphical item is later moved the stored value can be retrieved and efficiently written to the display without the need to recalculate what was behind the graphical item.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: April 22, 2008
    Assignee: Kyocera Wireless Corp.
    Inventors: Sumita Rao, Gowri Rajaram
  • Patent number: 7307634
    Abstract: The method of one embodiment for the invention is for the CPU to read a subset of consecutive pixels from RAM and cache each such pixel in the WC Cache (and load corresponding blocks into the L2 Cache). These reads and loads continue until the capacity of the L2 Cache is reached, and then these blocks (a “band”) are iteratively processed until the entire band in the L2 Cache has been written to the frame buffer via the WC Cache. Once this is complete, the process then “dumps” the L2 Cache (that is, it ignores the existing blocks and allows them to be naturally pushed out with subsequent loads) and the next band of consecutive pixels is read (and their blocks loaded). This process continues until the portrait-oriented graphic is entirely loaded.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: December 11, 2007
    Assignee: Microsoft Corporation
    Inventor: Donald David Karlov
  • Patent number: 7222305
    Abstract: A method of facilitating the reproduction of a presenter's desktop for attendees of a real-time collaboration. A bound portion of the desktop (the portion shared with the attendees) is logically divided into clusters. When the content of a cluster changes, the cluster is analyzed and one or more objects describing the content may be identified. Each object that is not already cached is cached and assigned a cache ID. Each object in the cluster is described in an object primitive to be sent to the attendees. Actions for reproducing the object on the attendees' clients are sent as action primitives. The object and action primitives allow the content of the presenter's desktop to be sent incrementally instead of sending the entire desktop.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: May 22, 2007
    Assignee: Oracle International Corp.
    Inventors: Ilya Teplov, Aleksey Skurikhin, Paul Huck, Alex Fedotov
  • Patent number: 7164483
    Abstract: Raster operations (ROPs) are executed using a few core blocks which implement the logical operations (e.g., AND, OR, XOR) forming the basis for the raster operations. In an embodiment, the core blocks are generated only for the basic Boolean operations namely AND, OR and XOR for the corresponding operands (one or two of the source, paint and destination). Each logical operation is performed by using the appropriate core block.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: January 16, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Sandeep Yaddula, Gaganjot Singh Maur
  • Patent number: 7061499
    Abstract: An image drawing apparatus includes a first data reading unit which stores a source image data into a first image data buffer. A second data reading unit reads a destination image data from a destination area of a memory device and stores the destination image data into a second image data buffer. A third data reading unit reads a transmission coefficient data from the memory device and stores the transmission coefficient data into a transmission coefficient data buffer. A transmission drawing processing control unit executes a transmission drawing processing for the source image data and the destination image data by using the transmission coefficient data to generate a processed image data. The transmission coefficient data has a block size that is the same as a block size of the source image data, and contains transmission coefficients that are varied with respect to every pixel of the source image data.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: June 13, 2006
    Assignee: Fujitsu Limited
    Inventors: Atsushi Yamada, Hidefumi Nishi
  • Patent number: 7061496
    Abstract: An image data processing system with a memory performing burst read/write operations. The memory includes a memory cell array provided with memory cells arranged in a plurality of rows and a plurality of columns. The image data processing system further includes a controller for controlling an operation of reading/writing the image data from/to the memory. The controller divides the image data into a plurality of segments when a horizontal size of the image data is larger than a column width of the memory. An (I+1)-th (where I is a positive integer) segment includes a last burst data of an I-th segment, or the I-th segment includes a first burst data of the (I+1)-th segment. The respective segments correspond to the plurality of rows of the memory.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: June 13, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Won Yi, Kyoung-Mook Lim
  • Patent number: 6992677
    Abstract: A system and method for accelerating 2D graphics in a computer system is disclosed, which has an graphic chip to perform graphic commands, each graphic command having an operation of a source pixel, a pattern and a destination pixel; and a 2D graphic device driver to set a command register of the graphic chip such that the graphic chip performs a graphic command. When the source pixel and the pattern of the graphic command received by the 2D graphic device driver are both colored, a copy procedure is performed to copy memory corresponding to the source pixel or the pattern and convert corresponding color for display. In addition, the 2D graphic device driver sets the command register of the graphic chip to perform a graphic command operation according to the source pixel or the pattern copied, the remaining one not copied and the destination pixel.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: January 31, 2006
    Assignee: VIA Technologies, Inc.
    Inventor: Phil Hsieh
  • Patent number: 6972770
    Abstract: A method and apparatus in a data processing system for performing a raster operation of graphics data. A system memory and a video memory is included in the data processing system. The system memory and the video memory are connected by a bus wherein the graphics data is organized into picture elements. A plurality of picture elements is read from the system memory. A plurality of picture elements is read from the video memory. A raster operation is performed on the plurality of picture elements to form a plurality of processed picture elements. The plurality of processed picture elements is written to the video memory.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: December 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Marc Leslie Cohen, Scott Thomas Jones, Ravi Ravisankar
  • Patent number: 6952217
    Abstract: A method of self-programming a graphics processing unit (GPU) includes receiving a blit instruction defining a blit operation and storing a first control value in a control register, which determines the behavior of the GPU, using the blit operation. The blit instruction is read by the GPU from a command buffer asynchronously with the CPU. The blit operation is applied to a second control value to determine the first control value. The second control value can be stored in a memory, such as a second control register or a table of control values accessed by an index value. In one application, the second control value is a starting memory address for a display buffer, while in another application, second control value is a clip plane distance. The blit operation can include a copy operation, a colorkey operation, a logic operation, and/or a pattern copy operation on the first control value.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: October 4, 2005
    Assignee: NVIDIA Corporation
    Inventors: Franck R. Diard, Christopher W. Johnson
  • Patent number: 6943804
    Abstract: Systems and methods are provided for performing a BLT (BLock Transfer). In accordance with one embodiment, a method uses a texture-mapping subsystem to perform the BLT by configuring the texture-mapping subsystem with coordinate values corresponding to a block of pixels to be transferred. In accordance with another embodiment, an apparatus comprises logic for defining a texture map from a source segment of memory corresponding to a frame buffer, logic for configuring a texture-mapping subsystem with coordinate values corresponding to a first block of pixels on a display, logic for using a texture-mapping subsystem to apply the texture map defined by the configured coordinate values to a destination segment of memory corresponding to a second block of pixels on the graphic display, wherein the application of the texture map effects a BLT of the data from the first block of pixels to the second block of pixels.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: September 13, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Byron A. Alcorn, Ronald D. Larson, Larry Jay Thayer
  • Patent number: 6924813
    Abstract: A method of eliminating stale information from a computer graphics buffer. The method facilitates switching from a fast clear mode to a non fast clear mode during the lifetime of a region of interest such as a window: A clear count value associated with a pixel is read and compared with a current clear count. If the counts are not equal, a replacement value is written into the pixel. The process may be repeated for each pixel in the region. Block transfer hardware and fast clear hardware may be used together to perform the procedure in a high-performance manner: A source region and a destination region for the block transfer operation are both set to the region of interest. As the block transfer proceeds, each pixel is written either with its own value or with a replacement value depending on whether the clear count for the pixel is current.
    Type: Grant
    Filed: March 31, 2001
    Date of Patent: August 2, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Calvin Selig, Ethan W Gannett, Kendall F Tidwell
  • Patent number: 6903744
    Abstract: A system is provided for storing pixel data associated with a predetermined pixel region. The system is configured to store pixel data in a predetermined block of memory along with a fill check bit indicative of whether or not values for each pixel within the pixel region are the same as a predetermined reference pixel. The system also provides for the generation of a stream of pixel data corresponding to a pixel region by outputting a value for a pixel within the region that is equal to the reference pixel when the fill check bit is set.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: June 7, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Darel N Emmot
  • Patent number: 6900813
    Abstract: A method and apparatus determines if a BLT command meets BLT override criteria. If the BLT override criteria is met, the method and apparatus performs a BLT command override and instead executes a FLIP operation instead of performing a BLT operation.
    Type: Grant
    Filed: October 4, 2000
    Date of Patent: May 31, 2005
    Assignee: ATI International SRL
    Inventor: Steve Stefanidis
  • Patent number: RE41967
    Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: November 30, 2010
    Inventors: Takatoshi Ishii, Edmund Cheung, Sherwood Brannon
  • Patent number: RE43235
    Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 13, 2012
    Assignee: Faust Communications, LLC
    Inventors: Takatoshi Ishii, Edmund Cheung, Sherwood Brannon