Abstract: A sliding window (block) system incorporating a methodology for providing a processor access to image data is described. In an exemplary embodiment, the system operates as follows. An image is received for processing that has a size that is too large for the processor to access directly. As a result, the sliding window system creates first, second, and third swappable windows (blocks) for accessing image data from the image; each windows is swappable so that any two are available within the memory space of the processor while a third is being loaded in a background memory. The system cycles through the three windows such that, at any given point in time, two of the three windows are affixed in the memory space of the processor as left and right adjacent windows, while the remaining or third window is being loaded in the background (e.g., in a DRAM) as a temporary shadow or background window. After the shadow window is loaded with appropriate image data, it is brought into the foreground (i.e.

Abstract: A memory system and methods of operating the same that drastically increase the efficiency in memory use and allocation in graphics systems. In a graphics system using a tiled architecture, instead of pre-allocating a fixed amount of memory for each tile, the invention dynamically allocates varying amounts of memory per tile depending on the demand. In one embodiment all or a portion of the available memory is divided into smaller pages that are preferably equal in size. Memory allocation is done by page based on the amount of memory required for a given tile.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: A system is provided for processing graphics data and outputting a stream of pixel data for display on an associated display device. The system is configured to store composed pixel data in a predetermined block of memory. The block of memory corresponds to a predetermined scan line of an associated display device.

Abstract: A data processing system comprising a block move engine, a memory, a register and a reader. The block move engine may be configured to process data. The memory may be configured to store data in the form of a linked list comprising a plurality of items of control data. The register may be associated with the block move engine and configured to control the block move engine, in response to the control data. The reader may be configured to read the control data from the memory and apply the control data to the register.

Abstract: A method and apparatus in a data processing system for processing a request to display a pattern. A plurality of partitions is created in a memory in a graphics adapter in the data processing system, wherein each partition within the plurality of partitions has a size equal to each of the other partitions within the plurality partitions. A determination is made as to whether the pattern is present within the plurality of partitions. The pattern is displayed using the plurality of partitions if the pattern is present within the plurality of partitions. The pattern is retrieved from another location if the pattern is absent from the plurality of partitions. Responsive to retrieving the pattern from another location, the pattern is stored if the pattern is within the size.

Abstract: Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.

Abstract: Systems and methods for managing window transparency for a computer display, making windows wholly transparent or semi-transparent, on a window-by-window basis. Window transparency is triggered by monitoring messages exchanged between a program and an operating system, or by a user action. Upon detection of a first message indicating that a window of the display should be transparent, a layered display mode for the window is initiated. Upon detection of a second message indicating that the window should no longer be transparent, the layered display mode for the window is terminated. The layered mode can be controlled by the operating system or by a graphics processor.

Abstract: A system and method for accelerating 2D graphics in a computer system is disclosed, which has an graphic chip to perform graphic commands, each graphic command having an operation of a source pixel, a pattern and a destination pixel; and a 2D graphic device driver to set a command register of the graphic chip such that the graphic chip performs a graphic command. When the source pixel and the pattern of the graphic command received by the 2D graphic device driver are both colored, a copy procedure is performed to copy memory corresponding to the source pixel or the pattern and convert corresponding color for display. In addition, the 2D graphic device driver sets the command register of the graphic chip to perform a graphic command operation according to the source pixel or the pattern copied, the remaining one not copied and the destination pixel.

Abstract: A digital image processing circuit for replacing an input code associated with a pixel of the image with an output code selected in a first memory containing a set of codes, including an input bus for receiving the input code, an output bus for providing the output code, said first memory, means of address calculation of the first memory, means of address selection of the first memory between the input code and an address code generated by the address calculation means, a second memory for containing an address code generated by the address calculation means, and means of selection of the output code between a code read from the first memory and said code contained in the second memory.

Abstract: Systems and methods are provided for performing a BLT (BLock Transfer). In accordance with one embodiment, a method uses a texture-mapping subsystem to perform the BLT by configuring the texture-mapping subsystem with coordinate values corresponding to a block of pixels to be transferred. In accordance with another embodiment, an apparatus comprises logic for defining a texture map from a source segment of memory corresponding to a frame buffer, logic for configuring a texture-mapping subsystem with coordinate values corresponding to a first block of pixels on a display, logic for using a texture-mapping subsystem to apply the texture map defined by the configured coordinate values to a destination segment of memory corresponding to a second block of pixels on the graphic display, wherein the application of the texture map effects a BLT of the data from the first block of pixels to the second block of pixels.

Abstract: A method of transferring a block of graphics data for display on a screen along a data bus between a processing block and a plurality of addresses in memory comprising the steps of (A) generating a first and a second X and Y coordinate value for each of one or more portions of data to be transferred, (B) calculating a respective address in memory of the plurality of addresses corresponding to each of the first and second coordinate values, (C) accessing the addresses to effect the data transfer, (D) determining if a plurality of bus criteria are met and (E) enabling or inhibiting transfer of the block of data in a data burst in response to the plurality of criterias being met.

Abstract: A computer system having multiple graphics controllers configured to share graphics and video functions, including each executing a portion of a single block transform “BLT” operation in parallel to transfer a block of pixel data from a source to a destination on a graphics surface; and multiple local memories connected to the graphics controllers and configured to store pixel data of a source in a designated pattern allocated to different graphics controllers, wherein each includes a scratch pad for storing, upon request to execute a single BLT operation, all pixel data of the source that are in regions controlled by another graphics controller and copied from the other local memory.

Abstract: A method, graphics engine boolean logic unit and digital video system that provide a raster operation unit capable of providing a raster and non-raster operation function(s) is provided. The raster operation may simultaneously conduct a raster function and non-raster operation function(s) by modification of at least one of a rasterop code and a pattern operand. The invention saves considerable logic since different functions are no longer executed separately and then multiplexed.

Abstract: A method and system for rendering computer graphics display tear-free is provided by determining a safe region for each associated block transfer command in real time. In response to a request of a graphics application program, a block transfer type is determined according to relative positions of a destination bitmap, and a source bitmap on the frame buffer. The invention defines three block transfer types: a top-down block transfer type, a bottom-up block transfer type and a direct block transfer type. Each of these block transfer types has an associated block transfer command for issuing to a command queue. After receiving each associated block transfer command, a safe region for an associated block transfer command will be determined in real time. Then, information from a source bitmap is transferred to a destination bitmap when the position of the current scan line is within the determined safe region defined for the associated block transfer command.

Abstract: A processing system having a CPU core and a cache transfers data between a first block of memory and a second block of memory that is preferably partitioned out of the cache as a non-cacheable scratchpad area and performs address calculations with protection and privilege checks without polluting the cache. Responsive to executing a predetermined instruction, the CPU core signals the cache to prevent caching data during transfer from system to scratchpad memory thereby reducing the number of bus turnarounds while maintaining byte granularity addressability.

Abstract: Systems and methods for repositioning and displaying objects in multiple monitor environments are disclosed. When two or more of the monitors have different color characteristics, images moved between monitors are processed to take advantage of the particular color characteristics of the monitors, while reducing the processing resources that might otherwise be needed to entirely render the image from scratch. For instance, an image positioned within a first monitor space can be repositioned such that a first portion is displayed in the first monitor space and a second portion in the second monitor space. The data representing the first portion of the image is moved from a first location to a second location in a frame buffer in a bit block transfer operation. If the first and second monitors have the same color characteristics, the data representing a second portion is also transferred using a bit block operation.

Abstract: An image drawing apparatus includes a first data reading unit which stores a source image data into a first image data buffer. A second data reading unit reads a destination image data from a destination area of a memory device and stores the destination image data into a second image data buffer. A third data reading unit reads a transmission coefficient data from the memory device and stores the transmission coefficient data into a transmission coefficient data buffer. A transmission drawing processing control unit executes a transmission drawing processing for the source image data and the destination image data by using the transmission coefficient data to generate a processed image data. The transmission coefficient data has a block size that is the same as a block size of the source image data, and contains transmission coefficients that are varied with respect to every pixel of the source image data.

Abstract: A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.

Abstract: A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.

Abstract: A first image data portion and a second image data portion differing from the first image data portion are converted so that they become similar to each other in binary notation. This conversion is performed, for example, by addition. Then, the first and second converted image data portions are transferred so that those converted portions are positioned adjacently to each other in a time-series manner. Finally, after the execution of said transferring step, the first and second image data portions are restored so that those restored portions respectively include original bits. This restoration is performed, for example, by subtraction.

Abstract: A display controller assists a host processor in decoding MPEG data. The display controller receives YUV data in non-pixel video format from a host CPU and perform the otherwise CPU intensive task of rasterization within the display controller. In addition, the display controller may use its internal BITBLIT engine to copy U and V data from one line in a BITBLIT operation to adjacent lines, so as to replicate U and V data. A byte mask preserves Y data on the adjacent lines from being overwritten. At the end of the BITBLIT operation, the display controller generates a signal indicating that the frame buffer has been filled with new data, and thus display controller automatically switches to reading from the newly written frame buffer.

Abstract: A method of providing text data for display in a processor controlled apparatus comprised of storing data defining a text character in a memory, in packed monochrome bit map form, addressing the memory to read the text character data, providing the text character to a graphics processor circuit, performing a bitblt operation on each bit of the text character while providing a color attribute, and storing the packed text character having a color attribute for subsequent display.

Abstract: A method used to test the correctness of image data transited between the system memory and display memory is described as follows. First, a image data A is stored in a location B of the system memory. Then, the data of image A and a location C of display memory are stored into a Bitblt temporary storage means. The Bitblt engine is used to transit the data of image A stored in the location B of system memory to the location C of display memory. Then, the data of location C, location D of display memory, and image A are input into the Bitblt temporary storage means. The Bitblt engine is used to transit the data of image A from the location C to the location D of display memory. The data of image A and location E are input into the Bitblt temporary storage means. The Bitblt engine is used to transit the data of image A from the location D into the location E of the system memory.