Abstract: Accordingly, the present invention is directed to providing methods and apparatus for detecting light energy in real-time while minimizing the effects of background charge accrual on the charge-coupled device. Exemplary embodiments provide relatively fast electronic shuttering and exposure control to minimize accrual of unwanted background illumination. Further, exemplary embodiments can be operated at relatively high speeds without increasing the complexity of electronics used to drive the charge-coupled device or process information produced by the charge-coupled device.

Abstract: A high frame rate camera includes;a multi-channel sensor array for producing a plurality of parallel analog image signals representative of a sensed image;a plurality of analog-to-digital converters (ADC) for converting each of the parallel analog image signals to parallel digital image signals, wherein each of the ADCs has a fine gain parameter which is a function of a top ladder potential and also has a fine offset parameter which is a function of a bottom ladder potential; anda control for controlling the fine gain and offset parameters of each of the ADCs by means of fine gain and offset control signals which are a function of desired average output black and gray levels of the image signal.

Abstract: An image sensor used to implement a system to prevent aliasing problems typically encountered in charge coupled devices where a single charge coupled device is used to sense multiple colors. The image sensor has an imaging region having a substrate of semiconductor material including that which provides for accumulation of charge. The transfer of charge carriers contained within said imaging region is performed to two horizontal shift registers located adjacent to the sensing region. The horizontal shift registers having a series of storage regions for receiving charge carriers from the sensing region. Control is provided for implementing transfer of charge carriers out of the image sensing region and into the horizontal registers. The controlled transfer of charge carriers employs multiple clocking techniques to transfer charge carriers between and out of the horizontal registers.

Abstract: A system architecture is provided that includes an image sensor unit operable in a single channel mode and a dual channel mode. The image sensor unit includes an electronic image sensor comprising a row and column array of pixel elements, wherein the rows of the array having a line length of N pixels. First and second digital signal processing units for processing image data generated by the image sensor unit into color component image data are provided, wherein each of said first and second digital signal processing units has a line length processing capacity less than N pixels.

Abstract: A solid state image sensor comprising a matrix of photosensitive elements adapted to accumulate signal charges corresponding to at least two different aspect ratios, a plurality of vertical shift registers disposed adjacent to columns of the photosensitive elements for a vertical transfer of the signal charges and a plurality of horizontal shift registers corresponding to the respective aspect ratios and disposed in parallel with each other for a horizontal transfer of the signal charges from the vertical shift registers. As a horizontal shift register exclusive to each aspect ratio is provided in the above manner, it is no longer necessary to superimpose the signal outputs of a plurality of buffer amplifiers so that a picture signal corresponding to the desired aspect ratio can be easily read out.

Abstract: There is provided a low-cost CCD solid state imaging device which can make best use of effective pixels and which can obtain images of two or more kinds of aspect ratios without using digital signal processing or any optical means. For creation of wide aspect ratio images, an image is formed by signal charges transferred by a first horizontal CCD. On the other hand, an image is formed by signal charges transferred from the first horizontal CCD to a second horizontal CCD via a coupling, whereby a narrow aspect ratio image with a horizontal dimension shorter than a wide aspect ratio image is created by utilizing any arbitrary horizontal area out of all effective pixels of a light receiving portion, depending on the area where the first horizontal CCD and the second horizontal CCD are coupled with each other by the coupling.

Abstract: A single-output CCD image sensor selectively transfers a normal or a mirror image without changing the combination of clock signals needed by the HCCD. The CCD image sensor comprises VCCD's arrayed in each row, photodiodes connected to the VCCD's through transfer gates, and an upper HCCD connected to one end of the VCCD's. A rotating part for connecting one end of the upper and lower HCCD's as used for one of the normal or mirror image serial transfers. A control gate formed in parallel between the upper and the lower HCCD is used for the other of the normal or mirror image serial transfers, and operates in parallel. An output circuit is connected to the other end of the lower HCCD.

Abstract: A high speed clock driver circuit for use with an area image sensor which has two horizontal shift registers is disclosed. Circuitry is provided which is responsive to the third level of one of the horizontal high speed clock driver signal and the vertical transfer signals for enabling the transfer, in parallel, of pixels from the first register into the second horizontal shift register.

Abstract: A solid state imaging device having a horizontal transfer register formed of a plurality of transfer sections for alternately transferring a signal charge of the same pixel in the horizontal direction wherein a signal charge can be distributed between respective transfer sections in consideration of the amount of signal charges handled by the respective transfer section. In a first horizontal transfer register (4) having transfer sections (4a) and (4b), a control gate section (5) that distributes signal charges between the respective transfer sections (4a) and (4b) has on its one region a potential barrier section (13) formed along the horizontal transfer direction.

Abstract: The present invention is directed to a charge transfer device having a four-phase drive system register in which first, second, third and fourth transfer sections sequentially arrayed constitute one bit. The first, second, third and fourth transfer sections are arranged such that, when applied with drive pulses of the same level, a potential difference occurs between the first and third transfer sections and the second and fourth transfer sections.

Abstract: A CCD linear image sensor comprises an array of linearly arranged photosensor cells, and a pair of CCD shift registers respectively arranged on both sides of the array of linearly arranged photosensor cells. The CCD shift registers are coupled in parallel to the linearly arranged photosensor cell array so as to read out signal charges from predetermined photosensor cells of the linearly arranged photosensor cell array and to transfer the read-out signal charge serially in the CCD shifter register. An output end of each CCD shift register is branched into a pair of CCD shift register transfer paths. An output circuit is connected to an output terminal of each of the branched CCD shift register transfer paths.