Abstract: A pixel conversion apparatus includes a sync separator for separating a sync signal from an input signal, a pixel conversion information analyzer for analyzing how to convert the number of pixels to display the input signal as an image from the input signal and a picture display area, a timing signal generator for generating a timing signal for displaying an image according to the outputs of the sync separator and the pixel conversion information analyzer, a pixel converter for processing a pixel conversion of the input signal according to the output of the timing signal generator, an interpolator for processing a pixel interpolation when the pixel to be interpolated generated by pixel conversion at the pixel converter, and a sync signal generator for generating a sync signal for displaying the input signal as an image.

Abstract: An interpolation filter for video signals includes four circuits to improve video quality in both intra-field and inter-field modes. The interpolation filter is configured to interpolate according to the direction of an image edge. The interpolation filter is also configured to interpolate in a prescribed spatial direction when no image edges can be univocally determined. The first circuit detects an image edge of discrete image elements to generate a first signal. The second circuit uses output from the first circuit to generate a first signal corresponding to an average of the discrete image elements along a direction of the image edge. The third circuit uses output from the first circuit to detect a texture image area wherein an image edge cannot be univocally determined and for generating a second signal depending on a degree of existence of the image edge. The fourth circuit is supplied by the first signal, the second signal and a third signal.

Abstract: A scan converter receives VGA or SVGA graphics data and outputs NTSC or PAL TV data. The scan converter is integrated inside a personal computer's graphics controller, allowing the digital-to-analog converter (DAC) to be used for either CRT-pixel conversion or TV encoding. The VGA timing is altered to better match with TV scan-conversion. The horizontal rate is not constant but can be increased or decreased during the vertical blanking period. A second register is provided for the total number of pixels in a line during vertical blanking, while a first register contains the total number of pixels in a displayable line not during the vertical blanking period. Since lines with fewer pixels require less time to display, the period of time or rate for blanked lines is changed. An extra horizontal line is added during vertical blanking for every second frame for SVGA conversion to better match the asymmetry of TV standards.

Abstract: A bilinear decimator converts an input data sequence representing a high resolution image formed by N horizontal pixel lines to an output data sequence representing a lower resolution image formed by P horizontal pixel lines where N>P. The decimation ratio P/N can be any rational fraction. When the decimation ratio reduces to the form 1-(1/n), the decimator computes the each output sequence data value as a simple weighted average of pixel data values for two vertically adjacent high resolution image pixels. When the decimation ratio is other than of the form 1-(1/n), the decimator adds additional terms to the computation of output pixel data values when necessary to compensate for aliasing errors.

Abstract: In a process for processing a first video picture with image points in m.sub.1 lines, whose image points in the l.sub.1 -th line have an intensity I.sub.1 (t, l.sub.1) depending on a parameter t, in particular depending on time, for generating a second video picture with m.sub.2 lines, the respective intensity I.sub.2 (t, l.sub.2) of an image point in the l.sub.2 -th line of the second video picture is interpolated from the intensities of the image points of the first video picture I.sub.1 (t, l.sub.1), wherein I.sub.2 is obtained according to the following equation:I.sub.2 (t,l.sub.2)=Max(J(t,l.sub.2)+.DELTA.;0),where the values J, with respect to the lines, represent discretized values of a signal waveform given by the sampling theorem and in which an offset .DELTA.

Abstract: A signal converting apparatus and a signal converting method which predictively produce highly accurate interpolated pixels in accordance with a classification which precisely reflects a variety of signal characteristics of inputted video signals to provide a high resolution video signal. An activity is evaluated and classified for each block of an inputted video signal (S.sub.1), and stepwise classifications are executed on each block of the inputted video signal (S.sub.1) in accordance with an activity code (c0) obtained as a result of the activity classification. In this way, the accuracy of subsequent classifications can be increased, reflecting the activity characteristic of each block of the inputted video signal (S.sub.1), thus achieving, as a whole, a highly accurate classification of the inputted video signal (S.sub.1). Appropriate prediction coefficients (d1) are read based on the activity code (c0) and a class code (c1) for each block of the inputted video signal (S.sub.

Abstract: A received 4-2-0 format, 2-1 interlaced digital component video signal is upconverted to a 4-2-2 format, 2-1 interlaced digital component video signal and a vertical chrominance bandwidth expansion enhancement signal is combined with the chrominance components in order to more closely simulate the wider bandwidth vertical chrominance resolution of the original 4:2:2 format signal from which the 4:2:0 format signal was derived. In a first embodiment, the vertical chrominance enhancement signal is derived from vertical transitions in the luminance component of the 4:2:0 format signal. In a second embodiment, the vertical chrominance enhancement signal is derived from vertical transitions in the luminance component of the 4:2:0 format signal when such vertical transitions are present and, in the absence of a luminance transition, the vertical chrominance enhancement signal is derived from the sampling-rate-reduced chrominance components of the 4:2:0 format signal.

Abstract: The present invention aims at providing an image display apparatus capable of displaying both a television signal and an image signal supplied from a personal computer with a high picture quality on a high definition display unit having 1024 by 768 pixels. In order to achieve this object, an image display apparatus according to the present invention includes an NTSC-VGA conversion circuit for converting a television signal to a signal having 640 by 480 pixels and corresponding to the non-interlacing VGA standard, a switch unit for selecting and outputting either the signal outputted from the NTSC-VGA conversion circuit and an inputted image signal from a personal computer, and a VGA-XGA conversion circuit for converting a number of pixels of a signal outputted from the switch unit to a number of pixels 1024 by 768 substantially equivalent to the number of the display unit.

Abstract: Video down-conversion apparatus in which an input, higher definition video signal is converted to an output, lower definition video signal having a smaller number of active lines and/or a smaller number of active pixels per line than the input video signal, comprises: an interpolator for receiving pixels of the input video signal at an input pixel rate and interpolating output data values at the input pixel rate, the output data values comprising active output pixel values interspersed with dummy pixel values; control logic for generating an active enable signal associated with the output data values generated by the interpolator, the active enable signal having a first state when an active output pixel value is generated and a second state when a dummy pixel value is generated; a signal processing device connected to receive the output data values generated by the interpolator, the signal processing device comprising an input latch operable to latch an output data value from the interpolator only when the ac

Abstract: Video down-conversion apparatus in which lines of successive output video field are interpolated from lines of respective input video fields, the apparatus being selectively operable to interpolate each output field from an input field of either field polarity so that the successive output video fields can maintain a regular odd-even field polarity sequence even if there is a discontinuity in the field polarity sequence of the input video fields.

Abstract: A display apparatus capable of receiving and displaying video signals which differ in scanning frequencies or resolutions. The display apparatus includes an input section for receiving at least one video signal and a conversion unit for converting at least one of the frequency and resolution of the at least one received video signal so as to be within predetermined higher ranges thereof. A display unit enables display of the converted received at least one video signal.

Abstract: An interpolation method and apparatus for converting pixels according to image formats, prevents deterioration of picture quality by performing a bilinear conversion which uses a larger number of pixels than does the conventional interpolation method which uses only two pixels. When a ratio between an interpolation point and a vertical line of unconverted pixels is .DELTA.1, a ratio between the interpolation point and a horizontal line of unconverted pixels is .DELTA.2, and eight unconverted pixels A1-A4 and B1-B4 on two lines adjacent to the interpolation position are used along with a coupling coefficient .alpha., a final interpolation signal I is generated according to the following equations:I1=(1-.DELTA.1)(1-.DELTA.2)A1+(1-.DELTA.1).DELTA.2A2+.DELTA.1(1-.DELTA.2)A3 +.DELTA.1.DELTA.2A4;I2=(1-.DELTA.1)(1-.DELTA.2)B1+(1-.DELTA.1).DELTA.2B2+.DELTA.1(1-.DELTA.2)B3 +.DELTA.1.DELTA.2B4; andI=.alpha.I1+(1-.alpha.)I2.

Abstract: A device for decoding digital video data including a variable length decoder (VLD), an inverse discrete cosine transform (DCT) converting part, a movement compensating part, and a first storage device for repeated production of first video frame data responsive to a control signal display format. A second storage device is also employed for reordering and storing second video frame data produced by adding the data from the inverse DCT converting part and the movement compensating part repeatedly and repeated production of stored data in response to a control signal produced according to the display format. A switching device is further included that selectively produces the second video frame data, composed of reordered and repeated production of the first video frame data in response to a selection control signal and a controlling device provides control signals and display format information.

Abstract: A controller for synchronising video signals for displaying on TV screen.

Abstract: A method for processing the information of a still picture of high resolution displayed on a television screen is disclosed. The method includes the steps of receiving the picture information encoded by a pre-set encoding method, generating the averaging information specifying which interpolation is to be performed on the received picture information, decoding the picture information by a decoding method corresponding to the encoding method, storing the decoded picture information in a memory, reading out the stored picture information for processing the decoded picture information with interpolation, and outputting the interpolated picture information as a picture for display. An apparatus for carrying out the information processing method is also disclosed.

Abstract: A variable coefficient, non-separable spatio-temporal interpolation filter is used to deinterlace an interlaced video signal to produce a progressive video signal. The interlaced video signal is input to a video memory which in turn provides a reference and plurality of offset video signals representing the pixel being interpolated and spatially and temporally neighboring pixels. A coefficient index, transmitted with the interlaced video as an auxiliary signal, or derived from motion vectors transmitted with the interlaced video, or derived directly from the interlaced video signal, is applied to a coefficient memory to select a set of filter coefficients. The reference and offset video signals are weighted together with the filter coefficients in the spatio-temporal interpolation filter, such as a FIR filter, to produce an interpolated video signal.

Abstract: An apparatus and method for extending the height of an image to display a video signal having a 4:3 aspect ratio on a screen having a 16:9 aspect ratio.

Abstract: An electronic format converter that can convert a high resolution computer graphics CRT signal to a quasi-television compatible proprietary signal. This subsequently can be recorded to a standard television video cassette recorder (VCR) or transmitted over a standard TV channel and re-converted back to HI-RES computer video with the same device upon playback of the VCR or receipt of the signal from the standard TV channel.

Abstract: An ultrasonic imaging system for an ultrasonic imaging unit generating ultrasonic image data of an interlaced scanning mode, includes a display of a non-interlaced scanning mode and a scanning mode converter for converting ultrasonic image data of the interlaced scanning mode received from the ultrasonic imaging unit into data of a non-interlaced scanning mode and supplying the ultrasonic image data of the non-interlaced scanning mode to the non-interlaced scanning mode display, to thereby provide an ultrasonic image having a better quality of picture in comparison with the interlaced scanning mode. The only ultrasonic image data in which the ultrasonic image data is displayed together with additional data on a screen by the image display of the non-interlaced scanning mode, is converted in the interlaced mode, thereby recording the ultrasonic image data via the conventional VCR.

Abstract: An active matrix display device comprises a plurality of pixels, a vertical scanning circuit, a horizontal scanning circuit, and a thinning-out circuit. The plurality of pixels are arranged in a matrix on a normal standard screen. The vertical scanning circuit is for sequentially selecting pixels every line. The horizontal scanning circuit is for writing single horizontal period portions of a wide standard image signal for selected lines of pixels. The thinning-out circuit is for controlling timing of the vertical scanning circuit sequential selection and thinning-out a prescribed number of horizontal period portions from a wide standard image signal in such a manner that wide displaying compressed in the longitudinal direction of the screen is carried out. It is therefore possible for a normal standard screen to change over to displaying a wide standard image.

Abstract: An image-processor system for compensating for accumulated phase-and-gain errors incurred during transmission of a video signal over a communications channel. The image-processor system comprises an initial-video processor, an input-video processor, a feature-video processor, a frame buffer, an RGB-output processor, an output-video processor, and a control processor. The initial-video processor generates a composite video signal. The input-video processor converts the composite video signal into digital-component signal information. The feature-video processor processes the digital-component signal information as processed component video information. The frame buffer re-establishes broadcast timing standards in the processed component video information to generate time-base corrected digital information. The RGB-output processor decodes the time-base corrected digital information into RGB analog and digital outputs. The analog RGB outputs are output directly.

Abstract: The invention concerns an image display apparatus having a non-interlaced display screen having a first number of display lines, to which an interlaced video signal (RGB-1) having a second number of video lines per field is applied, whereby the first number exceeds the second number but falls below twice the second number. A first line memory device (F1) is used for doubling the line number of the video signal (RGB-1). Second (F2) and third (F3) line memory devices each receive video lines of the line number doubled video signal, and provide a pair of video lines (RGB*, RGB**) at a reduced rate corresponding to the first number of display lines. An interpolator (7) provides the first number of display lines (RGB-2) to the display in response to the pair of video lines (RGB*, RGB**) received from the second (F2) and third (F3) line memory devices.

Abstract: A real-time video system which performs non-uniform interpolation between adjacent vertical scan lines is presented. The video system includes a converter, a memory, an enhanced-video circuit, and a sync generator. The video system decodes and digitizes an analog composite video signal, such as an NTSC, PAL, or SECAM signal, and generates a digital video signal having a greater number of horizontal scan lines than the analog video signal. The video system is programmable to allow a different number of scan lines in the output digital video signal.

Abstract: In an electronic still camera, an imaging device outputs a high-resolution image signal representative of an optical image incident thereto via a lens. A movie processing section reduces, or thins, the high-resolution image signal to produce a corresponding low-resolution image signal on a real-time basis. The camera, therefore, implements the real-time display of a picture converted from the high-resolution image of a subject on a monitor.

Abstract: A scanning line interpolator using a gamma correction memory includes a controller for outputting switching control signals according to an input video signal; an analog/digital converter for converting the input video signal into a digital signal; a first multiplexer for allowing the output signal of the analog/digital converter to pass according to the switching control signal output from the controller; a line buffer having a 1H delay for delaying the digital video signal having passed through the first multiplexer; a gamma correction memory for previously storing the scanning line interpolated digital video signal and then outputting it with the output signals of the analog/digital converter and 1H delay being taken as its addresses; and a second multiplexer for selectively outputting the output signals of the analog/digital converter and gamma correction memory according to the switching control signal output from the controller.

Abstract: A video signal format conversion apparatus, includes a memory for writing an input data by a first clock equal to a sampling rate of the input data and reading the input data by a second clock which is different from the first clock; a shift register for shifting the data read by the memory by the second clock; a multiplication and summation circuit for multiplying each of a plurality of data output from the shift register by a factor corresponding thereto among the plurality of factors and outputting a sum of values obtained by the multiplication by the second clock.

Abstract: A video signal converter comprising a frequency setting circuit, a first clock generator, a second clock generator, an analog-to-digital converter, a line conversion ratio setting circuit, a number of scanning lines converter, a frame memory, a writing controller, a reading controller and a digital-to-analog converter is disclosed. The frequency setting circuit sets a first frequency Fi which satisfies a formula: Fi.ltoreq.(To.times.Fo)/Ti, where Ti is a horizontal scanning period of a first analog video signal, To is a horizontal scanning period of a second analog video signal and Fo is a second frequency. The line conversion ratio setting circuit sets a line conversion ratio R which satisfies an equation: R=m/k, based on a width-to-height ratio 1/m of each pixel of the first digital video data and a width-to-height ratio 1/k of each pixel of second digital video data.

Abstract: An image processing apparatus, for processing a compressed image signal corresponding to an image obtained by optically compressing an object image with a predetermined compression rate, receives the compressed image signal, effects an expansion process on the compressed image signal according to the compression rate thereof, and extracts and releases an image signal corresponding to a part of the image represented by the image signal formed by the expansion, thereby enabling to display a distortion-free image on a monitor.

Abstract: A motion adaptive method for vertically scaling an image. The image data is analyzed to obtain a motion magnitude value for each pixel (31). The pixel data is then processed with two scaling processes (35, 36), performed in parallel. One scaling process is better suited for low motion images and the other is better suited for high motion images. The motion magnitude value is used to select between or combine (38) the pixel data outputs of the two scaling processes (35, 36).

Abstract: Circuitry and methods multiply the number of pixels in a television image without the need for changes in current transmission standards. One memory array or storage buffer is used to store one image, while data is being read from another memory or array storage buffer. The role of the two memory arrays changes with every incoming image, the memory array that was in the read mode is switched to the write mode, and vice-versa. The image read is interpolated through pixel replication in two-dimensions, followed by a square symmetrical two-dimensional low-pass filter, which provides interpolation based on the Sampling Theorem. This may be a two-dimensional (2-D) circularly-symmetrical high-pass filter for image enhancement. Interpolation may alternatively be carried out through a one-dimensional (1-D) filter, or through the Discrete Cosine transform.

Abstract: An input digital image signal (SD signal) is converted into a high resolution digital video signal (HD signal). A considered pixel is categorized as a class corresponding to a one-dimensional, two-dimensional, or three-dimensional level distribution of a plurality of reference pixels of the SD signal. A predicted value of the considered pixel is generated by linear combination of values of a plurality of pixels of the SD signal adjacent to the considered pixel of the HD signal and predicted coefficients that have been learnt. In the learning process, predicted coefficients are determined by linear combination of the values of pixels of the SD signal and the predicted coefficients so that the sum of squares of the predicted value and the true value is minimized. Instead of the predicted coefficients, representative values may be determined for each class. In this case, the representative values are used as predicted values corresponding to the class of the input SD signal.

Abstract: A vertical filter circuit providing a PIP function, which can be used for constructing a sub-screen when the input signal of a main screen is a double-scanned signal or a HDTV signal, compresses the vertical lines of the sub-screen into two-thirds of the original image. Preferably, the vertical filter includes an array of logical elements, a one line memory, two switches for signal routing and a control signal generator operating selected ones of the logical elements and the switches responsive to the horizontal and vertical sync signals.

Abstract: A pixel interpolation system provides for continuous scaling of an image, thus allowing for continuous modification of the size and aspect ratio of the image. A one-dimensional interpolator provides a weighted interpolation between two input pixels using a specified current interpolation weight. The weighting factor is then incrementally changed and further interpolations are sequentially performed across at least one dimension of the image. With one implementation of the system, the scaling across the image remains uniform while the weight varies from one pixel to the next to keep scaling constant. The interpolation operation of this invention may be performed simultaneously both vertically and horizontally.

Abstract: A picture processing system capable of processing a high resolution picture by a conventional picture processor, in which a picture converter is interposed between a camera producing a high resolution picture and a picture processor processing a general purpose picture signal, the picture processor applies coordinates (Xs, Ys) of a specific picture element and sampling intervals about picture element in X and Y axial directions to the picture converter upon the entry of the high resolution picture produced by the camera to the picture converter, the picture converter receives synchronizing signals and a horizontal blanking signal which are produced in the picture processor and subsequently extracts a predetermined picture element data based on the designated data in accordance with the timing of respective signals, and the extracted picture element data is converted to analog general purpose picture signal for application to the picture processor, which is processed by a conventional picture processing method

Abstract: This invention discloses a television signal converting apparatus for converting a television signal of a certain system containing a luminance signal component and chrominance signal components into a television signal of another system likewise containing a luminance signal component and chrominance signal components, in which the first television signal is digitized in synchronization with a frequency of four times of the color sub carrier frequency of the first television signal, and then the digitized first television signal is converted into a digitized second television signal which is converted into an analog signal in synchronization with a frequency of four times of the color sub carrier frequency of the second television signal, whereby the hardware structure can be significantly simplified and the exact conversion of television signal can be realized.

Abstract: A system and method for removing motion artifacts from an interlaced image is disclosed. The interlaced image comprises an odd and an even field. The system and method includes providing one of the odd and the even fields on every other line of the display and then providing a set of constant signal level lines to the remaining lines of the display. The method and system further includes shifting the location of the constant signal levels lines by a scan line responsive to a timing signal from the display, and providing the other of the odd and the even field to the display responsive to the shift.

Abstract: Methods and apparatus for enhancing the definition of television images in real-time is presented. Television video signals are digitized and processed, preferably through 3-D filtering, to increase the number of pixels per line, horizontal lines per frame, and frames per second and provide an output in progressive-scan format. The system accepts an interlaced scanned image of any transmission standard (NTSC, PAL, etc.), and can be adapted to work on progressively scanned images or digitally stored/transmitted images in real-time or off-line.

Abstract: A scan converting apparatus receives an NTSC signal which is scan converted and which has a changed aspect ratio. The subtitle domain, which is vertically overscaned out of the screen and cannot be observed, is extracted and superimposed on the scan converted image. Scanning lines of a brightness output signal of a brightness/chrominance signal separator are interpolated at a scanning line interpolator and are converted to a system which has more scanning lines at a scanning line converter. An odd/even field discriminator prevents deterioration of the resolution of the subtitle letters which is caused by an interchange of the positions between two adjacent scanning lines when the subtitle is transferred to a different field. By stopping the writing of data to a field memory in the subtitle signal processor when a subtitle is transferred, a subtitle transfer can be accomplished even when there is no subtitle on the image.

Abstract: An scanning line interpolating apparatus generates interpolation signals when scanning lines are not included in video signals are formed by interpolation, by adaptively mixing intra-picture interpolation signals formed with upper and lower scanning lines apart from scanning lines to be interpolated and inter-picture interpolation signals formed with pictures before and after the scanning lines to be interpolated. Inter-picture matching signals are obtained between the pictures and used to generate the inter-picture interpolation signals. Low frequency component difference signals are obtained between the intra-/inter-picture interpolation signals. In-and-out matching signals are obtained by obtaining an absolute value of or by squaring the difference signals. An adaptive mixture ratio is varied between the intra-/inter-picture interpolation signals with a signal obtained by adding the matching signals.

Abstract: An adaptive scan format converter (14 FIG. 1; FIG. 2) at a transmitter/encoder of a video signal processing system such as a high definition television (HDTV) system, as a function of what format is desired for coding and transmission via an output channel. Similarly, at a receiver, a received scan format is automatically converted (36, FIG. 1; FIG. 2) to a desired format for display as needed. For example, a received interlaced signal (I) will be automatically converted to progressive (P) format to be compatible with a progressive scan display device (39). A received progressive signal will be passed to the display device without format conversion. Automatic scan conversion is performed seamlessly so that, for example, the conversion between progressive main television program material and interlaced commercial material is produced without artifacts and is essentially invisible to a viewer.

Abstract: The present invention is an NTSC-PAL converter which can eliminate generation of bar noise, and convert image data from the NTSC format to the PAL format with less memory capacity. The converter comprises three field memories (1), (2) and (3) for storing image data in the NTSC format in which odd and even-numbered field data in the NTSC format are sequentially written. In reading for forming the image data in the PAL format, two memories which are not being written are selected so that data are sequentially read from memories in combination of, for example, (1) and (2); (2) and (3), and (3) and (1). That is, frame data for the PAL format is formed by adding and reading field data, and by interpolating them in predetermined interval. This eliminates such situation where writing of image data in the NTSC format overtakes reading of PAL image data.

Abstract: A compact and low cost HDTV receiver is capable of reproducing both an NTSC signal and an HDTV signal. The HDTV signal has a horizontal deflection frequency about twice that of the NTSC signal. The HDTV received includes a construction of a double speed NTSC signal processing portion in the receiver in which a pair of velocity modulation coils 13a and a pair of auxiliary vertical deflection coils 13b are provided on a common bobbin such that the coil pairs are arranged orthogonally to each other.

Abstract: An image reproduction apparatus which converts a sampling frequency from a first frequency to a second frequency, performs interfield interpolation at a third frequency, and converts the sampling frequency from the third frequency to the first frequency, wherein the interfield-interpolation is performed at the first frequency between signals one field apart from each other. The apparatus also converts a number of vertical scanning lines to convert a high definition TV signal of the MUSE format to a signal of NTSC format, sets a scanning period used in the vertical scanning line conversion, and generates a coefficient used in the vertical scanning line conversion.

Abstract: A format conversion is necessary if video picture sequences are to be displayed on computer screens. The conversion is carried out with the aid of a direction dependent interpolation within the moving objects. For this purpose interpolation lines which are rotated with respect to one another are projected through the pixel to be generated and their intersection with adjacently situated lines of pixels in the first pixel raster is determined. The changes in brightness value between the respective intersections of the interpolation lines with the adjacent lines, these intersections being allocated to the individual interpolation directions, are then determined. That interpolation line is selected whose change in brightness value is a minimum compared with the changes in brightness value of adjacently situated interpolation line. The brightness value of the pixel to be generated in then generated by interpolation in the direction of the interpolation line thus determined.

Abstract: A multi-format display system including hardware and algorithms for digital and High Definition Television. The system includes a light source (120), a tuner/preprocessor unit (114), a processor unit (116), a spatial light modulator (118), and a display surface (128). The processor unit can scale and format the data for a number of standardized-format video broadcast signals, and can perform additional interpolation to eliminate artifacts.

Abstract: An image reduction apparatus is disclosed which can sample and reduce an interlace video signal such as a digital video signal uniformly in a vertical direction without sampling out successive lines. A non-delayed horizontal synchronizing signal and a delayed horizontal synchronizing signal are logically ANDed to obtain a double-speed horizontal synchronizing signal having a double speed to that of the horizontal synchronizing signal. The double-speed horizontal synchronizing signal is sampled in accordance with a vertical reduction rate by a vertical sampling circuit to obtain a vertical sampling signal. In the first field, the vertical sampling signal and a vertical address signal are latched into respective latch circuits in response to the non-delayed horizontal synchronizing signal, but in the second field, the signals are latched similarly in response to the delayed horizontal synchronizing signal.

Abstract: A processing apparatus employs motion-adaptive processing to create a progressive scanning signal from an interlaced television scanning signal. The interlaced scanning signal is input to a field delay circuit and to a vertical highpass filter, the output of the field delay circuit is input to a field delay circuit and to a vertical lowpass filter, and the output of the field delay circuit is input to a vertical highpass filter. The outputs of the vertical highpass filters are added together at an adder. The output of the adder is added to the output of the vertical lowpass filter to create an interpolation signal. The interpolation signal and direct-type signal, being time-compressed, are coupled to a switch where they are alternately selected to obtain a progressive scanning signal with improved image quality, irrespective of whether the input signal represents a still or moving image.

Abstract: An improved apparatus for reducing flickers of an encoder capable of advantageously reducing flickers occurred when video signals are converted from a non-interlace scanning method to an interlace scanning method in the digital method, which includes a graphic controller for outputting a pixel signal by a line unit and for outputting a pixel clock, a horizontal synchronous signal and a vertical synchronous signal; a synchronous signal converter for converting a pixel clock, a horizontal synchronous signal and a vertical synchronous signal outputted from the graphic controller to a pixel clock, a horizontal synchronous signal and a vertical synchronous signal of an interlace scanning method; a control signal generator for outputting a control signal by receiving a pixel clock, a horizontal synchronous signal and a vertical synchronous signal of an interlace scanning method outputted from the synchronous signal converter; a line store unit for selecting a pixel data corresponding to nth even scanning line among

Abstract: A video signal processing circuit capable of converting digital color difference signals directly into a carrier chrominance signal is described. The processing circuit includes a first flip-flop for latching the first sampling clock signal of the first and second color difference signals with a second sampling clock signal having a frequency which is an integer multiple of a subcarrier frequency of the carrier chrominance signal to be produced, second and third flip-flops for respectively latching the first and second color difference signals with a third sampling clock signal obtained from the first flip-flop, and carrier chrominance signal generating circuit for generating the carrier chrominance signal from the first and second color difference signals outputted from the second and third flip-flops.

Abstract: A high definition television monitor which raises the level of a convergence voltage by a predetermined voltage in one of two consecutive horizontal periods in which the same video signal is produced, writes the same video image twice on the same line during the consecutive 2H, thereby displaying a video image of the normal standard on a CRT display with a satisfactory picture quality.