Abstract: A binarizer binarizes a video signal VD1 inputted from an A/D converter and a video signal VD2 outputted from a line memory using an average luminance value LU fed from a detection window video signal processor as a threshold value, to output a binary pattern BI. A reference pattern generator generates a plurality of reference patterns RA. A first pattern matching angle detector compares the binary pattern BI with each of the plurality of reference patterns RA, to output the angle of the reference pattern RA which matches with the binary pattern BI as angle information PA. A detected isolation point remover 4 outputs angle signal AN when the angle information PA has continuity.

Abstract: This invention is to enable, at low cost, image display with little line flicker based on an interlaced image signal and satisfactory movie display characteristics. The first de-interlace mode in which interlaced scanning line signals in the consecutive odd- and even-numbered fields are received by storage means, and the scanning line signals in the consecutive odd- and even-numbered fields are alternately read out to perform de-interlacing, and the second de-interlace mode in which scanning line signals in the odd- or even-numbered field are read out in units of fields and magnified in the vertical direction to perform de-interlacing are prepared. The scanning line signals are compared between the fields to determine whether the signal is a movie or a still image. When it is determined that the signal is a still image, the signal is displayed on a display device using a non-interlaced signal obtained in the first de-interlace mode.

Abstract: In an address generator, a spatial position after scan line interpolation necessary for scan line conversion, that is, an address, is generated from a synchronous signal and an enlargement ratio for setting a vertical enlargement ratio. A memory control unit generates a memory control signal for the read/write control of an FIFO memory, field memories, and one-line delay memories for scan line conversion so as to send line data necessary for resolution conversion to multipliers provided in the final stage. Further, in a coefficient generator, a coefficient to be sent to the multipliers is generated based on the signal output from the address generator. In the multipliers, sequentially scan converted signals are multiplied by coefficients, and the outputs of the multipliers are added together in an adder.

Abstract: A 525i (interlace) signal can be converted into a 1050i signal or a 525p (progressive) signal. A calculating circuit generates pixels of an output picture signal with a linear estimation expression of predictive taps received from a tap selecting circuit and a coefficient received from a coefficient memory. The coefficient memory stores coefficients pre-obtained for individual classes. A class is determined by combining a spatial class corresponding to spatial class taps received from a tap selecting circuit and motion class taps received from a tap selecting circuit. A line sequential converting circuit converts a scanning line structure of an output signal of the calculating circuit 34 and obtains an output picture signal. The output picture signal is designated with a conversion method selection signal. Information corresponding to the selection signal is loaded from an information memory bank to the coefficient memory and registers.

Abstract: A versatile video transformation device and adaptive image processing methodology thereof to digitally scan convert, that is, reformat TV raster scan video and particularly high definition (HD) and/or digital DTV (particularly those for example in 1920×1080i or 1280×720p format) video data and associated synchronizing signals, for the purpose of making present standard television sets compatible at low cost with the latest advancements in free HD whilst allowing a multitude of other DTV programs and ancillary data to fill to a greater extent the remaining channel allocations by FCC to TV broadcasters.

Abstract: A 525i (interlace) signal can be converted into a 1050i signal or a 525p (progressive) signal. A calculating circuit generates pixels of an output picture signal with a linear estimation expression of predictive taps received from a tap selecting circuit and a coefficient received from a coefficient memory. The coefficient memory stores coefficients pre-obtained for individual classes. A class is determined by combining a spatial class corresponding to spatial class taps received from a tap selecting circuit and motion class taps received from a tap selecting circuit. A line sequential converting circuit converts a scanning line structure of an output signal of the calculating circuit 34 and obtains an output picture signal. The output picture signal is designated with a conversion method selection signal. Information corresponding to the selection signal is loaded from an information memory bank to the coefficient memory and registers.

Abstract: A picture information converting apparatus for generating an output picture signal with a different scanning line structure from an input picture signal is disclosed, that comprises a first picture data selecting means for selecting adjacent pixels with a predetermined relation of positions to a plurality of considered points with a different relation of positions to scanning lines of the input picture signal, a spatial class detecting means for detecting a pattern of a level distribution from picture data selected by said first picture data selecting means and determining spacial class values that represent spatial classes of the considered points corresponding to the detected pattern, a second picture data selecting means for selecting the considered points and adjacent pixels with the predetermined relation of positions to the considered points from the input picture signal, a calculating process means for performing a calculating process for predicting and generating pixels at positions with a predetermin

Abstract: A sampling system includes an input terminal for receiving a data signal having a signal component and possibly a noise component. A sampler samples the data signal at a sample rate set in responsive to a control signal. A noise detector detects the presence of a noise component, and if a noise component is detected, generates the control signal conditioning the sampler to sample the data signal at a first sample rate satisfying the Nyquist criterion for the data signal including the noise component, and otherwise generating the control signal conditioning the sampler to sample the data signal at a second data rate satisfying the Nyquist criterion for the data signal including only the signal component.

Abstract: A display apparatus capable of receiving and displaying video signals which differ in scanning frequencies or resolutions. The display apparatus includes an input section for receiving at least one video signal and a conversion unit for converting at least one of the frequency and resolution of the at least one received video signal so as to be within predetermined higher ranges thereof. A display unit enables display of the converted received at least one video signal.

Abstract: This invention relates to a video signal converter, a conversion method of video signal, respectively suitable to be applied when a video signal according to National Television System Committee (NTSC) is illustratively converted to a video signal corresponding to an extended graphics array (XGA), an image display unit using the converter and conversion method, and a television receiver. A signal in each field of a video signal SNT according to NTSC in which the number of lines is 252.5 (effective line number is 240) is converted to a signal in each frame of a video signal SXG corresponding to XGA in which the number of lines is 840 (effective line number is 768). A video signal converter is composed of an image adaptive double-speed conversion circuit for converting a video signal SNT to a video signal S2N according to an interlaced scanning method in which the number of lines is doubled and an interpolation circuit for converting the video signal S2N to a video signal SXG.

Abstract: Disclosed is an image processing apparatus 10D for processing image data that composes a dynamic image, wherein pixels are thinned for each frame with respect to the pixels of the respective frames that compose a dynamic image, in such a manner that they become the chessboard-like lattice format in both directions of the spatial direction and the temporal direction, so that the quantity of information can be reduced, maintaining the resolutions of horizontal, vertical and oblique directions of the dynamic image.

Abstract: A system and method for enhancing resolution in a video image includes acquiring a relatively low resolution video signal and applying a peaking function and analyzing the peaked signal to identify potential edges. The low resolution signal is then upconverted to a higher resolution format. Actual edges in the image are detected and linked in the higher resolution format, and a luminance transition improvement function is applied to the edges to sharpen the image. Analysis of the image while at low resolution reduces computation time, yet still produces a high quality output image.

Abstract: An apparatus converts an input video signal having a first format into an output video signal having a second format. A formatter receives the first video signal and divides each field or frame into an active video top and bottom half. Two format converters receive and process the two halves of the active video images from the formatter and provide respective halves of the active video image for rejoining into the second format. A demultiplexer receives the two halves of the active video images from the two format converters and combines the active video upper and active video lower halves of the fields or frames into the output video signal having a second format.

Abstract: Systems for adaptively deinterlacing interlaced video to generate a progressive frame on a per pixel basis. Two consecutive fields of interlaced video are converted into a frame of progressive video. One of the fields is replicated to generate half the lines in the progressive frame. Each of the pixels in the other half of the progressive frame are generated pixel-by-pixel. For a given output position of the pixel in the other half of the progressive frame, a correlation is estimated between the corresponding pixel in the non-replicated field and at least one vertically adjacent pixel of the replicated field, and optionally one or more vertically adjacent pixels in the non-replicated fields. A value is then assigned to the output pixel that corresponds to the output position, the value depending on the correlation.

Abstract: A method and circuit for converting the image format of three-dimensional electronic images produced with line polarization wherein, given that television pictures are transmitted with different line resolution and displayed on devices whose line resolution does not coincide with the line resolution of the transmitted images, lines are not only respectively inserted or skipped, but also transposed with one another.

Abstract: One disclosed embodiment comprises a vertical scaler receiving a first number of video lines at a first frequency. The vertical scaler outputs a second number of video lines at the first frequency. A FIFO has as an input from the vertical scaler the second number of video lines at the first frequency. The FIFO outputs the second number of video lines at a second frequency. Another disclosed embodiment further comprises a modulator/timing generator having as an input from the FIFO the second number of video lines at the second frequency. The second number of video lines can be in a first video format. The first video format can be a high resolution video format. The modulator/timing generator converts the second number of video lines in the first video format into a second video format. The second video format can be a low resolution video format.

Abstract: A home theater comprises a video processing sub-system and a PC capable of controlling the sub-system. The sub-system has a de-interlacer/line doubler and the PC has a graphics controller with scaling capability. The combination of the line doubler and the scaler is made to function as a line quadrupler.

Abstract: A field-by-field vertical inverter selectively performs a vertical inverting process for an input picture signal for each field as a function of the relationship between the type of the input picture signal and the type of the output picture signal. A picture extractor extracts picture data at a predetermined position of the vertical inverting processed input picture signal. A class code is generated as a function of the extracted picture data, and this extracted picture data is used with conversion information data that is stored for each class code to generate the output picture signal.

Abstract: When a video signal is double-speed processed by the first device, a slight vertical deflection process is performed for redundant similar scan lines by the second device, and any slight deflection in the second device is controlled by the first device to enable setting so as to display images with excellent resolution. The first device generates a discrimination signal to designate interlaced scanning and flag a need for vertical scan-line deflection, and such signal is provided to the second device such that the second device can always appropriately determine need for vertical scan-line deflection. Through monitoring for the discrimination signal, an image display apparatus can prevent vertical resolution from deteriorating when video signals possibly requiring vertical line-shifting are inputted from an external source, and can prevent vertical resolution from deteriorating when displaying images of video signals having different systems within different areas on the same screen.

Abstract: A video decoder decimates an input image to produce a decimated output image. The video decoder uses approximately every line of pixels in the input image to compute the lines of pixels in the decimated image. The video decoder includes a vertical decimation filter that computes an average, and preferably a weighted average, of luminance (luma) values associated with pixels from each of four lines in the input image. The decimation filter preferably computes a weighted average of lumas from four adjacent lines of pixels from the input image which may represent a frame or a field of video data. The weighted average preferably uses coefficients that weight each luma in the calculation differently. After calculating all of the luma values for a particular line of the decimated image, the line number associated with the first of the four adjacent lines is incremented by four (in a field-based system) to determine the initial line number for calculating the next line in the decimated image.

Abstract: In a data transmission apparatus for transmitting digital video and audio data, a block forming circuit forms a plurality of data blocks of transmission data composed of at least one of digital video data, digital audio data, and digital auxiliary data related to the digital video data and the digital audio data. Thereafter, a grouping circuit groups a plurality of data blocks outputted from the block forming circuit so as to form transmission group data of one transmission unit block having a time length of approximately one three-hundredth second, and then transmits the transmission group data. Further, a classifying circuit preferably classifies the transmission group data into a plurality of sections, by adding section identification data to each transmission group data.

Abstract: A picture size conversion method (and device) is provided to avoid deterioration of picture display quality such as a blur and distortion, especially with respect to motion pictures which are displayed in accordance with an interlaced display method. Herein, a size conversion table storing display flags is created in accordance with a reduction ratio, wherein each of the display flags represents a decision whether to allow display with respect to each of horizontal lines. At first, the method discriminates whether the reduction ratio (R) belongs to a first range (0<R<½) or a second range (½≦R<1), while the method also discriminates whether each of horizontal lines belongs to an even-numbered field or an odd-numbered field within one frame.

Abstract: A picture reducing circuit 1 reduces a supplied original picture. An upper hierarchical level picture memory 2 stores an input upper hierarchical level picture. A predictive tap obtaining circuit 3 extracts a predictive tap from the upper hierarchical level picture stored in the upper hierarchical level picture memory 2 and outputs the extracted predictive tap to a predictive coefficient calculating circuit 4, a pixel value updating circuit 5, and a mapping circuit 6. The predictive coefficient calculating circuit 4 generates an observation equation using the predictive tap as student data and pixels of an original picture corresponding thereto as teacher data, solves the observation equation, and generates predictive coefficients.

Abstract: The invention is a method and apparatus for processing image data stored in a memory. A read interface circuit is coupled to the memory to transfer a patch of the image data from the memory to a buffer. A scale filter is coupled to the read interface circuit to scale the image data in the patch from the buffer. A receive circuit is coupled to the scale filter to re-organize the scaled image data.

Abstract: A display for receiving video signals of a plurality of deflection frequencies including a conversion unit which is responsive to at least one of a horizontal frequency and a vertical frequency of an input video signal below at least one of at least one predetermined horizontal frequency within a first horizontal frequency range and at least one predetermined vertical frequency within a first vertical frequency range for converting the input video signal to have at least one of a converted horizontal frequency within the first horizontal frequency range and a converted vertical frequency within the first vertical frequency range. The conversion unit is further responsive to the at least one of the horizontal frequency and the vertical frequency of the input video signal being within at least one of the first horizontal frequency range and the first vertical frequency range for directly supplying the input video signal to the output of the conversion unit.

Abstract: Input image information from an input terminal is stored in a line buffer for several lines and smoothed, and then an interpolation value for plural pixels is obtained by an interpolation unit. Further, maximum and minimum values are detected from information of a noticeable pixel and its peripheral pixels. An arithmetic unit performs calculation by using these detected values (interpolation value, maximum value and minimum value) and a predetermined value to obtain a high-resolution output value h(k). By this calculation, a jagless clear high-resolution image can be obtained even in a case where a contrast of inputted low-resolution information is deteriorated.

Abstract: A video signal processing apparatus processes input video signals. A video signal source supplies the input video signals carrying at least a first video signal that is an interlaced signal having 480 effective scanning lines and a second video signal that is an interlaced signal having 1080 effective scanning lines. A video signal processor converts at least the first and the second video signals into a third video signal that is a progressive signal having 1440 effective scanning lines, thus outputting the third video signal. The output third video signal may be converted into a fourth video signal that is an interlaced signal by a progressive-to-interlace converter, thus outputting the fourth video signal.

Abstract: A first interlaced video signal of a first number of scanning lines is converted into a second interlaced video signal of a second number of scanning lines. The first and second numbers are different from each other. The first interlaced video signal is converted into a first progressive video signal of the first number of scanning lines by interpolating the first interlaced video signal with scanning lines which have been decimated from the first interlaced video signal. The first number of scanning lines of the first progressive video signal is converted into the second number of scanning lines by re-sampling, to generate a second progressive video signal of the second number of scanning lines. The second progressive video signal is then converted into the second interlaced video signal by decimating the second number of scanning lines of the second progressive video signal.

Abstract: A format conversion apparatus for a digital TV includes a block division and control signal generating part for dividing an input image into a plurality of blocks according to an input image size data and an output image size data. A format conversion coefficient generating part generates a format conversion coefficient for converting formats per block according to a control signal output from the block division and control signal generating part. A synchronizing signal generating part generates vertical and horizontal synchronizing signals per block according to a control signal output from the block division and control signal generating part. A format conversion part performs format conversion of image input per block according to the format conversion coefficient and the vertical and horizontal synchronizing signals.

Abstract: There is provided a low-cost scanning line converting circuit being capable of properly converting the number of scanning lines for a video signal at various conversion ratios. Under the control of a write control signal generating circuit, an original video signal is written, on a scanning-line basis, in individual line memories. A write operation is performed to each of the line memories based on a clock and a horizontal synchronizing signal on the input side, while a read operation is performed to each of the line memories based on a clock and a horizontal synchronizing signal on the output side. A selecting circuit selects, based on a line select signal, at least one from scanning line signals stored in the individual line memories necessary to generate a post-conversion scanning line signal and outputting the selected scanning line signal.

Abstract: For an upper real scan signal that is above and adjacent to an interpolation scan line, a lower interpolation element Sd is generated based on the upper real scan signal and a plurality of real scan signals that are vertically continuous. For a lower real scan signal that is below and adjacent to an interpolation scan line, an upper interpolation element Su is generated based on the lower real scan signal and a plurality of real scan signals that are vertically continuous. Inclination information CNT for an image is detected based on at least two real scan signals, including the upper and lower real scan signals. The levels of the upper interpolation element Su and the lower interpolation element Sd are adjusted in accordance with the inclination information CNT, and the obtained first interpolation element and second interpolation element are added together.

Abstract: A transforming device for transforming computer graphics signals to television signals is provided. The transforming device includes a scaled-down line generating unit that receives the computer vertical line and generates the scaled-down vertical line, a controller that receives the scaled-down vertical line, and a scaled-down buffer that stores the scaled-down vertical line or the value of the scaled-down vertical line performed by the weighted-averages method. The content of the scaled-down buffer is transmitted to a weighted-averages operation unit, and then it is performed by the weighted-averages method with the next scaled-down vertical line. When a TV line is generated, it is the output of the transforming device. The present invention has the advantage of reducing the needed buffers in the transforming process and thereby reducing the cost.

Abstract: A matrix display device comprises a matrix display (10) with picture elements (18) arranged in a number of display lines (R). A driving circuit (3) supplies picture signals (Ds) to the picture elements (18) dependent on a video signal (V) which comprises, in a field (Fp), a number of video lines which is lower than the number of display lines (R). A line period (Tl) is defined as the duration of one of the video lines. To display video information on all display lines (R) regularly, after a number of line periods (Tl), more than one display line (R) is selected within one line period (Tl) to write video information to more than one display line (R). Therefore, a timing circuit (21) receives video timing information (S) to determine consecutive and non-overlapping select periods (Tr), each select period (Tr) completely occurring within a line period (Tl). In at least one of the line periods (Tl), at least two select periods (Tr) occur.

Abstract: A number of methods to display interlaced video on non-interlaced monitor are disclosed. One method is to display all of the incoming fields but one at a time, and correcting for the positional offset of one field relative to another in the interlaced data. An important aspect of the present invention is the correction of the positional offset of the two interlaced video fields. There are two ways presented to deal with the vertical offset of the two fields in accordance with the present invention. The first way is that the two fields can be displayed at different positions on the display using a non-interlaced display. The second way is that the video data can be altered to correct the positional offset between the fields. Another method of the present invention is to lock the frame rate of the output video to the incoming field rate or a multiple of the incoming field rate, or to certain sub-multiples of the incoming field rate.

Abstract: A delay register section 31 holds SD pixels of a luminance signal and a classification section 33 decides a class, reads a coefficient corresponding to the decision result from a coefficient RAM section 40, and outputs the coefficient to a product-sum section 38. The product-sum section 38 captures the pixel data for 17 taps from the delay register section 31, converts the pixel data into seven taps, and outputs them to the product-sum section 38. The product-sum section 38 performs the product-sum operation of pixel data and coefficients and outputs the operation result as HD pixels. An interpolation pixel operation section 42 applies a simple interpolation processing different from the case of a luminance signal to the pixel data of a color signal component to generate HD pixels of a color signal. Thus, downsizing and cost reducing can be realized.

Abstract: In each conversion blocks 10, 20 and 30, pixels adjacent to a subject pixel data are selected in the class tap construction section from SD signals, the detection of level distribution pattern of the pixel data is performed in the class categorization section and a class is determined based on the detected pattern. The pixel data of the subject pixel is generated by reading the prediction coefficient corresponding to classes from the prediction coefficient memory and performing prediction operation in the sum of products operation section using pixel data of the selected pixel selected by the prediction tap construction section and the prediction tap selection section and the read prediction coefficient. According to the selection of the switching sections 41 and 42, a HD signal having a high resolution is obtained and a signal whose tone level of a SD signal is corrected is obtained.

Abstract: A line doubling processing system has an input signal switching output section for receiving sequential input fields and for outputting, based on the sequential input fields, a plurality of fields obtained from the same image, and a line doubling device for generating one line-doubled field using the plurality of fields that are output from the input signal switching output section.

Abstract: This invention relates to a video signal processing circuit for easily simultaneously performing conversion of the number of lines and format conversion with a simple construction and an image pickup apparatus such as CCD using the circuit. A signal in a 4:2:2 format is supplied to a linear interpolating unit. Input luminance signals and input color difference signals of one line are written into line memories and the input luminance signals and the input color difference signals of the next one line are written into other memories. Similarly, signals are alternately written. The input luminance signal is read twice from the above memories in a period of writing signals of one line. The obtained signals are multiplied by coefficients for linear interpolation, respectively, and the resultant signals are added, thereby generating a luminance signal to be outputted.

Abstract: A signal processing apparatus and method up or down convert an interlace signal with a high degree of accuracy. The frequency of a write system clock supplied from a PLL circuit is divided by N by a dividing circuit and then multiplied by M by a multiplying circuit to produce a readout system clock. An interpolation circuit writes a video signal into a frame memory in synchronism with the write system clock from the PLL circuit, and reads out the video signal in synchronism with the readout system clock from the multiplying circuit.

Abstract: A system which can perform video communications via terminals which can send and receive video and audio signals should convert a video signal format set in each terminal into a common intermediate format (CIF) to then perform encoding and decoding operations. A video format converting apparatus can reduce the size of line memories which are used for video format conversion during converting an image picked up by a charge coupled device (CCD) camera into a CIF image. Thus, the number of line memories used for video format conversion of images can be reduced, thereby providing an effect capable of reducing the size of an integrated circuit of the line memories. The video format converting apparatus can be also applied to convert an NTSC signal as well as the CCD image into the CIF image.

Abstract: An image display device includes a display panel having predetermined numbers of pixels defined in horizontal and vertical directions, respectively, and an interpolated-data generation circuit whereby an expanded image data is produced in such a manner that when the number of pixels in the horizontal direction of the display panel is greater than the number of pixels in the horizontal direction of a given image signal, the interpolated-data generation circuit directly stores a plurality of image data A, B, C, D, E of the original image signal along one horizontal line at data storage locations closest to the original locations, and data at data storage locations remaining after storing all original data are given the results X, Y, and Z obtained by calculation from two original image data at locations adjacent to the respective remaining data storage locations thereby expanding the original image signal to have a resolution well matched to the resolution of the display panel without causing a reduction in con

Abstract: The invention provides a method for filtering motion effects from a de-interlaced image and an apparatus associated therewith. The method assumes that the de-interlaced image is formed by a combination of a first interlaced image and a second interlaced image. A first step in the method is to interpolate an interpolated line between two lines in a region of the first interlaced image. A variance value is then determined between the interpolated line and a corresponding line in a corresponding region of the second interlaced image. A threshold value will have been predetermined in the system and the variance value is compared against that threshold value. If the variance value is less than the threshold value then the correlation is strong and the corresponding line is displayed in the de-interlaced image. Otherwise if the variance value exceeds the threshold value then the interpolated line is displayed. This process is repeated for each pixel until the entire image is displayed.

Abstract: A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.

Abstract: A method for converting frame data at a slower rate into field data at a faster rate in a video decoder comprises determining a basic field repetition rate such that a field is repeated an integer number of times in a frame period, calculating a ratio differential of the repetition rate by subtracting from the speed-up ratio of the faster to the slower rate, the ratio of the fields per frame period to the slower rate, comparing the ratio differential with the differential of the field repetition rate and adding or subtracting extra fields when the two are substantially at variance.

Abstract: The present invention is a method and apparatus for converting scan rates of image data in a memory. A buffer stores a source image data. A scaling filter is coupled to the buffer to scale the source image data.

Abstract: An apparatus for converting a first picture comprising pixels into a second picture comprising pixels is provided. The second picture is converted by executing on the first picture an adaptive process that determines prediction values of the second picture by using a number of pixel values of the first picture as prediction taps and a number of prediction coefficients that are adapted to the first picture. The apparatus comprises a prediction taps forming circuit for forming a number of prediction taps from the first picture and a picture obtained by the adaptive process and an executing circuit for executing the adaptive process by using the formed number of prediction taps and a number of prediction coefficients that are adapted to the prediction taps. The apparatus further comprises a class taps forming circuit for forming a number of class taps from the first picture and the picture obtained by the adaptive process.

Abstract: A scanning line number converting apparatus using a linear array type multi-parallel processor constructed by an input image data storing unit, a plurality of element processors which has a data memory section and an ALU array section and are provided in parallel and operate in accordance with the same command for a plurality of data, and an output image data storing unit, wherein one of the element processors is used as an FIFO and image data is transferred to the other element processors, and an interpolation arithmetic operation for a scanning line number conversion is executed by the element processor on the transfer destination side, so that the scanning line number conversion can be performed without using any image memory and memory controller.

Abstract: A picture processing apparatus for picture-in-picture applications where the number of pixels n in the horizontal direction of an original picture, the number of pixels m in the vertical direction thereof, the number of pixels N in the horizontal direction of the converted picture, and the number of pixels M in the vertical direction thereof are supplied to a dividing device. Thus, ratios A=N/n and B=M/m are obtained. The inverse number 1/A of the value A is cumulated by circuits. An address generating circuit generates addresses at four points for calculating a density value a of a converted pixel corresponding to the integer part of a cumulated value &Sgr;(1/A). These addresses are supplied to memories. The pixel data at the four points that are read from the memories are supplied to respective multiplying devices. The decimal part of the value &Sgr;(1/A) is supplied as an interpolating coefficient p to a multiplying device. A coefficient (1−q) is supplied to a multiplying device.

Abstract: A liquid crystal display system which can accept display data having a resolution different from that of a screen for the liquid crystal display and display the display data. For example, a CPU outputs display data of 1120×780 dots and a liquid crystal panel has a 1024×768-dot resolution which is smaller than the display data resolution. The display screen of the liquid crystal panel comprises a linear arrangement of pixels. A data conversion section generates display data for a new horizontal or vertical line based on display data for two horizontal or vertical lines contiguous to each other and repeats replacement of display data of the two lines with the display data of the one line for reducing the number of horizontal lines of one screen and the number of dots of one line so as to match the resolution of the display data output by the CPU with the liquid crystal display.

Abstract: A classified adaptive spatio-temporal creation process is utilized to translate data from one format to another. This process creates new pixels by applying a filter selected on an output pixel by pixel basis which has been adaptively chosen from an application-specific set of three-dimensional filters. In one embodiment, a standard orientation is chosen, which is defined according to each output data position. Input data is flipped to align the output data position with the output position of the standard orientation. A classification is performed using the flipped input data and an appropriate filter is selected according to the classification. The filter is then executed to generate the value of the output data point.