Abstract: A signal processing apparatus and method for up or down conversion of an interlace signal with a high degree of accuracy. The frequency of a write system clock supplied from a PLL circuit is divided by N by a dividing circuit and then multiplied by M by a multiplying circuit to produce a readout system clock. An interpolation circuit writes a video signal into a frame memory in synchronism with the write system clock from the PLL circuit, and reads out the video signal in synchronism with the readout system clock from the multiplying circuit.

Abstract: Video data of a field necessary for I/P conversion and scanning line conversion is stored in a field memory part (7), vertical frequency conversion is performed by a memory control processing part (2), I/P conversion is performed by an I/P conversion processing part (3), scanning line conversion is performed by a scanning line conversion part (4) and horizontal pixel conversion is performed by a horizontal pixel conversion processing part (5) with the data stored in the field memory part, and a synchronous processing part (6) supplies a prescribed clock, a horizontal synchronizing signal and a vertical synchronizing signal to each block. A single system performs vertical frequency conversion, I/P conversion, scanning line conversion and horizontal pixel conversion.

Abstract: An adaptive digital image processor precedes an MPEG2 encoder. The processor receives a high definition video signal intended for broadcast or storage, and adaptively low-pass filters the signal. The signal is subjected to low-pass two-dimensional filtering to eliminate encoding artifacts and related noise. The video signal is then horizontally down-sampled to create a lower resolution hybrid signal. A receiver decodes and decompresses the hybrid signal. The hybrid signal is upsampled to its original resolution using existing hardware and software with a software modification.

Abstract: A method of processing video data to detect field characteristics of the data, including processing pixel values of the data to obtain differences between the values of two successive fields of the data, processing the difference values to detect interlace patterns in the successive fields, determining if the successive fields belong to a progressive frame based on detection of the interlace patterns, and generating a progressive frame output indicating that a progressive frame has been detected. The pixel values of the first field of the successive fields and a subsequent field to the successive fields are processed to obtain further difference values to determine if the subsequent field is a redundant field, when the progressive frame output is generated.

Abstract: Device for converting a video format including a control unit for determining an operation conducted at the present time, recognizing an operation to be conducted at the next time based on the operation conducted at the present time, and providing control signals suitable for the operation to be conducted at the next time, according to an input video format of an input video signal and an output video format of an output video signal desired to provide, and a processing unit for conducting operations required for converting the input video format into the output video format desired to provide in response to the control signals form the control unit, thereby requiring very simple modification of hardware for being adoptive to an addition of a new format and facilitating display of a variety of modes the user requires.

Abstract: A transforming device for transforming computer graphics signals to television signals is provided. The transforming device includes a scaled-down line generating unit that receives the computer vertical line and generates the scaled-down vertical line, a controller that receives the scaled-down vertical line, and a scaled-down buffer that stores the scaled-down vertical line or the value of the scaled-down vertical line performed by the weighted-averages method. The content of the scaled-down buffer is transmitted to a weighted-averages operation unit, and then it is performed by the weighted-averages method with the next scaled-down vertical line. When a TV line is generated, it is the output of the transforming device. The present invention has the advantage of reducing the needed buffers in the transforming process and thereby reducing the cost.

Abstract: A method and apparatus for detecting and correcting motion artifacts in interlaced video signal converted for progressive video display. A correction is applied where interlaced video material is determined to originate from film source, thereby having been converted to video using a process known as 3-2 pulldown. Where the video material is not a result of the 3-2 pulldown process, a check is made for the presence of “pixel motion” so that corrections may be applied to smooth out the pixel motion. To determine 3-2 pulldown or field motion, a video field is compared to the field prior to the previous field to generate field error. Field errors are generated for five consecutive fields and a local minimum error repeated every five fields indicate the origination of the video material from film source using the 3-2 pulldown process.

Abstract: An apparatus converts an input video signal having a first format into an output video signal having a second format. A formatter receives the first video signal and divides each field or frame into an active video top and bottom half. Two format converters receive and process the two halves of the active video images from the formatter and provide respective halves of the active video image for rejoining into the second format. A demultiplexer receives the two halves of the active video images from the two format converters and combines the active video upper and active video lower halves of the fields or frames into the output video signal having a second format.

Abstract: A method of optimizing the display of an up-converted interlaced video frame signal from a received progressive video frame signal (11) comprises the steps of receiving a progressive video frame signal, decoding (12) the progressive video frame signal using an interpolation function (18) to provide an interpolated interlaced video signal, deinterlacing (14) the interpolated interlaced video signal, and de-interpolating (16) the deinterlaced interpolated interlaced video signal to provide an optimized progressive video frame signal (17).

Abstract: In an electro-optical device including a scanning line driving circuit, the scanning line driving circuit includes a transfer direction control circuit for controlling the direction of transfer of a start pulse, a shift register for shifting the start pulse, supplied by the transfer direction control circuit, in response to a clock signal, and an output selection circuit for selecting the output signal of the shift register in accordance with a first enable signal and a second enable signal. A decimation process and a stretching process are performed by controlling the first enable signal and the second enable signal in accordance with the video line count of an input video signal.

Abstract: This is a unique method to convert analog and/or standard digital video to broadcast quality digital video. The process uses a “frame justification, then clone” horizontal and vertical cloning process converting analog and/or standard digital video to broadcast quality high definition video.

Abstract: There is provided a video signal processing apparatus that makes it possible to realize a favorable display of pictures by increasing the detection accuracy of the video source of an input video signal and by using an appropriate scanning method for an output video signal in accordance with the determined type of video source.

Abstract: In an image signal converter (ICp1) converting a component video signal (Scv) of an interlaced scanning format for image display on a display device for an image signal of a progressive scanning format (Scv, p) for image display on the display device, an up-converter (11) converts the component video signal (Scv) of the interlaced scanning format into the one of the progressive scanning format. A scanning format determination part (4, 14, 15) determines based on a luminance signal (Y) included in the component video signal (Scv1, Scv2) whether the component video signal (Scv1, Scv2) is of the interlaced or progressive scanning format. Based on the determination result of the scanning format determination part (15), an output destination selector (3B, 15A) selects an output destination of the component video signal (Scv1, Scv2).

Abstract: A video decoder compliant with the Advanced Television Systems Standard (ATSC) includes circuitry which decodes an ATSC encoded image and employs a downconversion process to produce a standard definition video signal. The video decoder includes a frequency-domain filter to reduce the resolution of the ATSC encoded signal. The video decoder downconversion system also includes a formatting section having vertical and horizontal filters, as well as resampling processing, to format the decoded and downconverted video image for a particular display and aspect ratio. The decoder senses the display format of the encoded video signal and changes the processing provided by the decoder to produce a standard definition output signal regardless of the display format of the encoded input signal. The system also includes a format converter which may be programmed to use a plurality of methods to convert the aspect ratio of the input signal for display on a display device having a different aspect ratio.

Abstract: Displaying a subject image on a browser in accordance with the aspect ratio of the subject image, with reduced scan line interference at a time exposure, as well as transmitting a high-quality image with easy compression processing.

Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

Abstract: The invention relates to a method and apparatus for vertically scaling a video picture comprising receiving and storing lines of a video frame of a video picture, reading lines of the frame into linestores, applying the lines to a vertical filter and providing an output video line as a function of the lines. Reading the lines of the frame into linestores comprises reading M lines of each successive 2nd line of the frame lines into the linestores. Following generation of the output video line, a further X lines are read from the framestore into the linestores to provide a further set of M lines in the linestores. The M lines are applied to the vertical filter to provide a further output video line as a function of the lines.

Abstract: Standard definition video can be upconverted to high-definition video without degrading the appearance of edges, lines and other visual transitions in the image with a diagonal geometry. Each horizontal scan line of the video is monitored to identify the location of such visual transitions. The transitions are then matched in successive scan lines. Successive scan lines are then morphed, e.g., shifted forward or backward to move the transition in each line toward an average position for the transition as located in the two successive scan lines. The successive morphed lines are then added to produce a single interpolated line that is interlaced between its parent lines in a resulting high-definition video signal.

Abstract: First and second line memories alternately store input video signals for every scanning line. The video signals stored in the line memories are read by a predetermined number of times in accordance with a signal system of the input video signals. A calculator calculates average values among the video signals read from the line memories. A selector circuit sequentially selects the video signals read from the first and second line memories when the input video signals are based on an interlace system, and sequentially selects the video signals read from the first and second line memories and the averaged video signals when the input video signals are based on a progressive scan system. The selected signals are supplied to a liquid crystal display apparatus.

Abstract: An apparatus for converting image format and methods thereof in a video signal processing system.

Abstract: An LCD apparatus has a control circuit 40 which makes a timing of the rear edges of scanning pulses provided to predetermined scanning lines coincide with the time when the display potential is renewed, wherein each of the predetermined scanning lines corresponds to an addition of a picture line to a picture or a reduction from two picture lines to one picture line on a picture in order to compensate for a difference between the number of scanning lines of the LCD and the number of lines of the picture to be displayed. In the control circuit, a circuit detects cycle times of the vertical and horizontal sync pulses, an MPU determines the reference value REF on the basis of the detected value and count CH of the horizontal sync pulse *HS from a counter, and a circuit generates a signal AE which makes the time when the pulse count CD of pixel clock CLKD from the counter becomes equal to the REF that coincides with the timing of the rear edge of scanning pulse.

Abstract: Video data is processed. A first high definition program stream is received that includes a first high definition video stream component. A first standard definition program stream is derived from the high definition program stream. A second standard definition is received having been derived from the first standard definition program stream. A second high definition program stream is derived from the second standard definition program stream and the first high definition video stream component.

Abstract: When an image is displayed on a display screen having a larger display area than a displayed image, a size of the displayed image is minutely changed cyclically in order to avoid boundary lines to be recognized when a full size image is displayed on the display screen of the display device. Direction of the size change of the displayed image is in the vertical direction or the horizontal direction. In this case additional non-image signal is added to top, bottom, left and/or right of the displayed image.

Abstract: The invention relates to a method for interpolating a pixel from an intermediate line of a first field of a sequence of interlaced fields.

Abstract: Disclosed is a video signal processing apparatus comprising a plurality of line memories to which in sequence input video signal data is written on a line-by-line basis; a timing controller for controlling a timing to write video signal data to the plurality of line memories and a timing to read video signal data from the plurality of line memories; a computation output portion for computing video signal data read from the plurality of line memories and outputting video signal data differing in resolution which is determined by a pixel count in the horizontal direction and a line count in the vertical direction; and a line controller which vary the pixel count in specified lines of video signal data obtained from the computation output portion, depending on a conversion rate of the video signal data resolution.

Abstract: The present invention relates to interpolating a pixel in an image that includes a number of pixels arrayed in matrix-like fashion, to each of which a video information value is assigned, in which method a gradient for the video information value is determined at, at least, a first and a second pixel adjacent to the pixel to be interpolated and, in the formation of the interpolated video information value, a greater weight is accorded to the video information value of the adjacent pixels whose associated gradient is smaller.

Abstract: A system and method for enhancing resolution in a video image includes acquiring a relatively low resolution video signal and applying a peaking function and analyzing the peaked signal to identify potential edges. The low resolution signal is then upconverted to a higher resolution format. Actual edges in the image are detected and linked in the higher resolution format, and a luminance transition improvement function is applied to the edges to sharpen the image. Analysis of the image while at low resolution reduces computation time, yet still produces a high quality output image.

Abstract: The scan conversion apparatus of the present invention comprises a video signal discriminating circuit for discriminating the kind of input video signal based on an interlaced scanning system; a telecine scan conversion circuit for converting input video signal into a video signal based on a progressive scanning system by processing suited for telecine video signal; a scan conversion circuit for converting input video signal into a video signal based on a progressive scanning system suited for signals other than telecine video signal; and a selector which selects and delivers the output from the telecine scan conversion circuit and the output from the scan conversion circuit in accordance with the result of discrimination executed by the video signal discriminating circuit.

Abstract: An image data conversion processing device including an issue unit, plural line storing units and a generating unit for converting to a television signal image data stored in plural kinds of developing formats in a storing unit. The image data comprises plural lines, and the television signal comprises a predetermined number of lines. The issue unit issues a transmission instruction of image data to the storing unit in accordance with a period specified by a ratio of the number of lines the image data to be converted and the line number of the television signal. The plural line storing units cyclically store the image data transmitted from the storing unit line by line on the basis of the transmission instruction of the issue unit.

Abstract: In each conversion blocks 10, 20 and 30, pixels adjacent to a subject pixel data are selected in the class tap construction section from SD signals, the detection of level distribution pattern of the pixel data is performed in the class categorization section and a class is determined based on the detected pattern. The pixel data of the subject pixel is generated by reading the prediction coefficient corresponding to classes from the prediction coefficient memory and performing prediction operation in the sum of products operation section using pixel data of the selected pixel selected by the prediction tap construction section and the prediction tap selection section and the read prediction coefficient. According to the selection of the switching sections 41 and 42, a HD signal having a high resolution is obtained and a signal whose tone level of a SD signal is corrected is obtained.

Abstract: An apparatus for enhancing the resolution of video data in a reduced scale of apparatus, and a video signal processing apparatus for freely setting the number of video data sequences for enhancing the resolution, is created from one horizontal scanning line portion of an incoming video data sequence, without changing the circuit configuration. The resolution enhancement processing apparatus stores every one horizontal line portion of each video data in an incoming video data sequence sequentially in a plurality of memories. A first video data group and a second video data group of horizontal scanning line portion of different scan periods are read repetitively N times within one horizontal scan period. The first video data group and the second video data group are mixed at varying mixing ratios to generate a video data sequence which has the vertical resolution enhanced by a factor of N.

Abstract: A video signal conversion part of a horizontal deflection circuit deletes a prescribed number of horizontal scanning lines from a vertical blanking interval of an input video signal and assigns a time corresponding to the deleted horizontal scanning lines to horizontal blanking intervals of the remaining horizontal scanning lines thereby extending the horizontal blanking interval of each horizontal scanning line and outputting a video signal. A synchronizing signal separation circuit extracts a horizontal synchronizing signal and a vertical synchronizing signal from the video signal output from the video signal conversion part. An output part of the horizontal deflection circuit supplies a sawtooth horizontal deflection current to a horizontal deflection yoke in synchronization with the horizontal synchronizing signal output from the synchronizing signal separation circuit.

Abstract: The present invention relates to an apparatus and method for converting scanning mode.

Abstract: A video format converting apparatus which optionally converts the sizes of input and output videos includes a mode generator for generating a control signal of required data flow and a clock required for format conversion by determining a format conversion structure after receiving format data of input and output videos, a format converter of which input/output data path is controlled to a corresponding operation mode by the control signal, for independently format converting the input video synchronized with the clock in vertical and horizontal directions, and a plurality of multiplexers for providing proper video to the format converter in accordance with the signal of the mode generator. When various kinds of input videos are format converted to various kinds of output videos, it is possible to reduce the capacity of required hardware and the capacity of the memory. Thus, a minimum memory band width is required.

Abstract: Deinterlacing is applied to a composite video image that includes alternating even and odd rows of pixels. The even rows form a first image; the odd rows, a second image; these are recorded at different times, introducing a possibility of motion artifact. A first average horizontal intensity difference is computed between the first image and the second image. The first image is offset by one pixel in each horizontal direction to form a horizontally offset image, and another average horizontal intensity difference is computed. A minimum average intensity difference is determined from a comparison of the average horizontal intensity differences. The first image is shifted in a horizontal direction determined to achieve the minimum average horizontal intensity difference, and the horizontally shifted first image is combined with the second image to form an improved composite image. An analogous series of steps is carried out in a vertical direction.

Abstract: An apparatus and a method for format converting a video are provided, in which an input video is format converted in a horizontal direction according to a horizontal output size to store in a line memory and the image stored in the line memory is format converted in a vertical direction according to a vertical output size, such that the amount of line memory required for converting various kinds of videos including the high resolution video to videos of the NTSC or the standard screen quality video are minimized. An input video is format converted in the horizontal direction and a plurality of the divided lines are temporarily format converted by using a single horizontal format converting unit, so that the required hardware becomes reduced.

Abstract: A video signal processing device of the invention includes an IP conversion means for converting an interlaced video signal that has been input into a progressive video signal and outputting it, a synthesis means for synthesizing the progressive video signal and a sub-picture or OSD that has been input and outputting the result as a progressive video signal, and a PI conversion means for converting the progressive video signal into an interlaced video signal and outputting it. The progressive video signal and the interlaced video signal are both output. Thus, the picture quality of synthetic sub-pictures or OSDs is not deteriorated and the progressive video signal and the interlaced video signal can be output simultaneously.

Abstract: In a video-processing unit comprising a processing means, memory means and a memory manager, the processing means comprises an N-tap digital filter for performing scaling operations on a sampled image present in the memory means. The N-tap digital filter further comprises a predetermined first number of line memories. Each line memory is arranged to contain a predetermined second number of samples of selected lines of the sampled image in the memory means. The second number of samples is smaller than the total number of samples of each line of the sampled image.

Abstract: The invention relates to an information signal processor etc. that are well suitable for use in conversion of, for example, an SD signal into an HD signal. The pixel data set of a tap corresponding to an objective position in the HD signal is extracted selectively from the SD signal. Class CL to which pixel data set of the objective position belongs is then obtained using the pixel data set of the tap. A coefficient production circuit (136) produces coefficient data sets Wi for each class based on coefficient seed data sets for each class and values of picture quality adjusting parameters h and v obtained by user operation.

Abstract: The invention relates to an information signal processor, etc. that are well suitable for use in conversion of, for example, an SD signal into an HD signal. The pixel data sets of a tap corresponding to an objective position in the HD signal are extracted selectively from the SD signal. Class CL to which pixel data set of the objective position belongs is then obtained using the pixel data sets of the tap. A coefficient production circuit (136) produces coefficient data sets Wi for each class based on coefficient seed data sets for each class and values of picture quality adjusting parameters, h and v obtained by user operation.

Abstract: An image display device includes a display panel having predetermined numbers of pixels defined in horizontal and vertical directions, respectively, and an interpolated-data generation circuit whereby an expanded image data is produced in such a manner that when the number of pixels in the horizontal direction of the display panel is greater than the number of pixels in the horizontal direction of a given image signal, the interpolated-data generation circuit directly stores a plurality of image data A, B, C, D, E of the original image signal along one horizontal line at data storage locations closest to the original locations, and data at data storage locations remaining after storing all original data are given the results X, Y, and Z obtained by calculation from two original image data at locations adjacent to the respective remaining data storage locations thereby expanding the original image signal to have a resolution well matched to the resolution of the display panel without causing a reduction in con

Abstract: A home theater comprises a video processing sub-system and a PC capable of controlling the sub-system. The sub-system has a de-interlacer/line doubler and the PC has a graphics controller with scaling capability. The combination of the line doubler and the scaler is made to function as a line quadrupler.

Abstract: In a regulation of a total image quality for an encoded picture, parameter conversion data which define applicable coding bit rates and coding frame rates for each image format are previously stored in a storage 13. An image quality regulating parameter is input through a parameter input section 11 and is used as a key in an image quality regulator 12 to make a reference to the parameter conversion data in the storage 13 in order to determine a coding frame rate and an image format. By delivering the coding frame rate and the image format to picture encoding means, a regulation of a total image quality is achieved through a single operation without independently operating two parameters, the image format and the frame rate.

Abstract: Standard definition video can be upconverted to high-definition video without degrading the appearance of edges, lines and other visual transitions in the image with a diagonal geometry. Each horizontal scan line of the video is monitored to identify the location of such visual transitions. The transitions are then matched in successive scan lines. Successive scan lines are then morphed, e.g., shifted forward or backward to move the transition in each line toward an average position for the transition as located in the two successive scan lines. The successive morphed lines are then added to produce a single interpolated line that is interlaced between its parent lines in a resulting high-definition video signal.

Abstract: Progressive-scan video signals that are generated from interlaced-scan video signals by interpolation may be subject to temporal distortion when the interstitial interpolated lines have a different time reference than the interlaced lines. This distortion may be mitigated by detecting vertical low-frequency spatial distortion in an interpolated video signal and by generating a compensating signal that, when added to the interpolated video signal reduces that vertical low-frequency spatial distortion. A spatial low-pass filter is applied to corresponding pixels of several adjacent lines of the current field of the original interlaced image. Concurrently, a spatial low-pass filter is applied to corresponding pixels of several interpolated lines that are inserted between the lines of the interlaced image to produce the progressive image. At each pixel position, the low-pass filtered values are compared.

Abstract: A method for reordering an edited digital video sequence composed of digital video fields from multiple sources is disclosed. When the digital video sequence is reordered temporal cadence is provided which will allow for the conversion to a digital film format through a reverse 3:2 pulldown. Let Fold=(F1old,F2old, . . . ,FNold) be the given edited sequence of video fields. In one embodiment, the method calculates an instruction set which is then used to transform Fold into a new sequence of video fields, denoted Fnew, where most of the fields in Fnew come from Fold and the remaining fields are “upconverted” fields from Fold. This reconstitution of Fold is obtained by optimizing a set of instructions based on various constraints which express the characteristics of the pattern AaBbBcCdDd. By assigning a cost to each violation of the constraints, and to each disruption of the natural flow of time, and to other undesirable properties, a real-valued function is constructed.

Abstract: A method is provided for displaying progressive video content on an interlaced display device. The method comprises vertically phase shifting video lines of the progressive video content to correctly position the video lines with respect to a video field of the interlaced display device. The method further comprises scaling the video lines of progressive video content to match a vertical size of a video field of the interlaced display device.

Abstract: A coefficient data generating apparatus includes a coefficient data generator and an estimation predictive calculation circuit. The coefficient data generator generates for each class coefficient data for an estimation expression which is used to obtain horizontal and vertical resolution corresponding to parameters input from a remote control transmitter by a user. The coefficient data is stored in a coefficient data memory. The estimation predictive calculation circuit generates based on an estimation expression HD pixel data constituting an output picture signal by using other coefficient data read from the coefficient data memory, and SD pixel data of prediction taps. The coefficient data is generated by linearly adding pieces of coefficient-generating data, and the output picture signal can be obtained so as to corresponds to the input parameters. This makes it possible to freely control the resolution of a displayed picture.

Abstract: The large circuit scale problem is avoided by applying a systematic algorithm for both enlargement and reduction. A resolution conversion unit for converting the resolution of an input video signal with a magnification of M/N is provided with a storage part for storing the arithmetic result, an arithmetic part having an adding part for adding a positive integer M to an output of the storage part and a subtracting part for subtracting a positive integer N from the output of the storage part, a memory part for temporarily storing a video signal, a memory control part for generating a reading and/or writing control signal based on an output supplied from the arithmetic part, and a pixel value arithmetic part for calculating an output pixel value corresponding to a pixel value included in an input video signal based on an output supplied from the arithmetic part.