Abstract: A frequency-locked loop (FLL) logic circuit, including a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator; a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal; a clock counter configured to count a number of pulses of the oscillator clock signal during a reference time; and a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.

Abstract: HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital communications protocol, the audio quality can be impaired by analog signal impairments and distortions even if there are no digital decoding errors. In particular, the very process by which the audio is converted from Digital (HDMI) to human audible “Analog Audio” can be prone to errors. This occurs when the Digital to Analog Converter (DAC) clock, which is derived from the HDMI TMDS clock or HDMI source, is “distorted” due to its jitter, resulting in erroneous sampling or outputting of vital audio samples, thereby reducing the audio quality of the experience. The present invention reduces the jitter on the TMDS clock, and hence the audio DAC clock, resulting in lower audio distortion.

Abstract: An image signal processor and a method for processing an image signal thereof are disclosed. When the image signal processor executes an automatic chroma gain control (ACC), the image signal processor adjusts a variable rate of ACC gain according to a size of an input color signal to reduce a time for processing the ACC. Even if a difference between the size of the input color signal and the size of a reference color signal is large, the ACC is rapidly processed. As a result, transient phenomenon disappears from a screen.

Abstract: A state detector of a video device and a state detection method thereof are provided. The state detector includes a first chroma detector, a second chroma detector, and a controller. The first chroma detector and the second chroma detector operate in a first state among a plurality of states. When the second chroma detector is not capable of processing an input signal normally, the controller controls the second chroma detector to switch between the states until the second chroma detector operates in a second state to process the input signal normally, and the first chroma detector is set to operating in the second state. As a result, the quality of a displayed image is improved.

Abstract: A video horizontal synchronizer outputting a line timing signal and an indicating flag of a received video signal for use in a video signal post-processing unit, including a filter outputting a wide bandwidth filtered and a narrow bandwidth filtered signals of the received video signal, a dynamic slicer threshold generator generating a slicer threshold, a timing recovery circuit generating a phase error and the line timing signal, a phase error statistics circuit averaging the phase error to generate a average phase error, a HSYNC checker generating a matching flag indicating whether a periodic pattern appears in the narrow bandwidth filtered signal according to the line timing signal, and a finite state machine controlling the dynamic slicer threshold generator, the timing recovery circuit, the phase error statistics circuit and the HSYNC checker and generating an indicating flag when the average phase error is small enough and the matching flag is confirmed.

Abstract: An apparatus having a complex sine wave generating circuit (3) that generates a complex sine wave, a multiplying circuit (4) that multiplies an input signal by the complex sine wave, a first integrating circuit (5) that integrates the product obtained by the multiplying circuit (4) in the time direction, a first squaring circuit (6) that takes the square of the absolute value of a complex signal output by the first integrating circuit (5), a second squaring circuit (7) that takes the square of the absolute value of the instantaneous amplitude of the input signal, a second integrating circuit (8) that integrates the results obtained by the second squaring circuit (7) in the time direction, and a frequency difference calculating circuit (9) that finds the difference between the frequency of the input signal and the oscillation frequency of the complex sine wave on the basis of the ratio between the output signal level of the first squaring circuit (6) and the output signal level of the second integrating circui

Abstract: A video signal converting device is capable of converting an analog composite signal into a proper digital signal with a small delay even if the analog composite signal contains much jitter. The video signal converting device has a sampling clock output unit for outputting a sampling clock signal having a frequency which is 4n times the frequency of a burst signal contained in the analog composite signal (n represents a positive integer of 2 or greater), and an analog-to-digital converting unit for converting the analog composite signal into a digital signal based on the sampling clock signal output from the sampling clock output unit.

Abstract: A synchronization separation circuit extracts a synchronization timing signal from a video signal, and a burst gate pulse generator generates a timing pulse signal for gating a color burst signal period. In the color burst signal period restricted by the timing pulse signal, a first counter counts up cycles of a color burst signal at a first timing as a rising edge of the color burst signal and a second counter counts up cycles of the color burst signal at a second timing as a falling edge of the color burst signal. A color burst determination circuit receives count values to determine presence/absence of a color burst signal superimposed on the video signal.

Abstract: Methods for recovering high-resolution images from an analog video interface by autonomously correcting for phase errors between a synchronized clock signal to a sampling analog-to-digital converter and the input video signal. A global phase adjustment first detects video transitions in the sampled video data stream in order to determine and then select the optimum clock phase over entire video frames for rendering the pixels of the video input. This corrects for long-term phase errors, such as those from timing tolerances in circuit components and timing tolerances in the video input. A local phase adjustment selects the samples used for rendering individual pixels according to an algorithm that avoids the selection of samples that may be located within video transition regions. This corrects for short-term phase errors, such as those from jitter and phase drift on the sample clock.

Abstract: To provide a video signal processing apparatus capable of generating video signals that enable displaying and recording of a high-quality picture. A video signal processing apparatus according to an embodiment of the present invention includes a decoder decoding an input TS to generate a video signal having a field frequency fv of 60 Hz or a video signal having a field frequency fv of 59.94 Hz, and a converter converting the respective video signals into NTSC video signals having a color subcarrier the phase of which is inverted for each frame.

Abstract: A two-stage pixel skew compensation circuit for use with digital display monitors. The first stage of the compensation circuit aligns the edges of the pixels received on the color component signal lines of an analog video signal. The second stage of the de-skew compensation circuit realigns the pixels themselves so that no skew exists between the digitized video color components. The digitized video signals drive a digital video monitor.

Abstract: A digital processing system and method for tracking a subcarrier included in a video signal are provided, where a phase comparator tracks the phase of a color burst signal based on predetermined supposed phases, Y/C separation and demodulation are carried out based on a compensation phase that is updated by a phase compensator in response to the tracked phase, and the Y/C separation and demodulation are performed based on a compensation frequency determined by a frequency compensator by checking short-term and long-term variations in the updated compensation phase.

Abstract: In the known color stripe process for preventing recording of video signals, the color burst present on each line of active video is modified so that any subsequent video tape recording of the video signal shows variations in the color fidelity that appear as undesirable bands or stripes of color error. This color stripe process is improved by a combination of modifying the phase of the color burst on only part of the color burst. Additional improvements were obtained by incorporating techniques of widening the normal color burst envelope towards the trailing edge of horizontal sync and towards the beginning of active video. These techniques are useful in improving the performance of the color stripe process in both the NTSC and PAL color systems. However, additional improvements are described in the PAL system whereby the phase modifications are controlled so as to avoid disturbing the so-called PAL ID pulse.

Abstract: A video signal processing circuit that uses a prescribed clock signal to process a digitized composite video signal. A clock generating means (2) generates the prescribed clock signal; a burst phase detecting means (3) detects color subcarrier phase information (p) in each line of the composite video signal; a phase difference calculation means (4) finds the phase difference between phase information (p) from the burst phase detecting means and a prescribed reference phase; a sampling phase conversion means (8) corrects the sampling phase of the composite video signal according to phase corrections (?b, ?t) obtained from the phase difference calculation means (4); a Y/C separation means (9) separates the luminance and chrominance signals from the composite video signal output from the sampling phase conversion means (8). Excellent two- or three-dimensional Y/C separation can be obtained regardless of the television broadcast system, even from a non-standard signal.

Abstract: Phase noise mitigation in an analog video receiver implemented in an integrated circuit device. A phase correction value that indicates a phase offset between a synthesized sinusoid and a reference sinusoid conveyed in a horizontal retrace region of a composite video signal is periodically generated. A phase error that will accumulate during an interval between horizontal retrace regions of the composite video signal is estimated based, at least in part, on the phase correction value, and the phase of a chroma signal component of the composite video signal is adjusted based on the estimated phase error.

Abstract: A bracket for holding of cylindrical tanks such as emergency breathing tanks adjacent to a wall surface or behind a seat surface in a detachable manner with positive engagement released by an operative release line. An upper and lower securement strap are secured together at an engaging tab which straps extend around the tank when the tab is engaged and can be easily released for rapid exit. A webbing extends between the upper and lower securement straps for minimizing any entanglements or catching of the straps on protruding portions of the tank.

Abstract: A system and method for automatically controlling color synchronization polarity during video decoding. Various aspects of the present invention may comprise at least one module that is adapted to monitor color synchronization polarity at a plurality of instances over a period of time. The at least one module may also, for example, be adapted to generate a sequence of signals indicative of the color synchronization polarity correctness at the plurality of instances. The at least one module may additionally, for example, be adapted to statistically analyze the sequence of signals. The at least one module may further, for example, be adapted to determine, based at least in part on the statistical analysis of the sequence of signals, whether color synchronization polarity is correct. The at least one module may still further, for example, be adapted to control color synchronization polarity based, at least in part, on the polarity correctness determination.

Abstract: A video signal processing apparatus comprises a component video signal demodulator to demodulate a component video signal sampled by a burst lock clock signal from a composite video signal sampled by the burst lock clock signal, the burst clock signal having multiplied frequency of a color subcarrier in the composite video signal having an auxiliary digital data signal inserted therein, and a re-sampling unit to convert sampling frequency of the component video signal selectively to a first frequency equal to or multiplied by horizontal synchronization frequency of the composite video signal or to a second frequency equal to or multiplied by frequency of the auxiliary digital data signal.

Abstract: A system and method for determining phase of a subcarrier (e.g., a jittering video subcarrier). Various aspects of the present invention may comprise determining at least one weighting factor based, at least in part, on a subcarrier synchronization signal (e.g., a video synchronization signal). A first subcarrier phase sample and at least a second subcarrier phase sample may then be obtained. Subcarrier phase may then be determined by interpolating between the first subcarrier phase sample and the second subcarrier phase sample, where such interpolation (e.g., linear interpolation) may be based, at least in part, on the determined weighting factor(s).

Abstract: We describe and claim an adaptive color burst phase correction system and method. The adaptive color burst phase correction system includes a signal detector to extract a color burst from a video signal, the color burst including a phase and an amplitude, an adaptive phase corrector to adjust the color burst phase responsive to corruption in the color burst, a Y/C separator to separate luminance and chrominance data from the video signal, responsive to the adjusted color burst phase, and a panel to display the luminance and chrominance data. The adaptive phase corrector includes a corruption detector to detect corruption in a color burst, a selector to select a phase correction value responsive to the detected corruption, and a phase adjuster to adjust a color burst phase responsive to the phase correction value.

Abstract: Video decoder systems in which both the analog-to-digital converter and the composite decoder are driven by the stable sample clock, such as a crystal source. The outputs of the composite decoder are provided to a source rate converter, having an output that is provided to a digital output formatter. The digital output formatter is driven by the output clock, which may be locked to the source clock if desired. The output clock is developed by a clock generator which may be one of several different types, including a fractional N synthesizer, a direct digital synthesizer or a puncture clock.

Abstract: Chrominance phase error correction circuitry includes a demodulator for demodulating a received video color burst signal into first and second demodulated signals and signal generation circuitry for providing to the demodulator a demodulating signal for demodulating video color burst signal. Phase correction circuitry detects a phase error from the first and second demodulated signals and varies a phase of the demodulating signal to provide a corrected demodulating signal for demodulating a video chrominance signal with the demodulator during an active video period.

Abstract: A color frame identifier circuit generates a pseudo-subcarrier signal and compares the pseudo-subcarrier signal to a sliced color burst of at least one selected line in a video frame. Based on this comparison, a processing circuit determines the color frame.

Abstract: When performing A/D conversion on image signals, when reducing noise that is caused by jitter by adjusting the phase of the sampling clocks, even if the input waveform has considerable waveform distortion such as a triangular wave, it is possible to reliably reduce this noise. Input analog image signals are converted into digital image data using sampling clocks from a PLL circuit by A/D conversion means. Next, image data that has delayed by a 1 clock delay circuit is subtracted from the digital data by a subtracter. The maximum value of one screen of the subtracted output is then determined, and 5 is subtracted therefrom to provide a threshold value. A comparator compares the subtracted output and the threshold value, and outputs a signal when the subtracted output is greater than the threshold value. A counter then supplies the count value of these signals to a CPU, and the CPU controls the phases of the sampling clocks using a switch.

Abstract: A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst signal where dramatic changes in the pixel clock frequency result.

Abstract: A sync generator (genlock) (10) for frequency and phase locking an incoming video signal to a system clock (12) includes a digitizer (16, 22) for digitizing the incoming video signal to yield a digitized color sub-carrier burst component. A numerically controlled oscillator (15) clocked by the system clock generates a phase lock reference signal for locking to the incoming video signal. Phase detection means logic unit (42, 74) sense a static phase offset magnitude from an ideal 90° phase offset between the digitized color sub-carrier burst component and the numerically controlled oscillator output signal. In accordance with the sensed static offset, a static phase error nulling circuit (70) generates a compensating offset in accordance for input to the system clock (27) to drive the static offset to zero, thus achieving frequency and phase locking.

Abstract: A vector waveform rotation device (60) for rotating a vector waveform displayed on a vector comprises rotation amount setting means (5?) for holding a rotation amount ?, and means (6?) for inputting a first color difference signal (B-Y signal) and a second color difference signal (R-Y signal) demodulated from a chrominance signal of a composite video signal as x and y, and rotating a vector (x, y) by generating a vector (x?,y?)=(x·cos ??y·sin ?, x·sin ?+y·cos ?) from the vector (x,y)=(first color difference signal, second color difference signal).

Abstract: A color demodualation device having an AD converter, a phase signal generator, a burst data generator and a multiplier. The AD converter produces digital samples of chrominance signal at a frequency four times a color subcarrier frequency, and the phase signal generator generating a phase signal for identifying phases of a burst signal and color subcarrier signals modulated by respective B-Y and R-Y signals. The burst data generator produce burst data corresponding to the burst signals modulated by respective B-Y and R-Y signals. The burst respective color subcarrier signals according to the phase signal. The multiplier produces products of the burst data and the digital samples of the chrominance signal, from which digital samples of the respective R-Y and B-Y signals are produced.

Abstract: Digital broadcasting receiver, and method for compensating a color reproduction error therein, the digital broadcasting receiver including a channel decoder, a TP part for demultiplexing a TP stream from the channel decoder for being provided with a PCR (Program Clock Reference), and receiving a receiver side STC (System Time Clock), and providing a PCR jitter which is a difference between the PCR and an STC value, an STC compensating part for providing the STC value to the TP part from a system clock, and varying the system clock so that the PCR value and the STC value are identical, to generate a reference system clock in which the PCR jitter value becomes ‘0’, a decoder for receiving the reference system clock from the STC compensating part, and decoding a received picture, a display clock generator for providing a display clock generated by receiving the reference system clock as singular system clock, a video format and display processor for receiving the reference system clock and the display clock, and

Abstract: A PLL circuit compares a PCR with the output frequency of a voltage controlled oscillator (VCO), and returns a voltage value which is the result of the comparison to the VCO, so that a reference clock corresponding to the PCR is outputted from the VCO. A switch supplies a control voltage from the PLL circuit to the VCO when digital broadcasting is viewed, while feeding a fixed voltage from a fixed voltage power supply to the VCO when analog broadcasting is viewed, to stably output a clock having a frequency of 27 MHz irrespective of the change in the PCR.

Abstract: A FIFO memory receives data transfer requests before data is stored in the FIFO memory. Multiple concurrent data transfers, delivered to the FIFO memory as interleaved multiple concurrent transactions, can be accommodated by the FIFO memory (i.e., multiplexing between different sources that transmit in distributed bursts). The transfer length requirements associated with the ongoing data transfers are tracked, along with the total available space in the FIFO memory. A programmable buffer zone also can be included in the FIFO memory for additional overflow protection and/or to enable dynamic sizing of FIFO depth.

Abstract: An apparatus to compensate a color carrier in an image processing system to convert an input analog image signal into a digital image signal includes a detector, a phase-locked loop unit, a difference detector, and a color signal processor. The detector detects a frequency of the color carrier in a color signal of the digital image signal. The phase-locked loop unit generates a subcarrier frequency by performing a phase-locked loop operation on a system clock signal applied to the image processing system. The difference detector detects a difference between the frequency of the color carrier and the subcarrier frequency. The color signal processor compensates for a phase deviation of the color carrier of the color signal using the subcarrier frequency generated by the phase-locked loop unit.

Abstract: A broadcast data receiver (BDR) is provided and a method of using the BDR for the production of a pseudo stable reference control for the reliable generation of composite video signals. The BDR receives video, audio and/or auxiliary data from a broadcaster can stored a part of all of the data in storage means, typically in the form of a hard disk drive. When the BDR is deriving video data from the hard disk due to the BDR being disconnected from the signal feed from the broadcaster, the BDR uses a pseudo stable reference produced by deriving one or more values from stable frequency information embedded in incoming data. The pseudo stable reference is used to control the frequency of a VCXO in the BDR, thereby allowing accurate color sub-carrier frequency generation for the generation of a final video output.

Abstract: A pixel clock frequency is adjusted in response to periodically monitoring the relative positions between a video signal to be displayed and a video signal captured. Image shear of the display signal may be avoided quickly. Adjustments are made to the color burst signal where dramatic changes in the pixel clock frequency result.

Abstract: In accordance with an embodiment of the present invention a microprocessor in the horizontal phased lock loop reads the horizontal timing with respect to the sync input and provides an increment inch to the horizontal discrete time oscillator to make corrections in its timing to maintain lock to the sync input. The horizontal discrete time oscillator output is used to produce a pixel clock which drives the color discrete time oscillator in a color phased locked loop. A microprocessor reads a phase error between the color burst input and the color local oscillator frequency and writes an increment incsc to the color discrete time oscillator to maintain lock to the color burst. The horizontal phase locked loop adjusts inch that varies about nominal increment (nom_inch) by ?h. The feed forward error correction for the adjustment to the color discrete time oscillator is the nomimal increment (nom_incsc) and a feed forwarded scaled version of ?h.

Abstract: A video decoder for decoding a composite video signal. The decoder includes an analog-to-digital converter (ADC), an input resampler, and a Y/C separator, all coupled in series. The ADC receives and digitizes the composite video signal to generate ADC samples. The input resampler receives and resamples the ADC samples with a first resampling signal to generate resampled video samples. The Y/C separator receives and separates the resampled video samples into luminance and chrominance components. The Y/C separator includes a delay element configured to receive the resampled video samples and provide a variable amount of delay. The variable amount of delay can be adjustable from line to line, and is typically based on an approximated duration of a video line.

Abstract: A photographic and video image system for transforming an image on a frame of a photographic film includes a structure in the overall form of a photographic printer having an image transformation element that transforms an optical image from the film into a video signal, a frame position indicator, which can be a hole or an optical or magnetic signal, is recorded on the film along with aspect information relating to the size of the frame exposed on the film. The frame position indicator and aspect information are detected and used to control a film feeding operation and the optical image to video signal transformation operation. The user of the system can record order information on the film that is used to specify the aspect of the resultant photographic print, as well as the quantity of prints to be made. Such order information can be superimposed as a menu on a displayed video signal at the time the video signal is reviewed prior to producing a photographic print.

Abstract: A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal.

Abstract: The present invention relates to a digital photo album having a hard drive and built-in scanner configured to scan photographic prints. The digital photo album allows a user to save the photographic prints as digital images on the hard drive, or another medium, and then view individual images or play photo album slideshows comprising a plurality of digital images. Additionally, a user may upload digital images from an external medium to the hard drive of the photo album, and then view those images and/or include them in a playlist. The digital photo album of the present invention advantageously allows a user to scan photographic prints, upload or download digital images, and view digital images individually or in an album format, in a substantially automated manner and without the need for complex peripheral devices.

Abstract: In a conventional construction to obtain a reference signal for a tuner and a subcarrier for color difference signal demodulation by only one quartz oscillator, the reference signal is unstable due to a PLL operation for oscillation of the subcarrier, which causes tuning error or tuning shift. To realize stable tuning operation, in an oscillation signal processing apparatus having a construction to use one quartz oscillator to obtain a reference signal for a tuner and a subcarrier to demodulate a color difference signal, a PLL operation is performed with the quartz oscillator and a color burst signal when the tuning operation is not performed, while a phase comparison operation is stopped and oscillation is fixed to 3.58 MHz when the tuning operation is performed.

Abstract: A technique to stabilize subcarrier generation in a line-locked digital video system, caused by simultaneous locking of the genlock device causing continuous changing of a shared clock signal, by calculating a time shift occurring in an output waveform, converting the time shift into an equivalent phase shift and sending a corresponding phase correction number to a waveform generator block to correct the time shift, and thus stabilize subcarrier generation.

Abstract: An apparatus to compensate a color carrier in an image processing system to convert an input analog image signal into a digital image signal includes a detector, a phase-locked loop unit, a difference detector, and a color signal processor. The detector detects a frequency of the color carrier in a color signal of the digital image signal. The phase-locked loop unit generates a subcarrier frequency by performing a phase-locked loop operation on a system clock signal applied to the image processing system. The difference detector detects a difference between the frequency of the color carrier and the subcarrier frequency. The color signal processor compensates for a phase deviation of the color carrier of the color signal using the subcarrier frequency generated by the phase-locked loop unit.

Abstract: A color signal reproducing circuit having A/D converter 101, sync separator 102, YC separator 103, gain controller 105, multipliers 106 and 107, low-pass filters 108 and 109, burst-period cumulative adders 110 and 111, SINCOS generator 112, clock generator 113, and ramp-wave generator 114. The simple structure allows a color signal reproducing circuit to be used commonly in a different television systems without changing its clock frequency considerably in accordance with broadcasting systems and also achieves YC separation and color signal demodulation from analog composite signal with a higher degree of precision.

Abstract: A PLL circuit which outputs an oscillation clock signal synchronous with a reference clock includes a phase lock detector for detecting if the oscillation lock signal is synchronous with the reference clock. If the phase lock detector detects a phase difference between the oscillation clock signal and the reference clock, a charge pump circuit is used to alter the oscillation clock signal so that the oscillation signal is placed back in sync with the reference clock. The charge pump selects one of a ground potential and a power supply potential in response to a comparison result of the oscillation clock signal and the reference clock. The charge pump pulls a constant current to ground from an output terminal of the charge pump ,circuit when the ground potential is selected and supplies a constant current to the output terminal of the charge pump circuit when the power supply potential is selected, thereby producing an output which alternately repeats the ground potential and the power supply potential.

Abstract: There is provided a UHF/VHF tuner in which complication in structure and increase in manufacturing costs are suppressed and broadcast receiving performance is improved by reducing variation in the reception sensitivity according to frequency when broadcast in the VHF band is received. In a UHF/VHF tuner for receiving both of a broadcast in the UHF band and a broadcast in the VHF band, one mixer and one UHF local oscillator are used for the broadcast in the UHF band, and one mixer, a VHF high-band local oscillator which is switched to be connected when the high band is selected and a VHF low-band local oscillator which is switched to be connected when the low band is selected are used for the broadcast in the VHF band.

Abstract: An embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a first comparator for generating a first error signal and a second comparator for generating a second error signal. The first and second comparators are coupled to an oscillator configured to receive the first and second error signals and generate the signal having a predetermined frequency. Another embodiment of the present invention provides a signal generator for generating a signal with a predetermined frequency. The signal generator includes a counter for generating a first count, Q_last. The counter is coupled to a ratio counter which generates a signal having a value less than or equal to Q_last. The contents of the ratio counter represent the phase of the signal having a predetermined frequency. The ratio counter outputs the signal having a predetermined frequency.

Abstract: An apparatus and method is provided for generating VBI data coding waveforms. The present invention utilizes a single look-up table that stores sampled values of sine waves in direct waveform synthesis for both color burst processing and VBI data coding processing. Furthermore, the present invention utilizes a 2T pulse as a signalling waveform in direct synthesis to overcome the problem of overlap for conventional unit pulse durations.

Abstract: A microprocessor controlled color phase locked loop is provided which provides flexibility and adaptability for different television standards and sampling rates. Color burst phase error and color burst amplitude information are stored in data registers located at the output of the phase locked loop's low pass filter rather than at the output of the color demodulator.

Abstract: In accordance with an embodiment of the present invention a microprocessor in the horizontal phased lock loop reads the horizontal timing with respect to the sync input and provides an increment inc h to the horizontal discrete time oscillator to make corrections in its timing to maintain lock to the sync input. The horizontal discrete time oscillator output is used to produce a pixel clock which drives the color discrete time oscillator in a color phased locked loop. A microprocessor reads a phase error between the color burst input and the color local oscillator frequency and writes an increment inc sc to the color discrete time oscillator to maintain lock to the color burst. The horizontal phase locked loop adjusts inch that varies about nominal increment (nom_inch) by &Dgr;h. The feed forward error correction for the adjustment to the color discrete time oscillator is the nonimal increment (nom_incsc) and a feed forwarded scaled version of &Dgr;h.

Abstract: A technique to stabilize subcarrier generation in a line-locked digital video system, caused by simultaneous locking of the genlock device causing continuous changing of a shared clock signal, by calculating a time shift occurring in an output waveform, converting the time shift into an equivalent phase shift and sending a corresponding phase correction number to a waveform generator block to correct the time shift, and thus stabilize subcarrier generation.